The document discusses PIC18 microcontroller architecture. It covers the Harvard architecture used by PIC microcontrollers which separates program and data memory. It provides an example of the memory layout of a PIC18F452 microcontroller, which has 32K bytes of program flash memory addressable from 0 to 7FFFH and 4K bytes of data memory addressable from 0 to FFFH. The document also describes the microprocessor unit, registers, I/O ports, and instruction set of PIC18 microcontrollers.
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The document discusses PIC18 microcontroller architecture. It covers the Harvard architecture used by PIC microcontrollers which separates program and data memory. It provides an example of the memory layout of a PIC18F452 microcontroller, which has 32K bytes of program flash memory addressable from 0 to 7FFFH and 4K bytes of data memory addressable from 0 to FFFH. The document also describes the microprocessor unit, registers, I/O ports, and instruction set of PIC18 microcontrollers.
The document discusses PIC18 microcontroller architecture. It covers the Harvard architecture used by PIC microcontrollers which separates program and data memory. It provides an example of the memory layout of a PIC18F452 microcontroller, which has 32K bytes of program flash memory addressable from 0 to 7FFFH and 4K bytes of data memory addressable from 0 to FFFH. The document also describes the microprocessor unit, registers, I/O ports, and instruction set of PIC18 microcontrollers.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online from Scribd
The document discusses PIC18 microcontroller architecture. It covers the Harvard architecture used by PIC microcontrollers which separates program and data memory. It provides an example of the memory layout of a PIC18F452 microcontroller, which has 32K bytes of program flash memory addressable from 0 to 7FFFH and 4K bytes of data memory addressable from 0 to FFFH. The document also describes the microprocessor unit, registers, I/O ports, and instruction set of PIC18 microcontrollers.
Copyright:
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Download as PPT, PDF, TXT or read online from Scribd
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Chapter 2
Microcontroller Architecture PIC18F Family
Harvard Architecture Von Neumann Architecture
Von Neumann Architecture:
8-bit Bus
CPU Harvard Architecture
Program & Data Memory
Fetches instructions and data from a single memory space Limits operating bandwidth
Harvard Architecture:
8-bit Bus
Data Memory
16-bit Bus
CPU
Uses two separate memory spaces for program instructions and data Improved operating bandwidth Allows for different bus widths
Program Memory
PIC18F Microcontroller Families
PIC microcontrollers are designed using the Harvard Architecture which includes:
Microprocessor unit (MPU) Program memory for instructions Data memory for data I/O ports Support devices such as timers
Microcontroller with the Harvard Architecture
PIC18F452/4520 Memory - Example
Program Memory: 32 K (215)
Address range: 000000 to 007FFFH 16-bit registers
Data Memory: 4 K
Address range: 000 to FFFH 8-bit registers
Not part of the data memory space Addressed through special function registers
Design a micro controller with the following specifications Specify bus widths.
Program Memory: 32 K Data Memory: 4 K
In your design show where the counter registers are located In your design show where the working registers are located (which part of the microprocessor unit) Show where the read/write lines are connected to specify the direction of each.
32 K (215)
PIC18F MCU and Memory Design Problem Design a micro controller with the following specifications Specify bus widths.
Program Memory: 32 K (215)
Address range: 000000 to 007FFFH 16-bit registers
Data Memory: 4 K
Address range: 000 to FFFH 8-bit registers
32 K (215)
Microprocessor Unit (1 of 3)
Includes Arithmetic Logic Unit (ALU), Registers, and Control Unit
Arithmetic Logic Unit (ALU)
WREG working register Status register that stores flags Instruction decoder when the instruction is fetched it goes into the ID
Microprocessor Unit (2 of 3)
Registers
Bank Select Register (BSR)
4-bit register used in direct addressing the data memory
File Select Registers (FSRs)
16-bit registers used as memory pointers in indirect addressing data memory 21-bit register that holds the program memory address while executing programs
Program Counter (PC)
Microprocessor Unit (3 of 3)
Control unit
Provides timing and control signals to various Read and Write operations
PIC18F - Address Buses
Address bus
21-bit address bus for program memory addressing capacity: 2 MB of memory 12-bit address bus for data memory addressing capacity: 4 KB of memory
Data Bus and Control Signals
Data bus
16-bit instruction/data bus for program memory 8-bit data bus for data memory Read and Write
Control signals
Examples
Refer to your notes!
Instructions 8-bit Program Memory
8-bit Instruction on typical 8-bit MCU
Example: Freescale Load Accumulator A: 2 Program Memory Locations 2 Instruction Cycles to Execute
Example: Move Literal to Working Register 1 Program Memory Location 1 Instruction Cycle to Execute
movlw k 0
0 0
0 1
Separate busses allow different widths 2k x 16 is roughly equivalent to 4k x 8
Flash (4K) EEPROM can be accessed individually 36 I/O ports F FLASH C EPROM
PIC18F452/4520 Memory
Program memory with addresses (Flash)
Data memory with addresses Also called Data Register or File Register
FFF=212=16x256=4096=4K
PIC18F452/4520 Data Memory with Access Banks
Three ways to access data registers:
Direct using Bank Select Registers (BSR)
Bank address (4-bit) + Instruction (8-bit) FSR contains the address of the data register Hence, MPU uses FSR
Indirect using File Select Registers (FSR)
Access Bank using General Purpose Registers (GPR)
Data Memory Organization
FFF=212=16x256=4096=4K
000h 07Fh 080h 0FFh 100h
Access RAM Bank 0 GPR
PIC16F8F2520/4520 Register File (data memory) Map
Bank 1 GPR 1FFh 200h
Data Memory up to 4k bytes
Data register map - with 12bit address bus 000-FFF
Bank 2 GPR 2FFh
Access Bank Access RAM (GPR) Access SFR
00h 7Fh 80h FFh
Divided into 256-byte banks There are total of F banks Half of bank 0 and half of bank 15 form a virtual bank that is accessible no matter which bank is selected
D00h
Bank 13 GPR DFFh E00h
256 Bytes
Bank 14 GPR EFFh F00h F7Fh F80h FFFh
GPR=General Purpose Reg. SFR=Special Function Reg.
Bank 15 GPR Access SFR
PIC18F452 I/O Ports
Five I/O ports
PORT A through PORT E Most I/O pins are multiplexed Generally have eight I/O pins with a few exceptions Addresses already assigned to these ports in the design stage Each port is identified by its assigned Special Function Registers (SFR) look at the previous slide
PORTA (address of F80) PORTB (address of F81) these are part of data memory or register file
TRISB must be set to specify signal direction of PORT B.
Processes and Conditions of Data Transfer
Interrupt is a process of communication between two devices
If provides efficient communication between the two devices Examples: Sending a file to a printer, pressing a key on the key board
A value is loaded in the register and continue changing at every clock cycle time can be calculated Can count on rising or falling edge There are several timers: 8-bit, 16-bit Controlled by SFR Serial interface supporting RS232 Another serial data communication
Master Synchronous Serial Port (MSSP)
Addressable USART
A/D converter Parallel Slave Port (PSP) Capture, Compare and PWM (CCP Module)
ToCON
PIC18F Special Features
Sleep mode
Power-down mode Able to reset the processor if the program is caught in unknown state (e.g., infinite loop) EEPROM can be protected through SFR
Watchdog timer (WDT)
Code protection
In-circuit serial programming In-circuit debugger
PIC18F4X2 Architectur e Block Diagram
PIC16F87 Architecture Block Diagram
Table 2-1
Questions - Table 2-9 (pp. 46 and 48)
How much of flash memory can be accessed? 13 bit 8K (1FFF) 9bit 512 Byte Effective address bus from data memory ? How many instruction sets can PIC16F687 be accessed? 35 It has no multiplication! compare Figure 2-8 and 2-9
PIC18F Instructions and Assembly Language
Has 77 instructions
Earlier PIC family of microcontrollers have either 33 or 35 instructions (Table 2-1)
In PIC18F instruction set, all instructions are 16-bit word length except four instructions that are 32-bit length
Instruction Description and Illustrations
Copy (Load) 8-bit number into W register
Mnemonics: MOVLW 8-bit Binary format:
0000 1110 XXXX XXXX (any 8-bit number) Copy Contents of W register in PORTC
Mnemonics: MOVWF PORTC, a
(a indicates that PORTC is in the Access Bank)
Binary format:
0000 1110 1000 0010 (82H is PORTC address)
Opcode 8-bit Literal 8-bit
Instruction
Instruction Set Overview
Literal and Control Operations 15 8 7 Literal Value
Opcode
k OR
Opcode
MOVLW
0 x25 Literal Value
Illustration: Displaying a Byte at an I/O Port (1 of 5)
Problem statement:
Write instructions to light up alternate LEDs at PORTC. PORTC
Hardware:
bidirectional (input or output) port; should be setup as output port for display
Logic 1 will turn on an LED in Figure 2.10.
Illustration (2 of 5)
TRISC=0
Interfacing LEDs to PORTC Port C is F82H Note that PORT C is set to be an output! Hence, TRISC (address 94H) has to be set to 0
Illustration (3 of 5)
Program (software)
Logic 0 to TRISC sets up PORTC as an output port Byte 55H turns on alternate LEDs
;Load W register with 0 ;Set up PORTC as output ;Byte 55H to turn on LEDS ;Turn on LEDs ;Power down
PIC18 Simulator
Using the Program Memory editor type in the opcode MOVLW 00 and MOWWF TRISC,0 as described in page 52 of your textbook. Run the program in step-by-step mode and observe the PC. Observe how the NEXT INSTRUCTION changes. What is the value of final clock cycle? How long does it take to complete the program in sec.?
PIC18 Simulator IDE
Questions - PIC18 Simulator IDE
What is the address for TRISC? SFR F94 What is the address for PORTE? How many SFR registers we have? FFF-F80 How many GPR? 000-5FF How many bit PC has? Compare with Fig 2-8
