BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
In this chapter, several types of combinational logic functions are introduced including adders,
comparators, decoders, encoders, code converters, multiplexers (data selectors), demultiplexers, and
parity generators/checkers.
The Half-Adder
The half-adder accepts two binary digits on its inputs and produces two binary digits on its outputs—a
sum bit and a carry bit. A half-adder is represented by the logic symbol in Fig 1
.
Fig 1.
Rules for binary addition.
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Block diagram of Full Adder
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
BCD to Excess-3 conversion
The process of converting BCD to Excess-3 is quite simple from other conversions. The Excess-3 code
can be calculated by adding 3, i.e., 0011 to each four-digit BCD code. Below is the truth table for the
conversion of BCD to Excess-3 code. In the below table, the variables A, B, C, and D represent the bits
of the binary numbers. The variable 'D' represents the LSB, and the variable 'A' represents the MSB. In
the same way, the variables w, x, y, and z represent the bits of the Excess-3 code. The variable 'z'
represents the LSB, and the variable 'w' represents the MSB. The 'don't care conditions' is expressed by
the variable 'X'.
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Now, we will use the K-map method to design the logical circuit for the conversion of BCD to Excess-3
code as:
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Comparator
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than, or greater than the other
binary number.
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Fig 1 bit Comparator Circuit
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Fig 6.3
Implement the following truth table using 8:1 MUX
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Fig 6.4
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
OR Gate implementation using 2:1 MUX
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
AND Gate implementation using 2:1 MUX
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Implementation of 3 to 8 Decoder circuit
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Encoder
An Encoder is a combinational circuit that performs the reverse operation of a Decoder. It has a
maximum of 2n input lines and ‘n’ output lines, hence, it encodes the information from 2 n inputs into
an n-bit code.
Types of Encoders
There are different types of Encoders which are mentioned below.
• 4 to 2 Encoder
• Octal to Binary Encoder (8 to 3 Encoder)
• Decimal to BCD Encoder
• Priority Encoder
4 to 2 Encoder
The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0, and two outputs A1 & A0. At any time, only
one of these 4 inputs can be ‘1’ in order to get the respective binary code at the output. The figure
below shows the logic symbol of the 4 to 2 encoder.
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Octal to Binary Encoder (8 to 3 Encoder)
The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs: Y7 to Y0 and 3 outputs: A2, A1 & A0.
Each input line corresponds to each octal digit value and three outputs generate corresponding binary
code. The figure below shows the logic symbol of octal to the binary encoder.
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Decimal to BCD Encoder
The decimal-to-binary encoder usually consists of 10 input lines and 4 output lines. Each input line
corresponds to each decimal digit and 4 outputs correspond to the BCD code. This encoder accepts the
decoded decimal data as an input and encodes it to the BCD output which is available on the output
lines. The figure below shows the logic symbol of the decimal to BCD encoder :
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Priority Encoder
A priority encoder is an encoder circuit in which inputs are given priorities. When more than one inputs
are active at the same time, the input with higher priority takes precedence and the output
corresponding to that is generated. Let us consider the 4 to 2 priority encoder as an example. From the
truth table, we see that when all inputs are 0, our V bit or the valid bit is zero and outputs are not used.
The x’s in the table show the don’t care condition, i.e, it may either be 0 or 1. Here, D3 has highest
priority, therefore, whatever be the other inputs, when D3 is high, output has to be 11. And D0 has the
lowest priority, therefore the output would be 00 only when D0 is high and the other input lines are
low. Similarly, D2 has higher priority over D1 and D0 but lower than D3 therefore the output would be
010 only when D2 is high and D3 are low (D0 & D1 are don’t care).
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Implementation –
It can clearly be seen that the condition for valid bit to be 1 is that at least any one of the inputs should
be high. Hence,
V = D0 + D1 + D2 + D3
X = D2 + D3
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
For Y:
Y = D1 D2’ + D3 Hence, the priority 4-to-2 encoder can be realized as follows:
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
Difference between Encoder and Decoder
Encoder
1. Purpose: Converts data from one format to another, typically compressing or transforming it
into a more efficient representation.
2. Input: Original data, such as a message, signal, or high-dimensional data.
3. Output: Encoded data, usually in a compact, standardized, or obfuscated form.
Decoder
1. Purpose: Reverses the encoding process to recover the original or a close approximation of the
original data.
2. Input: Encoded data, which may be compressed or transformed.
3. Output: Decoded data, ideally matching the original data or reconstructing it in a meaningful
way.
Parity Generators/Checkers
Errors can occur as digital codes are being transferred from one point to another within a digital system
or while codes are being transmitted from one system to another. The errors take the form of undesired
changes in the bits that make up the coded information; that is, a 1 can change to a 0, or a 0 to a 1,
because of component malfunctions or electrical noise. In most digital systems, the probability that
even a single bit error will occur is very small, and the likelihood that more than one will occur is even
smaller.
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
BRAINWARE UNIVERSITY
School of Engineering
Department of Computer Science & Engineering – Cyber Security & Data Science
398, Ramkrishnapur Road, Barasat, North 24 Parganas, Kolkata - 700 125
[BES 00018] Class Note Applied Digital Logic Design
9-BIT PARITY GENERATOR/CHECKER
2024-25 Prepared by: Faculty of CSE-CSDS Department (Brainware University, Barasat)
