DIGITAL SYSTEM DESIGN – 20ECE102
ECE II -Year I -Sem R20 DSD Question bank
Part A (Short answer question) – Unit 1 - 2
1. Write the distributive Law for Boolean function?
2. Write the gray code for the binary equivalent of (33)10.
3. Represent +49 and -49 in signed binary representation.
4. Define the following terms: (i) SOP (ii) POS.
5. Define race around condition.
6. Convert decimal (153)10 to equivalent octal number system.
7. Convert (53)10 to EXESS-3 code
8. Write the limitation of Half Adder.
9. Find 10’s complement of the decimal numbers 72532 and 3250.
10. Write De Morgan’s Theorem.
11. Define a combinational circuit
12. Draw the circuit for 1 bit comparator.
13. Express the following numbers in decimal: (a) (10110.0101)2 (b) (16.5)16
14. Draw OR Gate using NAND Gate
15. Write the Boolean expression for sum and carry for a half adder.
16. Write 9’s &10’s complement of decimal number 5674.
17. Convert 1100 to Gray code.
18. What are the advantage of logic minimization?
19. Write the truth table of EX-OR gate.
Part B (Long answer question)
UNIT 1
1. Determine the minimum SOP expression using K-map for the function f= Σm (7, 9, 10, 11, 12,
13, 14, 15) and realize the minimized function using only NAND gates.
2. (i) Perform the following operations using 2’s Complement method.
(a) 48-23 (b) 23-48 (c) 48-(-23)
(ii)Express the following numbers in decimal:
(a) (10110.0101)2 (b) (16.5)16
3. Applying K-Map reduction technique design an Excess 3 to Binary code converter.
4. Why NAND and NOR is called as Universal Gate? Design all gates using NAND & NOR itself.
5. Simplify the following Boolean expression: (i) Using laws of Boolean algebra
(a) AB+AB’C+AB’C’ (b) ABC’+ABC+A’BC
(ii) Using K-map F (A, B, C, D) = Σ m (0, 1, 3, 5, 6, 11, 13) + d (4, 7).
6. The state of an 8-bit register is 10010111. Determine is its content if it represents?
i. Two decimal digits in BCD?
ii. Two decimal digits in excess-3 code?
iii. Two decimal digits in 8-4-2-1 code?
7. Simplify the following functions using laws of Boolean algebra.
i) XY+XY’Z+XY’Z’ ii) Y = (A+B) (A+C’) (B’+C’)
ii) AB’+ABC’+AB’C’D iv) XY+XY’+X’Y
8. Simplify the following Boolean expression: (i) Using laws of Boolean algebra
(a) ABC’+ABC+A’BC (b) F = A+B [AC+(B+C’)D]
(ii) Using K-map F(w,x,y,z)=∑(1,3,7,11,15) +∑d(0,2,5)
9. Express the following numbers in decimal form: (i) (10110.0101)2 (ii) (16.5)16 (iii) (26.24)8
(iv) (ABCD.E) 16.
UNIT 2
1. Design Look ahead Carry Adder and write the advantage of Look ahead Carry Adder as
compared to parallel adder? .
2. Represent the decimal number 54 and 37 in 8-bit BCD format and compute their BCD sum.
Implement the combination logic circuit for implementing BCD addition of above two
numbers.
3. (I) Design 8x1 MUX using gates. (Ii) Implement 16x1 MUX by using 4x1 MUX.
4. Design a Decimal to BCD Encoder & Binary to octal Decoder
5. (I) Design 4x1 multiplexer using gates
(ii) Implement a 16×1 multiplexer using 4×1 multiplexer.
6. (I) Design a Full Adder circuit using gates
(ii) Implement the Full Adder using 3x8 decoder and OR gates.
7. Explain 3x8 Decoder & 8x3 Encoder with truth table and logic diagram.
8. Implement a full adder circuit using (i) two 4X1 multiplexers (ii) one 3X8 Decoder and two
OR gate.
9. Design a 4 bit parallel adder using Full adder and also modify the diagram to perform 4 bit
parallel Subtraction. Explain the operation in both circuit.
10. Implement the following Boolean function F=xy+x’y’+y’z :
a. With NAND gates. b. With NOR gates
