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HW 5

The document outlines Homework 5 for CSEE 3827, which includes five problems related to CPU time calculations, execution time variables, and the implementation of specific MIPS instructions. Students are tasked with calculating expected CPU time for a program, identifying minimal variable subsets, and designing hardware implementations for new instructions. Additionally, it explores the trade-offs between hardware and software implementations for certain operations.

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10 views2 pages

HW 5

The document outlines Homework 5 for CSEE 3827, which includes five problems related to CPU time calculations, execution time variables, and the implementation of specific MIPS instructions. Students are tasked with calculating expected CPU time for a program, identifying minimal variable subsets, and designing hardware implementations for new instructions. Additionally, it explores the trade-offs between hardware and software implementations for certain operations.

Uploaded by

Tugas Utomo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CSEE 3827: Homework 5 Due: 4/20/11

1. Suppose you wish to run a program P with 7.5 × 109 instructions on a 5GHz machine with a CPI of
0.8. What is the expected CPU time?

2. For the following set of variables, identify all of the subsets that can be used to calculate execu-
tion time. Each subset should be minimal (i.e., it should not contain any unnecessary variables.
CP I, clockrate, cycletime, numberof instructionsinprogram, numberof cyclesinprogram
3. Show how to add the linc (“load increment”) instruction to the single-cycle MIPS processor. Start
from the base processor implementation shown on the last page of this assignment. This instruction
corresponds to the following sequence of two instruction: lw $rt, L($rs) then addi $rs, $rs, 1.
Add all necessary datapaths and control signals to the processor.
4. Show how to implement the instruction swap $rs, $rt, which swaps the contents of registers $rs and
$rt. As before, start your design from a clean base processor.
5. One could always have executed two instructions to carry out the swap operation. Call this the software
implementation of swap. Imagine your hardware implementation of swap (from the previous problem)
increased the clock period by 10%. What percentage of swap operations in the instruction mix would
make it worthwhile to implement in hardware rather than using the two software instructions?

1
Datapath:

Control (Main Decoder):


Instruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0

R-type 000000 1 1 0 0 0 0 10
lw 100011 1 0 1 0 0 0 00
sw 101011 0 X 1 0 1 X 00
beq 000100 0 X 0 1 0 X 01
Control (ALU Decoder):

ALUOp1:0 Funct ALUControl2:0


00 X 010 (Add)
X1 X 110 (Subtract)
1X 100000 (add) 010 (Add)
1X 100010 (sub) 110 (Subtract)
1X 100100 (and) 000 (And)
1X 100101 (or) 001 (Or)
1X 101010 (slt) 111 (SLT)

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