Subject: Microprocessor and Microcontroller
Notes: Unit III
1. Serial Communication Standards
Serial communication standards play a vital role in enabling the exchange of data between devices
in a structured and efficient manner. These standards establish the rules and protocols that govern
how data is transmitted, received, and processed over serial interfaces. By adhering to specific serial
communication standards, devices can communicate seamlessly and reliably, facilitating various
applications across industries such as industrial automation, telecommunications, networking, and
more.
Serial communication standards are essential for ensuring compatibility and interoperability
between different devices from various manufacturers. They provide a common language that
devices can use to communicate with each other, regardless of their specific hardware or software
configurations. This standardized communication protocol simplifies integration, troubleshooting,
and maintenance of complex systems, ultimately improving overall system reliability and
performance.
RS232, RS485, and RS422 are among the most commonly used serial communication standards in
the industry. Each protocol has its own unique characteristics, specifications, and use cases tailored
to different communication requirements. Understanding the distinctions between these protocols
is crucial for selecting the most suitable one for specific applications based on factors like data rate,
distance, number of nodes, and noise immunity.
RS232:
• Speed: Typically, up to 115,200 bps (bits per second).
• Baud Rate: Standard baud rates range from 1,200 to 19,200 bps.
• Maximum Length of Bus: Limited to around 15 meters.
• Nodes Connected: Usually supports point-to-point communication (one transmitter, one
receiver).
RS485:
• Speed: Can support data rates up to 10 Mbps.
• Baud Rate: Flexible baud rates, commonly from 300 bps to 10 Mbps.
• Maximum Length of Bus: Extends up to 1,200 meters.
• Nodes Connected: Supports multi-point communication (multiple transmitters and receivers
on the same bus).
RS422:
• Speed: Similar to RS485, supporting data rates up to 10 Mbps.
• Baud Rate: Flexible baud rates, often from 300 bps to 10 Mbps.
• Maximum Length of Bus: Can extend up to 1,200 meters.
2. Serial Data Transfer Schemes
Like any data transfer methods, Serial Communication also requires coordination between the
sender and receiver. For example, when to start the transmission and when to end it, when one
particular bit or byte ends and another begins, when the receiver's capacity has been exceeded,
and so on. Here comes the need for synchronization between the sender and the receiver. A
protocol defines the specific methods of coordinating transmission between a sender and
receiver. For example, a serial data signal between two PCs must have individual bits and bytes
that the receiving PC can distinguish. If it doesn't, then the receiving PC can't tell where one
byte ends and the next one begin or where one bit ends and begins. So the signal must be
synchronized in such a way that the receiver can distinguish the bits and bytes as the transmitter
intends them to be distinguished.
There are two ways to synchronize the two ends of the communication.
1. Synchronous data transmission
2. Asynchronous data transmission
Synchronous Data Transmission
The synchronous signaling methods use two different signals. A pulse on one signal line
indicates when another bit of information is ready on the other signal line.
In synchronous transmission, the stream of data to be transferred is encoded and sent on one
line, and a periodic pulse of voltage which is often called the "clock" is put on another line, that
tells the receiver about the beginning and the ending of each bit.
Advantages: The only advantage of synchronous data transfer is the Lower overhead and thus,
greater throughput, compared to asynchronous one.
Disadvantages:
• Slightly more complex
• Hardware is more expensive
Asynchronous data transmission
The asynchronous signaling methods use only one signal. The receiver uses transitions on that
signal to figure out the transmitter bit rate (known as auto baud) and timing. A pulse from the
local clock indicates when another bit is ready. That means synchronous transmissions use an
external clock, while asynchronous transmissions are use special signals along the transmission
medium. Asynchronous communication is the commonly prevailing communication method in
the personal computer industry, due to the reason that it is easier to implement and has the
unique advantage that bytes can be sent whenever they are ready, a no need to wait for blocks
of data to accumulate.
Advantages:
• Simple and doesn't require much synchronization on both communication sides.
• The timing is not as critical as for synchronous transmission; therefore, hardware can be
made cheaper.
• Set-up is very fast, so well suited for applications where messages are generated at irregular
intervals, for example data entry from the keyboard.
Disadvantages: One of the main disadvantages of asynchronous technique is the large relative
overhead, where a high proportion of the transmitted bits are uniquely for control purposes and
thus carry no useful information.
3. 8251 USART Architecture and interfacing
A USART is also called a programmable communications interface (PCI). When information
is to be sent by 8086 over long distances, it is economical to send it on a single line. The 8086
has to convert parallel data to serial data and then output it. Thus, lot of microprocessor time is
required for such a conversion.
Similarly, if 8086 receives serial data over long distances, the 8086 has to internally convert
this into parallel data before processing it. Again, lot of time is required for such a conversion.
The 8086 can delegate the job of conversion from serial to parallel and vice versa to the 8251A
USART used in the system.
The Intel8251A is the industry standard Universal Synchronous/Asynchronous Receiver /
Transmitter (USART), designed for data communications with Intel microprocessor families
such as 8080, 85, 86 and 88. The 8251A converts the parallel data received from the processor
on the D7-0 data pins into serial data, and transmits it on TxD (transmit data) output pin of
8251A. Similarly, it converts the serial data received on RxD (receive data) input into parallel
data, and the processor reads it using the data pins D7-0.
FEATURES
• Compatible with extended range of Intel microprocessors.
• It provides both synchronous and asynchronous data transmission.
• Synchronous 5-8 bit characters.
• Asynchronous 5-8 bit characters.
• It has full duplex, double buffered transmitter and receiver.
• Detects the errors-parity, overrun and framing errors.
• All inputs and outputs are TTL compatible.
• Available in 28-pin DIP package.
ARCHITECTURE
The 8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data
communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from
the CPU and transmits serial data after conversion. This device also receives serial data from the outside
and transmits parallel data to the CPU after conversion. The internal block diagram of 8251A is shown
in fig below.
Data Bus Buffer: This bidirectional, 8-bit buffer used to interface the 8251A to the system data
bus and also used to read or write status, command word or data from or to the 8251A.
Read/Write control logic: The Read/Write Control logic interfaces the 8251A with
microprocessor, determines the functions of the 8251A according to the control word written
into its control register and monitors the data flow. This section has three registers and they are
control register, status register and data buffer.
Transmitter section: The transmitter section accepts parallel data from microprocessor and
converts them into serial data. The transmitter section is double buffered, i.e., it has a buffer
register to hold an 8-bit parallel data and another register called output register to convert the
parallel data into serial bits. When output register is empty, the data is transferred from buffer
to output register. Now the processor can again load another data in buffer register.
Receiver Section: The receiver section accepts serial data and convert them into parallel data.
The receiver section is double buffered, i.e., it has an input register to receive serial data and
convert to parallel, and a buffer register to hold the parallel data. When the RxD line goes low,
the control logic assumes it as a START bit, waits for half a bit time and samples the line again.
If the line is still low, then the input register accepts the following bits, forms a character and
loads it into the buffer register. The microprocessor reads the parallel data from the buffer
register.
MODEM Control: The MODEM control unit allows to interface a MODEM to 8251A and to
establish data communication through MODEM over telephone lines. This unit takes care of
handshake signals for MODEM interface.
PIN DIAGRAM
8251A USART INTERFACING WITH 8086
4. RS-232
The term RS232 stands for "Recommended Standard 232" and it is a type of serial
communication used for transmission of data normally in medium distances. It was introduced
back in the 1960s and has found its way into many applications like computer printers, factory
automation devices etc.
RS232C “Recommended Standard 232C” is the recent version of Standard 25 pin whereas,
RS232D which is of 22 pins. In new PC’s male D-type which is of 9 pins.
RS232 is a standard protocol used for serial communication, it is used for connecting computer
and its peripheral devices to allow serial data exchange between them. As it obtains the voltage
for the path used for the data exchange between the devices. It is used in serial communication
up to 50 feet with the rate of 1.492kbps. As EIA defines, the RS232 is used for connecting Data
Transmission Equipment (DTE) and Data Communication Equipment (DCE).
Universal Asynchronous Data Receiver &Transmitter (UART) used in connection with RS232
for transferring data between printer and computer. The microcontrollers are not able to handle
such kind of voltage levels, connectors are connected between RS232 signals. These connectors
are known as the DB-9 Connector as a serial port and they are of two type’s Male connector
(DTE) & Female connector (DCE).
Electrical Specifications of RS232C for Data Transfer
Voltages
There can be two states in the signal level of RS232C pins.
• Mark state – It is the high bit which is represented by binary 1 and have negative
voltages. Its voltage limits for transmitting signal ranges from -5 to -15V. Its voltage
limits for receiving signals ranges from -3 to -25V.
• Space state – It is the low bit which is represented by binary 0 and have positive
voltages. Its voltage limits for transmitting signal ranges from +5 to +15V. Its voltage
limits for receiving signals ranges from +3 to +25V.
Cables and Wires
The maximum cable length for RS232C is equals to 15.24 meters or equal to the capacitance
of 2500pF. Limits for the impedance of wires ranges from 3 ohms to 7 ohms.
Data and Slew Rates
Rate of data transmission through RS232C is up to 20Kbps. The rate of change in signal
levels i.e. slew rate is up to 30V/microsecond.
Current
Maximum current rating is 3 Amps at the maximum operating voltage of 250V AC.
Pins and Working of RS232C
RS232C requires 25 pins connector for connecting DTE and DCE. Here is the list of pins and
signals of RS232C and the connection between DTE and DCE using drivers and receivers.
• TXD & RXD
Transmit Data and Receive Data on the DTE are the serial data lines. These lines have
opposite functions on a DCE. TXT sends outgoing data to DCE. RXD receives incoming
data from DTE.
• RTS & CTS
Transmitter activates the Request to Send when it requires to transmit data over the line.
The line itself gets deactivated when the communication stops. Receiver activates the
Clear To Send to tell the transmitter whether it is ready or not to receive the data. It
remains active during the transmission.
• DTR & DSR
Through the Data Terminal Ready line, DTE informs the DCE that it is in online mode
and the process of communication can occur. The main task of Data Set Ready signal is
to inform that DCE is ready for communication.
• DCD
DCE activates the Data Carrier Detect in order to show that it has been connected to
DTE.
• RI
When an incoming call on the telephone line is detected by DCE, then the Ring Indicator
gets activates.
Handshaking
Before the actual data transfer, signals are transmitted from DTE to DCE in order to make
connections by a process known as handshaking. Following is the sequence of signal
handshaking:
• Initially, the computer activates RTS signal to modem when a data is transferred from
computer to modem.
• Modem in turn activates the DCD and then the CTS gets activated.
• Computer then sends data on TXD. After the data transmission is completed, the
computer deactivates the RTS which causes the modem to deactivate CTS.
Applications
• It is used in establishing communication between the computer and embedded systems.
• Due to its lower costs, It plays a vital role in CNC machines and servo controllers
• Some microcontroller boards and PLC machines use RS232C.
• RS232C ports are used to communicate in headless systems in the absence of any
network connection.
• Many Computerized Numerical Control Systems are containing RS232C port.
Limitations
• It cannot be used for chip to chip or chip to sensor device communication
• It degrades the performance of the system in the presence of noise and requires shorter
cables due to having common grounds between DTE and DCE
• The cost of system increases as RS232C interface needs separate transceiver chips.
• Its performance degrades to short distances only when transfer speed is high.
5. IEEE 488 Standards
IEEE-488 General purpose interface bus and appropriate protocol are widely used in hardware-
software systems for the connection of PC and work station with measurement instruments (e.g.
in data acquisition systems). The protocol was developed in 60s in Hewlett-Packard and its
initial name was HPIB (Hewlett-Packard Interface Bus). Afterwards other companies took up
the initiative and started to use the protocol for their own purposes. In the middle of 70s, the
protocol was standardized by American Institute of Electrical and Electronics Engineers (IEEE)
and then given another name – IEEE-488 (by number of the standard) or GPIB (General
Purpose Interface Bus).
Since IEEE-488 bus is well standardized and tested; the majority of manufacturers of automated
measuring systems and instruments build GPIB interfaces into their devices as the main data
transfer channel.
Devices connected to IEEE-488 interfaces can have two conditions "listener" (read messages
from the bus) or “talker” (send messages to the bus) or be in a condition of “controller”. In
every certain moment only one device can stay in “talker” condition while the number of those
in “listener” condition can reach any quantity. Controller can determine which devices stay in
“talker” and “listener” conditions at the moment.
The bus consists of 24 wires (16 signal lines for data transfer: 8 straight and 8 return; 3
matching; 5 for the bus control) and configured in such a way that it can serve up to 15 clients
with addresses from 0 till 30 inclusive (the devices addresses should be different).
Fig. IEEE 488 BUS Connector
6. Interrupt Structure of 8086
An interrupt is a special condition that arises during the working of a microprocessor. The
microprocessor services it by executing a subroutine called Interrupt Service Routine (ISR).
The different types of interrupts present in the 8086 microprocessor are given by:
1. Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any
peripheral device by sending a signal through a specified pin to the microprocessor. There
are two hardware interrupts in the 8086 microprocessor. They are:
• NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt
that cannot be disabled. It is the highest priority interrupt in the 8086 microprocessor.
After its execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word
location 00008 H, and CS is loaded from the word location 0000A H.
• INTR (Interrupt Request): It provides a single interrupt request and is activated by the
I/O port. This interrupt can be masked or delayed. It is a level-triggered interrupt. It can
receive any interrupt type, so the value of IP and CS will change on the interrupt type
received.
2. Software Interrupts – These are instructions inserted within the program to generate
interrupts. There are 256 software interrupts in the 8086 microprocessor. The instructions
are of the format INT type, where the type ranges from 00 to FF. The starting address
ranges from 00000 H to 003FF H. These are 2-byte instructions. IP is loaded from type *
04 H, and CS is loaded from the following address given by (type * 04) + 02 H. Some
important software interrupts are:
• TYPE 0 corresponds to division by zero(0).
• TYPE 1 is used for single-step execution for debugging the program.
• TYPE 2 represents NMI and is used in power failure conditions.
• TYPE 3 represents a break-point interrupt.
• TYPE 4 is the overflow interrupt.
7. Interrupt Vector Table
• The interrupt vector (or interrupt pointer) table is the link between an interrupt type code and
the procedure that has been designated to service interrupts associated with that code. 8086
supports total 256 types i.e. 00H to FFH.
• For each type it has to reserve four bytes i.e. double word. This double word pointer contains
the address of the procedure that is to service interrupts of that type.
• The higher addressed word of the pointer contains the base address of the segment containing
the procedure. This base address of the segment is normally referred as NEW CS.
• The lower addressed word contains the procedure’s offset from the beginning of the segment.
This offset is normally referred as NEW IP.
• Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will
start.
• As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore interrupt
pointer table occupies up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low memory.
• The total interrupt vector table is divided into three groups namely,
▪ Dedicated interrupts (INT 0…..INT 4)
▪ Reserved interrupts (INT 5…..INT 31)
▪ Available interrupts (INT 32…..INT 225)
8. Need for 8259 Programmable Interrupt Controller
The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085
and 8086 there are five hardware interrupts and two hardware interrupts respectively. Bu adding
8259, we can increase the interrupt handling capability. This chip combines the multi-interrupt
input source to single interrupt output. This provides 8-interrupts from IR0 to IR7. Let us see
some features of this microprocessor.
• This chip is designed for 8085 and 8086.
• It can be programmed either in edge triggered, or in level triggered mode
• We can mask individual bits of Interrupt Request Register.
• By cascading 8259 chips, we can increase interrupts up to 64 interrupt lines
• Clock cycle is not needed.
The pin level diagram and functional pin diagram is given below
The block diagram is like below
Why is the 8259 PIC Needed?
1. Limited Interrupt Handling in 8086
• The 8086 processor has only one interrupt request line (INTR).
• Without an interrupt controller, handling multiple interrupt sources would require
continuous polling, which is inefficient.
2. Interrupt Prioritization
• The 8259A allows up to 8 hardware interrupts and prioritizes them.
• The highest priority interrupt is serviced first, ensuring critical tasks get immediate
attention.
3. Interrupt Expansion
• Multiple 8259A PICs can be cascaded, allowing up to 64 interrupt sources.
• This is useful in complex systems like computers, industrial automation, and embedded
systems.
4. Interrupt Masking
• The Interrupt Mask Register (IMR) in the 8259A allows selective enabling or disabling of
specific interrupts.
• This helps in managing different priority levels dynamically.
5. Efficient Interrupt Processing
• The 8259A automatically identifies the highest priority interrupt and sends an Interrupt
Vector Number (IVN) to the CPU.
• The processor does not need to poll each device to determine the interrupt source, saving
execution time.
6. Supports Different Interrupt Modes
• Fully nested mode (default mode, highest priority serviced first).
• Rotating priority mode (priority changes dynamically).
• Special mask mode (ignores masked interrupts).
• Polled mode (processor queries the PIC for interrupt status).
7. Reduces CPU Overhead
• The CPU does not need to continuously check each device for interrupts.
• This improves system efficiency and allows the processor to focus on execution rather than
interrupt management.
Applications of 8259 PIC
• Personal Computers (PCs) (used in IBM PC XT and AT systems).
• Embedded Systems for real-time interrupt handling.
• Industrial Automation for controlling multiple sensors and actuators.
• Military and Aerospace applications requiring real-time processing.
