CHAPTER 5
Serial I/O
SERIAL DATA TRANSMISSION,
Data is transmitted bit by bit
Either from the microprocessor to I/O devices or
Vice-versa.
There are certain input/output devices which only
accept the serial data.
Examples:
CRT terminals, printers, cassette recorders etc.
2
SERIAL DATA TRANSMISSION,
Parallel to Serial conversion
Required for data transfer from the microprocessor to
the peripheral device
Serial to Parallel conversion
Required for data transfer from the peripheral device to
the microprocessor
3
BLOCK DIAGRAM
Serial I/O interfacing
4
SERIAL I/O: INTERFACING REQUIREMENTS:
Identify the device through a port number.
Memory-mapped.
Peripheral-mapped.
Enable the device using the Read and Write control
signals.
Read for an input device.
Write for an output device.
Only one data line is used to transfer the information
5
BASIC CONCEPTS
Controlling the transfer of data:
Microprocessor control.
• Unconditional, polling, status check, etc.
Device control.
• Interrupt.
6
TRANSMISSION FORMAT
Synchronous Data Transmission
The transmitter and receiver are synchronized.
A sequence of synchronization signals is sent before the
communication begins.
Usually used for high speed transmission
More than 20 K bits/sec.
Message based.
Synchronization occurs at the beginning of a long
message 7
TRANSMISSION FORMAT
Asynchronous Data Transmission
Transmission occurs at any time.
Character based.
Each character is sent separately.
Generally used for low speed Transmission.
Less the 20 K bits/sec.
8
TRANSMISSION FORMAT
Asynchronous Data Transmission
Follows agreed upon standards:
The line is normally at logic one (mark)
Logic 0 is known as space.
The transmission begins with a start bit (low).
Then the seven or eight bits representing the
character are transmitted.
The transmission is concluded with one or two
stop bits.
9
TRANSMISSION FORMAT
Simplex and Duplex Transmission
Simplex.
One-way transmission.
Only one wire is needed to connect the two devices
Like communication from computer to a printer.
Half-Duplex.
Two-way transmission but one way at a time.
One wire is sufficient.
Full-Duplex.
Data flows both ways at the same time.
Two wires are needed.
Like transmission between two computers. 10
TRANSMISSION FORMAT
Rate of Transmission
For parallel transmission, all of the bits are sent at
once.
For serial transmission, the bits are sent one at a
time.
Therefore, there needs to be agreement on how
“long” each bit stays on the line.
The rate of transmission is usually measured in
bits/second or baud. 11
TRANSMISSION FORMAT
Rate of Transmission
Length of Each Bit
Given a certain baud rate, how long should each bit
last?
Baud = bits / second.
Seconds / bits = 1 /baud.
At 1200 baud, a bit lasts 1/1200 = 0.83 m Sec.
12
TRANSMISSION FORMAT
Transmitting a Character
To send the character A over a serial
communication line at a baud rate of 56.6 K:
ASCII for A is 41H = 01000001.
Must add a start bit and two stop bits:
11 01000001 0
Each bit should last 1/56.6K = 17.66 µ Sec.
Known as bit time.
Set up a delay loop for 17.66 µ Sec and set the
transmission line to the different bits for the duration of
the loop. 13
TRANSMISSION FORMAT
Error Checking
Various types of errors may occur during transmission.
To allow checking for these errors, additional information is
transmitted with the data.
Error checking techniques:
Parity Checking.
Checksum.
These techniques are for error checking not correction.
They only indicate that an error has occurred.
They do not indicate where or what the correct information is.
14
BASIC CONCEPTS
Parity Checking
Make the number of 1’s in the data Odd or Even.
Given that ASCII is a 7-bit code, bit D7 is used to carry
the parity information.
Even Parity
The transmitter counts the number of ones in the data. If there is an
odd number of 1’s, bit D7 is set to 1 to make the total number of 1’s
even.
The receiver calculates the parity of the received message, it
should match bit D7.
If it doesn’t match, there was an error in the transmission. 15
TRANSMISSION FORMAT
Checksum
Used when larger blocks of data are being transmitted.
The transmitter adds all of the bytes in the message
without carries.
It then calculates the 2’s complement of the result and
send that as the last byte.
The receiver adds all of the bytes in the message including
the last byte.
The result should be 0, if no error has occurred.
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SERIAL I/O STANDARD
RS 232
A communication standard for connecting computers to
printers, modems, etc.
The most common communication standard.
Defined in the 1950’s.
It uses voltages between +15 and –15 V.
Restricted to speeds less than 20 K baud.
Restricted to distances of less than 50 feet (15 m).
The original standard uses 25 wires to connect the two
devices. 17
However, in reality only three of these wires are needed.
SOFTWARE-CONTROLLED SERIAL TRANSMISSION
The main steps involved in serially transmitting a
character are:
Transmission line is at logic 1 by default.
Transmit a start bit for one complete bit length.
Transmit the character as a stream of bits with
appropriate delay.
Calculate parity and transmit it if needed.
Transmit the appropriate number of stop bits.
Transmission line returns to logic 1.
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SERIAL TRANSMISSION
19
FLOWCHART OF SERIAL TRANSMISSION
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SOFTWARE-CONTROLLED SERIAL RECEPTION
The main steps involved in serial reception are:
Wait for a low to appear on the transmission line.
Start bit
Read the value of the line over the next 8 bit lengths
The 8 bits of the character.
Calculate parity and compare it to bit 8 of the character
if parity checking is being used.
Verify the reception of the appropriate number of stop
bits.
21
SERIAL RECEPTION
22
FLOWCHART OF SERIAL RECEPTION
23
THE 8085 SERIAL I/O LINES
The 8085 Microprocessor has two serial I/O pins
for software-controlled serial I/O:
SOD – Serial Output Data
SID – Serial Input Data
Serial input and output is controlled using
the RIM(Read Interrupt Mask) and SIM (Set
Interrupt Mask) instructions respectively.
24
SIM AND SERIAL OUTPUT
SIM instruction has dual use:
It is used for controlling the maskable interrupt
process
For the serial output process.
The figure below shows how SIM uses the accumulator
for Serial Output.
MVI A,80H ; D7[A] 1
RAR ; D6D7 and D7carry
SIM ; OutputD7
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RIM AND SERIAL INPUT
RIM instruction has dual use
Reading the current settings of the Interrupt Masks
Serial Data Input
The figure below shows how the RIM instruction uses
the Accumulator for Serial Input
Serial Input data
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PORTS?
Using the SOD and SID pins, the user would not need
to bother with setting up input and output ports.
The two pins themselves can be considered as the
ports.
The instructions SIM and RIM are similar to the OUT
and IN instructions except that they only deal with
the 1-bit SOD and SID ports.
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HARDWARE CONTROLLED SERIAL I/O
Functions and requirement for hardware control
serial I/O
Ports for interfacing : Input and output ports
Parallel to Serial conversion : Transmission
Serial to Parallel conversion : Reception
Data transfer synchronization between MP and peripheral
28
INTEL 8251 USART
USART- Universal Synchronous / Asynchronous Receiver/
Transmitter
An IC which Incorporate all above stated requirements
A programmable serial communication interface chip
Designed for synchronous and asynchronous serial data
communication.
It is packed in a 28 pin DIP.
29
PIN DETAILS
D0-D7 Data bus (8 bits)
/RxC Receiver Clock
C/D Control or data to be written or
read
/RxD Receiver Data
RxRDY Receiver Ready
/RD Read Data Command
TxRDY Transmitter Ready
/DSR Data Set Ready
/WR Write Data or Control Command
/DTR Data Terminal Ready 30
PIN DETAILS
SYNDET/BD Sync/Break Detect
CLK Clock Pulse (TTL)
/RTS Request to Send Data
/CS Chip Enable
/CTS Clear to Send Data
RESET RESET Input
TxE Transmitter Empty
/TxC Transmitter Clock V
TxD Transmitter Data
CC + 5 V
31
GND Ground
ARCHITECTURE
32
ARCHITECTURE - DETAILS
The functional block diagram of 8251 consists five
sections.
Read/Write control logic
Transmitter
Receiver
Data bus buffer
Modem control.
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READ/WRITE CONTROL LOGIC
Interfaces the 8251 with MPU
determines the functions of the 8251 according to the
control word written into its control register.
It monitors the data flow.
Has three registers
control register, status register and data buffer.
The active low signals RD, WR, CS and C/D(Low)
are used for read/write operations with these
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three registers.
READ/WRITE CONTROL LOGIC
When C/D(low) is high, the control register is selected
for writing control word or reading status word.
When C/D(low) is low, the data buffer is selected for
read/write operation.
When the reset is high, it forces 8251 into the idle
mode.
The clock input is necessary for 8251 for communication
with CPU and this clock does not control either the
serial transmission or the reception rate.
35
TRANSMITTER
The transmitter section accepts parallel data from CPU
and converts them into serial data.
The transmitter section is double buffered
buffer register to hold an 8-bit parallel data and
output register to convert the parallel data into serial bits.
When output register is empty, the data is transferred
from buffer to output register.
Now the processor can again load another data in buffer
register. 36
TRANSMITTER
If buffer register is empty, then TxRDY is goes to high.
If output register is empty then TxEMPTY goes to
high.
The clock signal, TxC (low) controls the rate at which
the bits are transmitted by the USART.
37
RECEIVER
The receiver section accepts serial data and convert
them into parallel data
The receiver section is double buffered
input register to receive serial data and convert to parallel
buffer register to hold the parallel data.
When the RxD line goes low, the control logic assumes it
as a START bit, waits for half a bit time and samples
the line again.
If the line is still low, then the input register accepts the
following bits, forms a character and loads it into the
38
buffer register.
RECEIVER
The CPU reads the parallel data from the buffer register.
When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
The clock signal RxC (low) controls the rate at which bits are
received by the USART.
During asynchronous mode, the signal SYNDET/BRKDET
will indicate the break in the data transmission.
During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
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MODEM CONTROL
The MODEM control unit allows to interface a MODEM to 8251A
and to establish data communication through MODEM over
telephone lines.
This unit takes care of handshake signals for MODEM interface.
The 825 1A can be either memory mapped or I/O mapped in the
system.
8251A in I/O mapped in the system is shown in the figure.
Using a 3-to-8 decoder generates the chip select signals for I/O
mapped devices.
The address lines A4, A5 and A6 are decoded to generate eight chip
select signals (IOCS-0 to IOCS-7) and in this, the chip select signal
40
IOCS-2 is used to select 8251A.
MODEM CONTROL
The address line A7 and the control signal IO / M(low) are used as
enable for decoder.
The address line A0 of 8085 is connected to C/D(low) of 8251A to
provide the internal addresses.
The data lines D0 - D7 are connected to D0 - D7 of the processor to
achieve parallel data transfer.
The RESET and clock signals are supplied by the processor. Here
the processor clock is directly connected to 8251A. This clock
controls the parallel data transfer between the processor and
8251A.
The output clock signal of 8085 is divided by suitable clock dividers
like programmable timer 8254 and then used as clock for serial
41
transmission and reception.
MODEM CONTROL
The TTL logic levels of the serial data lines and the control
signals necessary for serial transmission and reception are
converted to RS232 logic levels using MAX232 and then
terminated on a standard 9-pin D-.type connector.
In 8251A the transmission and reception baud rates can be
different or same.
The device which requires serial communication with
processor can be connected to this 9-pin D-type connector
using 9-core cable
The signals TxEMPTY, TxRDY and RxRDY can be used as
interrupt signals to initiate interrupt driven data transfer
42
scheme between processor and 8251
MODEM CONTROL
The CPU reads the parallel data from the buffer register.
When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
The clock signal RxC (low) controls the rate at which bits are
received by the USART.
During asynchronous mode, the signal SYNDET/BRKDET
will indicate the break in the data transmission.
During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
43
8251 MODE REGISTER
7 6 5 4 3 2 1 0 Mode register
Number of Baud Rate
Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even 44
8251 COMMAND REGISTER
EH IR RTS ER SBRK RxE DTR TxE
TxE: transmit enable
DTR: data terminal ready
RxE: receiver enable
SBPRK: send break character
ER: error reset
RTS: request to send
IR: internal reset
EH: enter hunt mode
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8251 STATUS REGISTER
DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY
TxRDY: transmit ready
RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
46
8251 INTERFACED WITH 8085
47
EXAMPLE
Write a subroutine program to transmit serially 256 bytes of
data stored in the memory locations starting at 3000 H. The
bytes are to be transmitted in synchronous mode (without
parity) with two sync characters using 8251. Consider 90 H and
91 H are the port addresses for control/status register and data
register respectively.
48
MODE WORD
D7 D6 D5 D4 D3 D2 D1 D0
Number of stop Parity Parity Character Baud Rate
bit enable length
0 0 0 0 1 1 0 0
Number of Baud Rate
Stop bits Parity enable
00: Syn. Mode
00: invalid 0: disable
01: x1 clock
01: 1 bit 1: enable
10: x16 clock
10: 1.5 bits Character length
11: x64 clock
11: 2 bits 00: 5 bits
01: 6 bits
Parity
10: 7 bits
0: odd
11: 8 bits
1: even
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SUBROUTINE PROGRAM
LXI H, 3000 H ; Initialize H-L register pair for index pointer.
MVI C, FF H ; Register C to be used as counter.
MVI A, 00 H ; Dummy word
OUT 91 H
MVI A, 40 H ; Command word for resetting 8251
OUT 91 H ; Command word loaded to the control register.
MVI A, 0C H ; Mode word 0C H is loaded to the accumulator.
OUT 91 H ; The mode word for two sync character
; is loaded to the control register.
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SUBROUTINE PROGRAM…
STATUS IN 90 H ; Read the status word.
ANI 01 H ; Mask all the bits except D0 for
; checking the status.
JZ STATUS ; If D0 bit is zero jump to STATUS to read again.
MOV A, M ; Loads the character to be transmitted
; to the accumulator.
OUT 91 H ; Character is transmitted.
DCR C ; Decrements the data in C register for
; next byte for transmission.
JNZ STATUS ; If all bytes are not transmitted then
; jump to STATUS to read the next byte.
RET ; Returns to main program 51
