ECE 4101

Digital Electronics and Logic Design

Dr. Sheikh Md. Rabiul Islam

Professor
Dept. of ECE
Khulna University of Engineering & Technology

Topic 7 - 1
 Supplementary Reading
• Microelectronic Circuit Design
by – Richard C. Jaeger & Travis N. Blalock

Chapter-6
Introduction to Digital Electronics

Topic 7 - 2
 The Ideal Inverter
The ideal inverter has the following voltage transfer characteristic
(VTC) and is described by the following symbol

V+ and V- are the supplyrails

VH and VL describe the high and low logic levels at the output
Topic 7 - 3
 Inverter - circuit

An inverter operating with power supplies at V+ and 0 V

can be implemented using a switch with a resistive load.

Q-point

Topic 7 - 4
 Inverter - circuit

An inverter operating with power supplies at V+ and 0 V

can be implemented using a switch with a resistive load.

Topic 7 - 5
 VTC of Non-Ideal Inverter
Voltage Level Definitions

For the (VTC) of the non-ideal inverter no Vref is defined. There is now an
undefined logic state. The points (VIH ,VOL ) and (VIL ,VOH ) are defined as the points
on the VTC curve where slope is -1.

Topic 7 - 6
Logic Voltage Level Definitions
• VL – The nominal voltage corresponding to a low-logic
state at the output of a logic gate for vi = VH
• VH – The nominal voltage corresponding to a high-logic
state at the output of a logic gate for vi = VL
• VIL – The maximum input voltage that will be recognized
as a low input logic level
• VIH – The minimum input voltage that will be recognized
as a high input logic level
• VOH – The output voltage corresponding to an input
voltage of VIL
• VOL – The output voltage corresponding to an input
voltage of VIH

Typically, V-=0.
V+=5 for bipolar logic,
V+=1.8, 2.5, 3.3 for MOS logic
V+=1.0-1.5 for ultra low voltage logic

Topic 7 - 7
Noise Margins

• Noise margins represent “safety margins”

that prevent the circuit from producing
erroneous outputs in the presence of noisy
inputs
• Noise margins are defined for low and high
input levels using the following equations:

NML = VIL – VOL

NMH = VOH – VIH

Topic 7 - 8
 Logic Gate Design Goals

• An ideal logic gate is highly nonlinear and attempts to

quantize the input signal to two discrete states. In an actual
gate, the designer should attempt to minimize the
undefined input region while maximizing noise margins
• The logic gate is unidirectional. Changes at the output
should have no effect on the input.
• Voltage levels at the output of one gate should be
compatible with the input levels of a following gate
• The output of one gate should be capable of driving the
input of more than one gate: the gate should have sufficient
fan-out and fan-in capabilities
• The gate should consume minimal power (and area for
ICs) and still operate under the design specifications

Topic 7 - 9
Dynamic Response of Logic Gates

• An important characteristic of the

logical gates is the response in the
time domain
• To describe the typical pulse signal
at the input, we introduce:
The rise and fall times: tf and tr, are
measured at the 10% and 90%
points on the transitions between
the two states as shown by the
following expressions:
V10% = VL + 0.1V

V90% = VL + 0.9V = VH – 0.1V

where V is the logic swing given by

V = VH - VL
• Topic 7 - 23
Dynamic Response of Logic Gates
• For the input on the top, will the
output will be like the signal on the
bottom plot?
• No, It will be delayed.
• Propagation delay describes the
amount of time between the input
reaching the 50% point and the output
reaching the 50% point. The 50%
point is described by the following:
 PHL
 50%      
2
• The high-to-low propagation delay,
PHL, and the low-to-high propagation
delay, PLH, are usually not equal, but
can be combined as an average value:
 
 P  PHL PLH
2
Topic 7 - 11
 NMOS Logic Design
• MOS transistors (both PMOS and NMOS) can be combined with resistive
loads to create single channel logic gates.

• In most logic design situations, the power supply voltage is predetermined

by either technology reliability constraints or system-level criteria
• The circuit designer is limited to altering circuit topology and the width-to-
length (W/L) ratio since the other factors are dependent upon processing
parameters

• We begin our study of MOS logic circuit design by considering the detailed
design of the NMOS inverter with the resistor load.
• In integrated logic circuits, the load resistor occupies too much silicon area,
and is replaced by a second NMOS transistor. This “load device” can be
connected in three different configurations called the saturated load, linear
load, and depletion-mode load circuits.

Topic 7 - 12
NMOS Inverter with a Resistive Load

• The basic inverter circuit consists of an NMOS

switching device MS and a resistor load element.

• MS is the switching transistor used to “pull” the

output high - toward to the power supply VDD

• The resistor R is used to “pull” the output low, to

force vO to VL

• The size of R and the W/L ratio of MS are the

design factors that need to be chosen.

Topic 7 - 13
 NMOS Inverter with a Resistive Load
When the input voltage is at a low state, vI = VL , MS
should be cut off, with iD = 0, so that
vO = VDD = VH
Thus, in this particular logic circuit, the value of VH is
set by the power supply voltage VDD = 2.5V.
To ensure that switching transistor MS is cut off when
the input is in the low logic state, VL is designed to be
25 to 50 percent of the threshold voltage VTN of
switch MS. This choice also provides a reasonable value
The equation for the output for noise margin NML .
voltage (load line):
vO = vDS = VDD − iD R

Topic 7 - 14
 NMOS Inverter with a Resistive Load
When the input voltage is at a low state, vI = VL , MS should
be cut off, with iD = 0, so that
vO = VDD = VH
Thus, in this particular logic circuit, the value of VH is set by
the power supply voltage VDD = 2.5V.
To ensure that switching transistor MS is cut off when the input
is in the low logic state, VL is designed to be 25 to 50 percent
of the threshold voltage VTN of switch MS. This choice also
provides a reasonable value for noise margin NML .
The equation for the output voltage
(load line): vO = vDS = VDD − iD R

When the input voltage is

at a high state, vI = VH ,
switch MS is set in the
triode region by the
design of W/L parameter
and load line to ensure
that vO = VL.

Topic 7 - 15
 NMOS with Resistive Load
Design Example (1)
• Design a NMOS resistive load
inverter for
IDD – VDD = 3.3 V
 – Power(P) = 0.1 mW when VL =
0.2 V
vo
– Kn = 60 A/V2
 – VTN = 0.75 V
• Find the value of the load resistor R
and the W/L ratio of the switching
transistor MS

Topic 7 - 16
 NMOS with Resistive Load
Design Example (2)
• First the value of the current through the
resistor (for vO = VL) must be determined by
using the following:
IDD

  0.1 
    30.3
  3.3
vo


• The value of the resistor can now be found
by the following, which assumes that the
transistor is on and the output is low:

VDD  VL 3.3V  0.2V

R   102k
IDD 30.3 A

Topic 7 - 17
 NMOS with Resistive Load
Design Example (3)
• For vI = VH = 3.3 V, and vO = VL = 0.2V,
the transistor’s drain-source voltage
VDS =VL will be less than VGS -VTN=VH -VTN
IDD
• Therefore it will be operating in the triode
 region. Using the triode region equation
vo for the MOSFET, the W/L ratio can be
found:

    
   '           
   2
   0.2 
30.3  60 10 6
    3.3  0.75  0.2
2 
   1.03 1
   
   1 1

Topic 7 - 18
On-Resistance of the Switching Device
• The NMOS resistive load inverter can be thought of
as a resistive voltage divider when the output is low:

Ron
VL  V DD
Ron  R
where the On-Resistance Ron of the NMOS can be
calculated with the following expression:

vDS 1
Ron  
 W  v 
Kn'   vGS VTN  DS 
iD
 L  2 

• Note :
1.Ron should be kept small compared to R to ensure
that VL remains low.
2. Its value is nonlinear, since it has a dependence on
vDS.

Topic 7 - 19
 Noise Margin Analysis
The following equations (base on the calculation of the derivatives of
vO =VDD –iDR with respect to vI ) can be used to determine the
various parameters needed to determine the noise margin of NMOS
resistive load inverters

1
VIL  VTN 
KnR
1
VOH  VDD 
2K n R
1 V
VIH  VTN  1.63 DD
K nR K nR
2VDD
VOL 
3K n R

Topic 7 - 20
 Load Resistor Issue
• For completely integrated circuits, R must be
implemented on chip using the shown structure.

• If the resistor width W were made a line width of

1m (minimum feature size F), then the length L
would be 2880 m, and the area would be 2880 m2.

L L • For the transistor MS, W/L was found to be 2.22/1. If

R
A tW the device channel length is equal to the minimum
28.8k 1104 cm  feature size of 1 m, then the gate area of the NMOS
L Rt 2880
   is only 2.22 m2. Thus, the load resistor would
W  0.001cm 1
consume more than 1000 times the area of the
for R  28.8k switching transistor MS.

• This is simply not an acceptable utilization of area in

IC design.

• The solution to this problem is to replace the load

resistor with a transistor.
Topic 7 - 21
 Using Transistors in Place of a Resistor
We are replacing a 2-terminal device with a 3(4)-terminal device and need to figure our what
to do with the gate (since drain and source are conducting).

NMOS load with

a) gate connected to the source
b) gate connected to ground
c) gate connected to VDD
d) gate biased to linear region
e) a depletion-mode NMOSFET
f) gate grounded PMOS load

Note that a) and b) are not useful,

since with 0 at the gate, the
enhancement mode NMOS is
not conducting.

We’ll consider other methods

starting from (c)

Topic 7 - 22
 NMOS Saturated Load Inverter
It’s the (c) on diagram, called saturated because ML is in saturation region:
vDS = vGS  vDS ≥ vGS − VTN for VTN ≥ 0

The substrate is common and grounded:

 vSB=0 for MS .
Schematic for a NMOS  vSB=vO for ML ,
saturated load inverter thus VTN is generally different for both.

Topic 7 - 23
NMOS Saturated Load Inverter-Design Strategy

• Given VDD, VL, and the power level, find IDD from VDD and power.

• Assume MS off, and find high output voltage level VH

• Use the value of VH for the gate voltage of MS and calculate(W/L)S

of the switching transistor based on the design values of IDD and VL

• Use the value of VH for the gate voltage of MS and find (W/L)L of
the load transistor based on IDD and VL

• Check the operating region assumptions of MS and ML for vo =VL

Topic 7 - 24
 NMOS Saturated Load Inverter - Example
• First, set vi = VH ,vO = VL, MS - on, and find the
V DD  3.3V
value of the current through the resistor using the
power :
P 0.2mW
I DD    60 A
VDD 3.3V
IDD
 VH  2.11V • Now set vi = VL ,vO = VH, MS - off, ML - off and then,
find VH (since now, VH is not equal VDD.) Why?
• When MS turns off from the on state, the current IDD
will stop when the value of vGSL will reach VTNL, (vGS >
VTN, for IDD to exist)V
H
vGSL = VDD − vO =VTN  VH = VDD − VTN .
Design an saturated load inverter
Thus, taking into account the body effect () and
given the following specifications: surface potential parameter (F): VH
VDD  3.3V '  50 /  2  
VH  VDD VTNL  VDD  VTO  VSB  2F  2 F 
VL  0.2V   0.75   
VH  3.3  0.75 0.5 VH  0.6  0.6 
 
P  0.2mW   0.5  VH  2.11V , 4.01V ,since VH VDD

2  0.6  (The output cannot exceed the positive power supply
voltage.)
Topic 7 - 25
 NMOS Saturated Load Inverter - Example
VH VL
I DL I DS  K n'   VGS VTN
W V DSV
 L S  2  DS

60 A  50106    2.11 0.75 

W 0.2 
2 
0.2
 L S 
SAT
 W 4.76
 L 
I DS  S 1

K n' W 
I DL  L VGSL  VTNL 2
, VGSL  VDD VL
2  L
LIN
• Now we can find W/L for both
VTNL  0.75  0.5  
0.2  0.6 0.6  0.81V

60  A  50106   3.3  0.2  0.812

transistors MS and then ML. W
• Set vi = VH , vo = VL:  L L
MS is in the triode region (on)  W 1
ML is in saturation (on).  L   2.19
 L

Check the operating region. For the switch, VGS − VTN = 2.11 − 0.75 = 1.36 V, which is greater than
VDS = 0.2 V, and the triode region assumption is correct. For the load device, VGS − VTN =3.1 − 0.81=
2.29 V and is less than VDS = 3.1 V, which is consistent with the saturation region of operation.

Topic 7 - 26
NMOS Saturated Load Inverter -Noise Margin
The detailed analysis of the noise margins for saturated load inverter is
quite tedious. Instead, the PSPICE simulation can be used. Example:

From the PSPICE simulation typical noise margins are:

NMH = VOH - VIH = 1.55 - 1.42 = 0.33 V
NML = VIL - VOL = 0.90 - 0.38 = 0.22 V

Topic 7 - 27
NMOS Inverter with a Linear Load
• This inverter has a load transistor that is biased
with VGG defined by the following:

VGG  VDD VTNL

• This causes the load transistor to operate in the
linear region:
vGSL − VTNL = VGG − vo − VTNL

Topic 7 - 28
NMOS Inverter with a Linear Load
• This inverter has a load transistor that is biased
with VGG defined by the following:

VGG  VDD VTNL

• This causes the load transistor to operate in the
linear region:
vGSL − VTNL = VGG − vo − VTNL
≥ VDD + VTNL − vo − VTNL
≥ VDD − vo = vDSL

• For this value of VGG, the output voltage in the

high output state VH is equal to VDD:
MS -off, iD=0  vDSL=0 (linear region) 
vDSL= VDD − vo = VDD − VH =0  VH =VDD

• The W/L ratios for MS and ML can be calculated

as in previous section ( easier, since VH is equal
to VDD)
Topic 7 - 29
 NMOS Inverter with a Depletion-mode Load
• The saturated load and linear load circuits were used when all the devices had
the same threshold voltages in early NMOS and PMOS technologies.
• However, once ion-implantation technology was perfected, it became possible to
selectively adjust the threshold of the load transistors to alter their characteristics
to become those of NMOS depletion mode devices with VTN < 0.

• When MS is off (vI = VL ), the current

iD =0, hence from the linear region
(which is now possible even for vGSL =0
D LIN
because of depletion mode) we have
iD =0 vDSL =0 (< vGSL - VTN >0) and output
voltage rises to VH = VDD

Topic 7 - 30
 NMOS Inverter with a Depletion-mode Load
• The saturated load and linear load circuits were used when all the devices had
the same threshold voltages in early NMOS and PMOS technologies.
• However, once ion-implantation technology was perfected, it became possible to
selectively adjust the threshold of the load transistors to alter their characteristics
to become those of NMOS depletion mode devices with VTN < 0.

• When MS is off (vI = VL ), the current

iD =0, hence from the linear region
(which is now possible even for vGSL =0
D because of depletion mode) we have
SAT
vDSL =0 (< vGSL - VTN >0) and output
voltage rises to VH = VDD

• For MS on and conducting (vI = VH ),

E vO = VL, ML is designed to be saturated
LIN
(vDSL = 2.5 - vO > vGSL - VTN ) and MS , as
usual, in the triode region.

Topic 7 - 31
NMOS Inverter with a Depletion-mode Load

• Then we set input to VH a(both transistors on) and find W/L

• To find (W/L)L given iDL (which we find from power requirements)

we use the saturation mode for ML with vGS =0 :

  
'
 
      
2

2   

• To find (W/L)S where VH = VDD, use the same technique as used for
the resistor load inverter:
   
             
'

   2
iDS  iDL

Topic 7 - 32
NMOS Inverter with a Depletion-mode Load -
Noise Margins
The detailed analysis of the noise margins for saturated load inverter is
quite tedious. Instead, the PSPICE simulation can be used. Example:

From PSPICE simulation, typical noise margins are:

NMH = VOH - VIH = 2.35 - 1.45 = 0.90 V
NML = VIL - VOL = 0.93 - 0.50 = 0.43 V
Topic 7 - 33
 Pseudo NMOS Inverter
• It is possible to replace the load resistor with a PMOS transistor with its
source connected to VDD, its drain connected to the output node and its gate
grounded.
• This circuit is called pseudo NMOS since circuit operates very similar to
NMOS although has a PMOS in it.

• For vo = VL (MS is on), ML is in

the saturation region.

LIN • For vo = VH (MS is off) ML is in

the triode region (i=0,
0=VDS < |VGS - VTN |=|2.5 - VTN |.

• For this circuit, VH = VDD

because ML is in the linear
triode region and VDS =0 when
MS is off.

Topic 7 - 34
 Pseudo NMOS Inverter
• It is possible to replace the load resistor with a PMOS transistor with its
source connected to VDD, its drain connected to the output node and its gate
grounded.
• This circuit is called pseudo NMOS since circuit operates very similar to
NMOS although has a PMOS in it.

• For vo = VL (MS is on), ML is in

the saturation region.

LIN • For vo = VH (MS is off) ML is in

the triode region (i=0,
0=VDS < |VGS - VTN |=|2.5 - VTN |.

• For this circuit, VH = VDD

because ML is in the linear
triode region and VDS =0 when
MS is off.

Topic 7 - 35
 Pseudo NMOS Inverter Design - Example

• First calculate (W/L)P to limit

inverter current to 80 uA.
SAT

MS is on, ML is in saturation:

VGS  VDD
LIN K 'p  W 
ID   
2
V
2  L P GS
V
• Design an pseudo NMOS inverter TP

given the following specifications:

40 A  W 
80 A 2.5 ( 
2 2
  0.6) V
K n' 100A/ V 2V 2  L  P
    2.5 
2

K 'p  40A/ V 2  W   1.11

   0.2   L
 P 1
  80 VTO  0.6V
 0
Topic 7 - 36
Pseudo NMOS Inverter Design - Example

• Now calculate (W/L)S for the same

condition and current of 80 uA.
SAT

Kn'  W  
  VL 
 V VTN
2  L S  H 2  L
ID V (triode region)

LIN 100 A  W   0.2 

80 A     2.5  0.6   0.2V 2
2V  L S 
2 2 
 W   2.22
 L
 S 1

Topic 7 - 37
Pseudo NMOS Inverter - Noise Margins

From SPICE simulation, typical noise margins are:

NMH = VOH - VIH = 2.33 - 1.58 = 0.75 V
NML = VIL - VOL = 0.95 - 0.49 = 0.46 V

Topic 7 - 38
 NMOS Inverter Summary
• Resistive load inverter takes up too much area for and IC design.

• The saturated load configuration is the simplest design, but VH

never reaches VDD, and it has a slow switching speed.

• The linear load inverter fixes the speed and logic level issues, but
it requires an additional power supply for the load gate.

• The depletion-mode NMOS load requires the most processing

steps, but needs small area to achieve the high speed, VH = VDD,
and best combination of noise margins.

• The Pseudo NMOS inverter offers the best speed with the lowest
area.
Topic 7 - 39
 Typical Inverter Characteristics

Inverter w/ Saturated Linear Inverter w/ Pseudo-

Resistor Load Load Depletion- NMOS
Load Inverter Inverter Mode Load Inverter

VH (V) 2.50 1.55 2.50 2.50 2.50

VL (V) 0.20 0.20 0.20 0.20 0.20
NML (V) 0.25 0.25 0.12 0.43 0.46
NMH (V) 0.96 0.33 0.96 0.90 0.75
Relative 2880 6.39 7.94 4.03 3.33
Area

Topic 7 - 40
 Static Power Dissipation
• Static Power Dissipation is the average power dissipation of the logic
gate for the high and low logic states. If the duty cycle is 50% it is:

VDD IDDH VDD IDDL

Pav 
2
• IDDH = current in the circuit for vO = VH
• IDDL = current in the circuit for vO = VL

VDD IDDL
• Since IDDH = 0 for vO = VH : Pav 
2
• If the duty cycle is different, 2 in the denominator should be changed
appropriatly.

Topic 7 - 41
 Dynamic Power Dissipation

• Dynamic Power Dissipation is the power dissipated during the process

of charging and discharging the load capacitance connected to the
logic gate

Charging Discharging

Topic 7 - 42
 Dynamic Power Dissipation

• Dynamic Power Dissipation is the power dissipated during the process

of charging and discharging the load capacitance connected to the
logic gate

Charging Discharging

Topic 7 - 43
 Dynamic Power Dissipation

• Dynamic Power Dissipation is the power dissipated during the process

of charging and discharging the load capacitance connected to the
logic gate

Charging Discharging

Topic 7 - 44
 Dynamic Power Dissipation
• Based on the energy equation, the energy delivered to the capacitor can be
found by:
 VC () VC ()
dvC
ED  VDD  i(t)dt  V DD  C dt  CV DD  dvC  CVDD
2

0 VC (0)
dt VC (0)

2
• The energy stored by the capacitor is: CV DD
ED 
2
2
CV

• The energy lost in the resistive elements is given by: EL  E D  ES  DD
2

• The total energy lost in the first charging and discharging of the capacitor
through resistive elements is given by: 2 2
CVDD CVDD
ETD    CV 2DD
2 2

• Thus, if the logic circuit is switching at a frequency f, the dynamic power

dissipation is given by:
PD  CVDD2
f

• In the high speed logic circuits this component becomes dominant and
constitutes the primary source of power dissipation in CMOS logic gates.
Topic 7 - 45
 Power Scaling in MOS Logic

• With the transistor load, the current in both the load and switch
transistors is determined by the similar expressions, e.g.:

• By reducing the W/L of the load and switching transistors of an

inverter, it is possible to reduce the power dissipation by the same
factor without sacrificing VH and VL.
• This same concept works for increasing the power which will increase
the dynamic response.

Topic 7 - 46
 Power Scaling in MOS Logic

a) Original Saturated Load Inverter

b) Saturated Load inverter designed to operate at 1/3 the power
c) Original Depletion-Mode Inverter
d) Depletion-mode inverter designed to operate at twice the power

Topic 7 - 47
 Dynamic Behavior
Capacitance in MOS Logic Circuits

• The MOS device has capacitances CSB, CGS, CDB, and CGD that need to be considered
for dynamic response analysis.
• The capacitances seen at a node can be lumped together.
• DC loading constraints are not usually important for MOS logic circuits since they
normally drive capacitive loads (i.e. the gate of a MOS)
• As the number of gates the output (fan-out) of a logic device has to drive increases, the
load capacitance increases, and the time response degrades.
• This notion implies that the fan-out that a logic circuit can drive will be limited by time
delay tolerances of the circuit.

Topic 7 - 48
 Dynamic Response of the NMOS Inverter
with a Resistive Load

Closing switch: vI high  low Charging capacitor

• Rise time is defined as the time for the output to change from 10% to 90% of
the complete transition.
t t
vO (t1)  VF  V exp  1   VI  0.1V  V exp  1   0.9 V  t1 RC ln 0.9
 RC   RC 
t t
vO (t 2 )  VF  V exp 2   VI 0.9V  V exp  1   0.1 V  t2  RC ln 0.1
 RC   RC 
tr  t2  t1  RC(ln 0.1 ln.9)  RC ln(0.9 / 0.1)  RC ln 9  2.2RC

Topic 7 - 49
Dynamic Response of the NMOS Inverter
with a Resistive Load
Delay time τPLH is defined as the time required for the output to change 50:
vO(τPLH) = VI + 0.5V, which yields :
PLH  PHL  RC ln 0.5  0.69RC
where R and C are the resistance and capacitance seen at the output.
For high-to-low transitions, the on resistance of MS, RonS, varies during the
transition but an effective R, Reff, can be approximated as 1.7 RonS.
 PHL  0.69Reff C  1.2RonS C t f  2.2Reff C  3.7RonS C,
where Reff 1.7RonS

For low-to-high transitions, R is the load resistance (MS is off):

Topic 7 - 50
 Pseudo NMOS Inverter - Dynamic
Response

Closing switch: vI high  low Opening switch: vI low  high

• The expressions for the propagation delays are the same as for resistive

  0.69eff   1.2   0.69eff   1.2

 2.2eff  3.7,  2.2eff   3.7,

Topic 7 - 51
 Pseudo NMOS Inverter - Dynamic Response
Example
• Find tf, tr, PHL, PLH for a pseudo NMOS • Now calculate delays from the Reff
inverter where: approximations:
– (W/L)S = 2.22/1 and (W/L)L = 1.11/1
   1.2   1.2(2.37)(1)  2.84 
– CLOAD = 1 pF
   3.7   8.77 
– VTN = 0.6 V and VTP = -0.6 V
– VDD = 2.5 V   1.2  1.2(11.9)(1)  14.3 
– Kn = (2.06)(100 ´ 10-6 A/V2)    3.7    44.0 
– KL = (1.11)(40 ´ 10-6 A/V2)

• First find the on-resistances of the

two switch and load devices
1 1
RonS    2.37k
K S VH VTNS   A
2.22100 2 2.5 0.6
 V 
1 1
RonL    11.9k
K L | VDD  VTP |  A
1.11 40 2 | 2.5  (0.6) |
 V 
Topic 7 - 52
 Comparison of Load Devices

The simulation results

for all five inverters.
The current has been
normalized to 80 A
for vo = VOL= 0.20V

• The saturated load devices have the poorest fall time since they have the lowest
load current delivery
• The saturated load devices also reach zero current before the output reaches 2.5 V
• The linear load device is faster than the saturated load device, but about equal to
the resistive load speed.
• The fastest PLH is for the pseudo NMOS device as a result of the PMOS device

Topic 7 - 53
 PMOS Logic

• PMOS logic circuits predated NMOS logic circuit, but were replaced
since they operate at slower speeds

Resistive Load Saturated Load Linear Load Depletion-Mode Pseudo PMOS

Load

Topic 7 - 54
PMOS NAND and NOR Gates

NOR Gate NAND Gate

Topic 7 - 55