IT & Software Other IT & Software SystemVerilog
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Design Veri�cation with SystemVerilog/UVM
Unveiling UVM in SystemVerilog language: From Building UVM Agents to Functional Coverage
and Debugging Techniques
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Created by Cristian Slav
Last updated 03/2025
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What you'll learn
Module level veri�cation using SystemVerilog Build agents in SystemVerilog/UVM to drive and
and UVM library. monitor communication interfaces.
Build the model of the registers using UVM and Build the functional model of a Device Under
connect it to the APB interface in order to let Test (DUT) and use it to predict the correct
UVM perform its automatic checks on the response expected from the DUT.
register accesses.
Build a scoreboard to verify automatically all the Build the coverage model and all the logic
expected outputs of a DUT. necessary to collect that coverage.
Build random tests to verify all the features of a Learn how to deal with synchronization issues in
DUT. the model.
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SystemVerilog Other IT & Software IT & Software
This course includes:
21 hours on-demand video Access on mobile and TV
46 articles Certi�cate of completion
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(51 resources
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Course content
8 sections • 162 lectures • 21h 20m total length Expand all sections
Introduction 7 lectures • 1hr 25min
Introduction Preview 02:34
What is Design Veri�cation 08:29
Device Under Test (DUT) 27:52
Environment Architecture Preview 06:58
Environment Coding Kick O� - Lecture 08:03
Environment Coding Kick o� - Practice - Info 00:31
Environment Coding Kick O� - Practice 30:45
The Basics in Building an UVM Agent 25 lectures • 3hr 27min
Building Reusable UVM Agents 21 lectures • 4hr 6min
Advanced Technique For Building UVM Agents 20 lectures • 1hr 29min
UVM Register Model 21 lectures • 3hr 29min
Modeling and Checking 49 lectures • 5hr 3min
Debug and Tests 17 lectures • 2hr 9min
Wrapping Up 2 lectures • 11min
Requirements
You need to have a basic understanding of digital integrated circuits and how they are modeled in a HDL language
like Verilog.
There is no hard requirement for your to know SystemVerilog but prior OOP and Verilog knowledge is required.
Description
Master UVM Library & Create a Veri�cation Environment: Comprehensive Course Overview
In this course, you'll delve into two crucial areas:
Highest Rated 4.7Uncover 2,343 ₹499
1. UVM Library: Add to cart
all its features, secrets, and how they can be applied e�ectively in veri�cation environments.
(51 students ₹1,799
2. Veri�cation Environment Creation: Learn the step-by-step process of building a robust veri�cation environment
ratings)
from the ground up using UVM.
Course Objectives:
Throughout this course, we'll guide you through the development of a veri�cation environment, meticulously designed
using the UVM library. Each tutorial will introduce new functionalities, demonstrating the UVM features necessary for
each phase of our comprehensive project.
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Instructor
Cristian Slav
Veri�cation Engineer
4.7 Instructor Rating
51 Reviews
2,343 Students
1 Course
I am a senior veri�cation engineer with around 20 years experience in ASIC functional veri�cation.
I have contributed to the successful completion of projects ranging from start-ups to well established companies.
Professional Experience:
- 20 years experience as a functional veri�cation engineer using 'e' language and SystemVerilog
Show more
4.7 course rating 51 ratings
Ishfaq A. Abdallah S.
IA AS
2 weeks ago 2 weeks ago
Great course.- Content covers all fundamental Very rich and informative course. I highly
topics.- In-depth explanation of practical recommend this course to all₹499
the potential
Highest Rated 4.7 2,343
concepts which Add to cart
(51are easy to follow along.- Great
students students who want to enrich₹1,799
their information
cohesion between modules.
ratings) about the UVM. Also recommend students to
have at-least the basics of UVM before starting…
Helpful? this course.
Helpful?
Paweł M. Ahmad K.
PM AK
3 weeks ago 3 weeks ago
Very well explained topics so far (half of course The best UVM course I have ever seen so far.
done) - everything is clear and the presentation is There is so much e�ort put into these tutorials.
really nice explained (from UVM basics to more The slides are animated which is a plus and
advanced topics). everything is explained in a simple manner.
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Highest Rated 4.7 2,343 ₹499
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(51 students ₹1,799
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