x86 Processor Memory Management

Course Teacher:
Md. Obaidur Rahman, Ph.D.
Professor
Department of Computer Science and Engineering (CSE)
Dhaka University of Engineering & Technology (DUET), Gazipur.

Course ID: CSE - 4503

Course Title: Microprocessors and Assembly Language
Department of Computer Science and Engineering (CSE),
Islamic University of Technology (IUT), Gazipur.
Lecturer Reference
• Lecture Material:
– Intel x86 Architecture: Computer Organization and
Assembly Languages, Yung-Yu Chuang
– with slides by Kip Irvine

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Real-address mode
• 1 MB RAM maximum addressable (20-bit address)
• Application programs can access any area of
memory
• Single tasking
• Supported by MS-DOS operating system

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Real-address Mode: Segmented memory
Segmented memory addressing: absolute (linear) address
is a combination of a 16-bit segment value added to a 16-
bit offset

F0000
E0000 8000:FFFF
D0000
C0000
B0000
A0000
one segment
90000
80000 (64K)
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs
00000
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Real-address Mode: Calculating linear addresses

• Given a segment address, multiply it by 16 (add

a hexadecimal zero), and add it to the offset
• Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0

Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0

• A typical program has three segments: code,

data and stack. Segment registers CS, DS and SS
are used to store them separately.
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Real-address Mode: Calculating linear addresses

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Real-address Mode: Example
What linear address corresponds to the segment/offset
address 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.

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Real-address Mode: Example
• Segment Overlapping

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Protected mode
• 4 GB addressable RAM (32-bit address)
– (00000000 to FFFFFFFFh)
• Each program assigned a memory partition
which is protected from other programs
• Designed for multitasking
• Supported by Linux & MS-Windows

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Protected mode
• Started with 80286 up to Pentium, all processors use 2
modes for memory address management

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Protected mode (Types of Address Space)
• Logical/Virtual Address:
– An address used by application program consists of 16-bit selector
and 32-bit offset value.
– In a flat memory model, 16-bit selector is loaded in CS, DS, SS and
ES registers.
• Linear Addresses:
– It is calculated from virtual address by segmentation unit.
– The base of the segment refer to by the selector is added with the
offset, generating a 32-bit linear address.
– When paging is disabled, Linear Address = Physical Address
• Physical Address:
– The address value appears on the address bus of a microprocessor
during a memory read/write operation
– Physical address calculated from linear addresses through paging
unit.
– Linear address is used as an index into the page table, where the
CPU locates the corresponding physical address. 11
Protected Mode: Calculating Linear Addresses

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Protected Mode: Calculating Addresses

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Protected mode

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Protected mode
• In this mode there is a Segment Descriptor
Table
• Typical Program structure follows:
– Code, Data, and Stack areas
– CS, DS, SS segment descriptors
– Global Descriptor Table (GDT)
– Local Descriptor Table (LDT)

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Protected mode (Address Translation)

• 80386 and later microprocessors transforms

logical address into physical address in 2 steps:
– Segment translation
– Page translation

• These translations are done in a way that it is

not visible to the application programmers or
users

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 Flat segmentation model
• All segments are mapped to the entire 32-bit physical address space, at
least two, one for data and one for code.
• All tasks can share the GDT memory.
• GDTR Register is 48-bit. LDTR is 16-bit, of which 13-bits are used to define
8192 Descriptors, each having 8 bytes size (i.e., total 64-bits = 32-bit base
address + 16-bit limit + 16-bit access). So, total memory size of GDT = 8K
x 8 bytes = 64 KB.
• Global Descriptor Table (GDT)

multiplied by
CS /
1000h DS /
SS 17
Multi-segment model
• Each program/task has a local descriptor table (LDT)
– Holds descriptor for each segment used by the program
– Uses any of the Descriptor of 8K GDT as LDT. So, LDT is not an
independent memory table from GDT.
– LDTR further can have max 8K Descriptors from the memory.
RAM

Local Descriptor Table

26000
base limit access
00026000 0010
00008000 000A
00003000 0002 8000
multiplied by
1000h 3000 18
Translating Addresses
• The processor uses a one- or two-step process
to convert a variable's logical address into a
unique memory location.
• The first step combines a segment value with a
variable’s offset to create a linear address.
• The second optional step, called page
translation, converts a linear address to a
physical address.
Converting Logical to Linear Address
• All information about a
segment is stored in a 8-
byte data structure called Logical address

Selector Offset
segment descriptor.
Descriptor table
• The segment selector
points to a segment
descriptor, which contains
Segment Descriptor +
the base address of a
memory segment. The 32-
bit offset from the logical
address is added to the GDTR/LDTR

segment’s base address, Linear address

generating a 32-bit linear (contains base address of

descriptor table)

address.
Indexing into a Descriptor Table
Each segment descriptor indexes into the program's local
descriptor table (LDT). Each table entry is mapped to a
linear address:
Linear address space

(unused)

Logical addresses
Local Descriptor Table DRAM
SS ESP
0018 0000003A

DS offset (index)
0010 000001B6 18 001A0000
10 0002A000
08 0001A000
IP 00003000
00
0008 00002CD3

LDTR register
Finally …. Defining Multi-Segments

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Paging
• Virtual memory uses disk as part of the memory,
thus allowing sum of all programs can be larger
than physical memory
• Only part of a program must be kept in
memory, while the remaining parts are kept on
disk.
• The memory used by the program is divided
into small units called pages (4096-byte or
4KByte).
• As the program runs, the processor selectively
unloads inactive pages from memory and loads
other pages that are immediately required.
Paging
• OS maintains page directory and page tables
• Page Translation: CPU converts the linear
address into a physical address
• Page Fault: Occurs when a needed page is not
in memory, and the CPU interrupts the
program
• Virtual Memory Manager (VMM): OS utility
that manages the loading and unloading of
pages
• OS copies the page into memory, program
resumes execution
Page Translation
A linear address is 10
Linear Address
10 12

divided into a page Directory Table Offset

directory field, page Page Frame

table field, and page

Page Directory Page Table
frame offset. The
Physical Address
CPU uses all three to
calculate the Page-Table Entry

physical address.
Directory Entry

CR3
32
Thank You

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