NAND and NOR Implementation in Digital Circuits
Dr. M Rambabu
Course Code: 24CSEN1001
Course Name: Digital Logic Circuits
Date: February 21, 2025
1 Preference in Digital Circuits
NAND and NOR gates are commonly used instead of AND and OR gates in digital circuits.
They are easier to fabricate and form the foundation of all digital logic families.
2 Importance of NAND and NOR Gates
These gates are called universal gates because they can be used to implement any Boolean
function.
Boolean expressions in terms of AND, OR, and NOT can be converted into NAND or NOR
logic.
3 NAND Gate as a Universal Gate
3.1 Basic Logic Operations with NAND
Inverter (NOT Operation): A NAND gate with both inputs connected together behaves as
an inverter.
AND Operation: Achieved using two NAND gates—one for NAND operation and another
for inversion.
OR Operation: Implemented by using NAND gates with additional inverters at the inputs.
3.2 Implementation of Boolean Functions
A Boolean function should first be simplified using AND, OR, and NOT.
The function is then converted to NAND logic using simple circuit manipulation techniques.
The transformation involves replacing AND-OR expressions with equivalent NAND structures.
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4 Alternative Representation of NAND Gate
To facilitate easier conversion, alternative graphical symbols for NAND gates are used. Two
equivalent graphic symbols for the NAND gate are shown in Fig. 1.
These representations help in simplifying circuit design and implementation.
Figure 1: Two graphic symbols for the NAND gate
4.1 Two-Level Implementation
The implementation of Boolean functions using NAND gates requires that the functions be in sum-of-
products (SOP) form. To understand the relationship between a sum-of-products expression and its
equivalent NAND implementation, consider the logic diagrams shown in Fig. 2. All three diagrams
are equivalent and implement the function:
Figure 2: Two-level NAND gate implementation of Boolean function F = AB + CD
F = AB + CD
The function is implemented in Fig. 2(a) using AND and OR gates. In Fig. 2(b), the AND
gates are replaced by NAND gates, and the OR gate is replaced by a NAND gate with an OR-invert
graphic symbol. A bubble represents complementation, and two bubbles along the same line indicate
double complementation, which cancels out. Removing these bubbles from the gates in Fig. 2(b)
results in the circuit of Fig. 2 (a), proving that the two diagrams are equivalent.
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In Fig. 2(c), the output NAND gate is redrawn using the AND-invert graphic symbol. When
drawing NAND logic diagrams, the circuits in either Fig. 2(b) or Fig. 2(c) are acceptable. Fig.
2(b) is in mixed notation and represents a more direct relationship to the Boolean expression it
implements. The NAND implementation in Fig. 2(c) can be verified algebraically. The function it
implements can be rewritten in sum-of-products form using De Morgan’s theorem:
F = ((AB)′ (CD)′ )′ = AB + CD
5 Multilevel NAND Circuits
The standard form of expressing Boolean functions results in a two-level implementation. However,
in digital system design, gate structures with three or more levels are sometimes required. The most
common procedure in designing multilevel circuits is to express the Boolean function using AND,
OR, and complement operations. The function is then implemented using AND and OR gates. If
necessary, it can be converted into an all-NAND circuit.
Consider the Boolean function:
F = (AB ′ + A′ B)(C + D′ )
Figure 3: Implementing F = (AB’ + A’B)(C + D’)
Although this function could be expanded into a standard sum-of-products form, we choose to
implement it as a multilevel circuit for illustration. The AND-OR implementation is shown in Fig.
3 (a). This circuit consists of four levels of gating:
1. The first level has two AND gates. 2. The second level has an OR gate. 3. The third level
consists of another AND gate. 4. The fourth level has a final OR gate.
A logic diagram with alternating levels of AND and OR gates can be easily converted into an
NAND circuit using mixed notation, as shown in Fig. 3 (b). The conversion procedure is as follows:
1. Change every AND gate to an AND-invert graphic symbol. 2. Change every OR gate to an
invert-OR graphic symbol. 3. Ensure that each bubble in the diagram is compensated by another
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small circle along the same line. If a bubble is not compensated, insert an inverter (a one-input
NAND gate) or complement the input literal.
In this example, the bubble associated with input B introduces an extra complementation, which
must be compensated by changing the input literal to B ′ .
5.1 General Procedure for Multilevel NAND Conversion
The general steps to convert a multilevel AND-OR circuit into an all-NAND circuit using mixed
notation are:
1. Convert all AND gates to NAND gates using AND-invert graphic symbols. 2. Convert all OR
gates to NAND gates using invert-OR graphic symbols. 3. Check all the bubbles in the diagram. If
a bubble is not compensated by another along the same line, insert an inverter or complement the
input literal.
5.2 Example: Another Multilevel Boolean Function
Consider the Boolean function:
F = (AB ′ + A′ B)(C + D′ )
The AND-OR implementation of this function is shown in Fig. 3.23(a) with three levels of gating.
The conversion to NAND using mixed notation is shown in Fig. 3.23(b). In this case:
- The bubbles associated with inputs C and D′ require these literals to be complemented to C ′
and D. - The output NAND gate introduces an additional bubble, which complements the output
value. To restore the original function, an inverter is added at the output to complement the signal
again.
This method ensures that the multilevel Boolean function maintains its logical equivalence while
being implemented using only NAND gates.
6 NOR Implementation
The NOR operation is the dual of the NAND operation. Therefore, all procedures and rules for NOR
logic are the duals of the corresponding procedures and rules developed for NAND logic. The NOR
gate is another universal gate that can be used to implement any Boolean function.
Figure 4: Logic operations with NOR gate
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The implementation of the complement, OR, and AND operations using NOR gates is shown in
Fig. 4. The complement operation is obtained from a one-input NOR gate, which behaves exactly
like an inverter. The OR operation requires two NOR gates, and the AND operation is achieved
using a NOR gate with inverters at each input.
Figure 5: Two graphic symbols for the NOR gate
The two graphic symbols for the mixed notation are shown in Fig. 5. The OR-invert symbol
defines the NOR operation as an OR followed by a complement. The invert-AND symbol comple-
ments each input before performing an AND operation. These two symbols designate the same NOR
operation and are logically identical due to **De Morgan’s theorem**.
6.1 Two-Level Implementation with NOR Gates
A two-level implementation using NOR gates requires that the function be expressed in **product-
of-sums (POS) form**. The **simplified product-of-sums expression** is obtained by combining the
**0s in a Karnaugh map** and then complementing the result. A product-of-sums expression is
implemented using: - **First level**: OR gates that produce the sum terms. - **Second level**: An
AND gate that performs the final product.
The transformation from an OR-AND circuit to a NOR circuit is done by: 1. Converting the OR
gates to **NOR gates** using OR-invert graphic symbols. 2. Converting the AND gate to a **NOR
gate** using an invert-AND graphic symbol. 3. Complementing any single-literal terms going into
the second-level gate.
The NOR implementation of a function expressed as a **product of sums** is illustrated in Fig.
6:
F = (A + B)(C + D)E
Figure 6: Two-level NOR gate implementation of Boolean function F = (A + B)(C + D)E
The OR-AND pattern can easily be detected by **removing the bubbles along the same line**.
**Variable E is complemented** to compensate for the extra bubble at the input of the second-level
gate.
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6.2 Multilevel NOR Implementation
The procedure for converting a multilevel AND-OR diagram into an **all-NOR logic diagram** is
similar to the one for NAND gates. In NOR logic: - **Each OR gate** is converted to an **OR-
invert** symbol. - **Each AND gate** is converted to an **invert-AND** symbol. - Any unpaired
**bubbles** must be handled by adding **inverters** or complementing the input literals.
Figure 7: Implementing F = (AB’ + A’B)(C + D’) with NOR gales
The transformation of the **AND-OR diagram** of Fig. 3 (a) into a **NOR-only diagram** is
shown in Fig. 7. The Boolean function for this circuit is:
F = (AB ′ + A′ B)(C + D′ )
The equivalent **AND-OR diagram** can be recognized from the NOR diagram **by removing
all bubbles**. To compensate for bubbles in four inputs, the corresponding input literals must be
complemented.
