Introduction to Programmable Logic

Devices
Design approaches for digital circuits
Introduction
• So far we have discussed various digital ICs for performing basic digital
operations and other functions, such as adders, comparators, arithmetic logic
unit, multiplexers, demultiplexers, code converters, shift registers, counters etc.
These ICs, due to their fix function are known as fixed function ICs. These ICs
are designed by their manufacturers and produced in large quantities to satisfy
the needs of a wide variety of applications.

• We have seen the design of digital circuits using fixed function ICs. There are
two more approaches for the design of digital circuits.

• Use of Application Specific Integrated Circuits (ASICs)

• Use of Programmable Logic Devices (PLDs)

• In the fixed function IC approach, we have to use various fixed function ICs to
implement different functional blocks in the digital circuit. On the other hand, in
ASIC, a single IC is designed and manufactured to implement the entire circuit.
In the third approach programmable logic devices are used to implement logic
functions. The main advantage of PLD approach is that PLDs can be easily
configurable by the individual user for specific applications. The Table 9.1.1
shows the comparison between these three design approaches.
• PLDs can be reprogrammed in few seconds and hence gives more flexibility to
experiment with designs. Reprogramming feature of PLDs also make it possible
accept changes/modifications in the previously design circuits. These two main
advantages and others discussed in Table 9.1.1 make PLDs very popular in
digital design.

• According to architecture, complexity and flexibility in programming PLDs

are classified as

■ PROMs : Programmable Read Only Memories

■ PLAs : Programmable Logic Arrays

■ PAL : Programmable Array Logic

■ FPGAs : Field Programmable Gate Arrays

■ CPLDs : Complex Programmable Logic Devices

 PROM (Programmable Read Only
Memory)
PROM (Programmable Read Only Memory)
• The Fig. 9.2.1 shows the block diagram of PROM. It consists of n-input lines
and m-output lines. Each bit combination of the input variables is called an
address. Each bit combination that comes out of the output lines is called a
word. The number of bits per word is equal to the number of output lines, m.
The address specified in binary number denotes one of the minterms of n
variables. The number of distinct addresses possible with n-input variables is
2n. An output word can be selected by a unique address and since there are 2n
distinct addresses in PROM, there are 2n distinct words in the PROM. The word
available on the output lines at any given time depends on the address value
applied to the input lines.

• Let us consider 64 × 4 PROM. The PROM consists of 64 words of 4-bits each.

This means that there are four output lines and particular word from 64 words
presently available on the output lines is determined from the six input lines.
There are only six inputs in a 64 × 4 PROM because 26 = 64 and with six
variables, we can specify 64 addresses or minterms. For each address input,
there is a unique selected word. Thus, if the input address is 000000, word
number 0 is selected and applied to the output lines. If the input address is
111111, word number 63 is selected and applied to the output lines.

• The Fig. 9.2.2 shows the internal logic construction of a 64 × 4 PROM. The
six input variables are decoded in 64 lines by means of 64 AND gates and 6
inverters. Each output of the decoder represents one of the minterms of a
function of six variables. The 64 outputs of the decoder are connected through
fuses to each OR gate. Only four of these fuses are shown in the diagram, but
actually each OR gate has 64 inputs and each input goes through a fuse that can
be blown as desired.

• The PROM is a two level implementation in sum of minterms form. Let us see
AND-OR and AND-OR-INVERTER implementation of PROM. Fig. 9.2.3
shows the 4 × 2 PROM with AND-OR and AND-OR-INVERTER
implementations.
1. AND Matrix
• The Fig. 9.2.4 shows the AND matrix. It is used to form product terms. It has
m AND gates with 2n-inputs and m-outputs, one for each AND gate. The Fig.
9.2.4 shows the AND gates formed by diodes and resistors structure. Each AND
gate has all the input variables in complemented and uncomplemented form.
There is a nichrome fuse link in series with each diode which can be bum out to
disconnect particular input for that AND gate. Before programming, all fuse
links are intact and the product term for each AND gate is given by

• The Fig. 9.2.5 shows the simplified and equivalent representation of input
connections for one AND gate. The array logic symbol shown in Fig. 9.2.5 (b)
uses a single horizontal line connected to the gate input and multiple vertical
lines to indicate the individual inputs. Each intersection between horizontal line
and vertical line indicates the fuse connection.
• The Fig. 9.2.6 shows the simplified representation of AND matrix with input
buffer.

2. OR Matrix
• The OR matrix is provided to produce the logical sum of the product term
outputs of the AND matrix. The Fig. 9.2.7 shows the OR gates formed by
diodes and resistors structure. Each OR gate has all the product terms as input
variables. There is a nichrome fuse link in series with each diode which can be
bum out to disconnect particular product term for that OR gate. Before
programming, all fuse link in OR matrix are also intact and the sum term for
each OR gate is given by,

• The Fig. 9.2.8 shows the simplified and equivalent representation of input
connections for one OR gate.
• The Fig. 9.2.9 shows the simplified representation of OR matrix.

3. Invert / Non-invert Matrix

• Invert/Non-invert matrix provides output in the complement or
uncomplemented form. The user can program the output in either complement
or uncomplement form as per design requirements. The typical circuits for
invert/non-invert matrix

is as shown in Fig. 9.2.10. In both the cases if fuse is intact the output is in its
uncomplemented form; otherwise output is in the complemented form.
4. Combinational Logic Implementation using PROM
• Looking at the logic diagram of the PROM, we can realize that each output
provides the sum of all the minterms of n-input variables. We know that any
Boolean function can be expressed in sum of minterms form. By breaking the
links of those minterms not included in the function, each PROM output can be
made to represent the Boolean function of one of the output variables in the
combinational circuit. For an n-input, m-output combinational circuit, we need a
2n × m PROM.

Examples for Understanding

Ex. 9.2.1 Using PROM realize the following expressions.

F1 (a, b, c) = ∑ m (0, 1, 3, 5, 7)

F2 (a, b, c) = ∑ m (1, 2, 5, 6)

Sol. : The given functions have three inputs. They generate 2 3 = 8 minterms and
since there are two functions, there are two outputs. The functions can be
realized as shown in Fig. 9.2.11.
The Fig. 9.2.12 shows the block diagram and truth table of PROM.
Ex. 9.2.2 Design a combinational using a PROM. The circuit accepts 3-bit
binary number and generates its equivalent Excess-3 code.

Sol. : Let us derive the truth table for the given combination circuit. Table 9.2.1
shows the truth table.
• In practice when we are designing combinational circuits with PROM, it is not
necessary to show the internal gate connections of fuses inside the unit, as
shown in the Fig. 9.2.13.

This was shown for demonstration purpose only. The designer has to only
specify the PROM (inputs and outputs) and its truth table, as shown in the Fig.
9.2.14.
Examples with Solutions

Ex. 9.2.3 Design a combinational circuit using ROM. The circuit accepts 3-
bit number and generates an output binary number equal to square of input
number.

AU : May-10, Marks 16

Sol.
Ex. 9.2.4 Design ROM for the following functions

F1 = ∑ (1,2,3); F2 = ∑ (0,2)

Sol. : The given functions have 4 minterms. To generate four minterms and two
outputs we need 4 x 2 ROM. For 4x2 ROM, there are two address inputs and
two data outputs.
Examples for Practice

Ex. 9.2.5 Design a switching circuit that converts a 4 bit binary code into a 4
bit Gray code using ROM array.

Ex. 9.2.6 Design a 3-bit gray to binary code converter using suitable ROM.

PLA (Programmable Logic Array)

PLA (Programmable Logic Array)
Dec.-05, 06, 08, 12, 16, 17, May-08, 09, 10, 11, 17

• The combinational circuit do not use all the minterms every time.
Occasionally, they have don't care conditions. Don't care condition when
implemented with a PROM becomes an address input that will never occur.
The result is that not all the bit patterns available in the PROM are used, which
may be considered a waste of available equipment.
• For cases where the number of don't care conditions is excessive, it is more
economical to use a second type of LSI component called a Programmable
Logic Array (PLA). A PLA is similar to a PROM in concept; however it does not
provide full decoding of the variables and does not generates all the minterms
as in the PROM. The PLA replaces decoder by group of AND gates, each of
which can be programmed to generate a product term of the input variables.
In PLA, both AND and OR gates have fuses at the inputs, therefore in PLA both
AND and OR gates are programmable. Fig. 6.6.17 shows the block diagram of
PLA. It consists of n-inputs, output buffer with m outputs, m product terms, m
sum terms, input and output buffers. The product terms constitute a group of
m AND gates and the sum terms constitute a group of m OR gates, called OR
matrix. Fuses are inserted between all n-inputs and their complement values
to each of the AND gates. Fuses are also provided between the outputs of the
AND gates and the inputs of the OR gates. The third set of fuses in the output
inverters allows the output function to be generated either in the AND-OR
form or in the AND-OR-INVERT form. When inverter is bypassed by link we get
AND-OR implementation. To get AND-OR-INVERTER implementation inverter
link has to be disconnected.

1. Input Buffer
• Input buffers are provided in the PLA to limit loading of the sources that drive
the inputs. They also provide inverted and non-inverted form of inputs at its
output. The Fig. 9.3.2 shows two ways of representing input buffer for single
input.
2. Output Buffer
The driving capacity of PLA is increased by providing buffers at the output.
They are usually 1 IL compatible. The Fig. 9.3.3 shows the tri-state, 1 IL
compatible output buffer. The output buffer may provide totem-pole, open
collector or tri-state output.

3. Output through Flip-Flops

For the implementation of sequential circuits we need memory elements, flip-
flops and combinational circuitry for deriving the flip-flop inputs. To satisfy
both the needs some PLAs are provided with flip-flop at each output, as shown
in the Fig. 9.3.4.
4. Implementation of Combination Circuit using PLA
• Like ROM, PLA can be mask-programmable or field-programmable. With a
mask-programmable PLA, the user must submit a PLA program table to the
manufacturer. This table is used by the vendor to produce a user-made PLA
that has the required internal paths between inputs and outputs. A second
type of PLA available is called a field-programmable logic array or FPLA. The
FPLA can be programmed by the user by means of certain recommended
procedures. FPLAs can be programmed with commercially available
programmer units.

• As mentioned earlier, user has to submit PLA program table to the

manufacturers to get the user-made PLA. Let us study how to determine PLA
program table with the help of example.

Examples for Understanding

Ex. 9.3.1 A combinational circuit is defined by the functions :

F1 = ∑ m (3,5,7), F2 = ∑ m (4,5,7)

Implement the circuit with a PLA having 3 inputs, 3 product terms and two
outputs.

Solution :

Step 1 : Simplify the given Boolean functions

The Boolean functions are simplified, as shown in the Fig. 9.3.5. The simplified
functions in sum of products are obtained from the maps are :

Step 2 : Write PLA program table

Therefore, there are three distinct product terms : AC, BC and AB, and two sum
terms. The PLA program table shown in Table 9.3.1 consists of three columns
specifying product terms, inputs and outputs. The first column gives the lists of
product terms numerically. The second column specifies the required paths
between inputs and AND gates. The third column specifies the required paths
between the AND gates and the OR gates. Under each output variable, we
write a T (for true) if the output inverter is to be bypassed, and C (for
complement) if the function is to be complemented with the output inverter.
The product terms listed on the left of first column are not the part of PLA
program table they are included for reference only.

Step 3 : Implementation

Ex. 9.3.2 Draw a PLA circuit to implement the logic functions

Sol. :

Step 1 : Simplify the Boolean functions

Note : The second Boolean function is in simplified form.

Step 2 : Implementation
Ex. 9.3.3 Implement the following multiboolean function using 3 × 4 × 2 PLA
PLD.

f1 (a2, a1, a0 ) = ∑ m (0, 1, 3, 5) and

f2 (a2, a1, a0 ) = ∑ m (3, 5, 7)

Sol. :

Step 1 : Simplify the Boolean functions.

To implement functions fj. and f2 we require 3 x 5 x 2 PLA and we have to
implement them using 3x4x2 PLA. Therefore, we have to examine product
terms by grouping Os instead of 1. That is product terms for complement of a
function.

Step 2 : Implementation

Looking at function outputs we can realize that product

terms are common in both functions. Therefore, we

need only 4 product terms and functions can be implemented using a 3 × 4 × 2
PLA as shown in Table 9.3.2 and Fig. 9.3.10.

PLA
As shown in the Fig. 9.3.10 exclusive-OR gate is programmed to invert the
function to get the desired function outputs.

Ex. 9.3.4 Design a BCD to Excess-3 code converter and implement using
suitable PLA.

Sol. :

Step 1 : Derive the truth table of BCD to Excess-3 converter

Step 2 : Simplify the Boolean functions for Excess-3 code

Step 3 : Write PLA program table

Step 4 : Implementation
Examples with Solutions

Ex. 9.3.5 Design and implement 3-bit binary to gray code converter using
PLA.

Sol. :

Step 1 : Derive the truth table for 3-bit binary to gray code converter
Step 2 : Simplify the Boolean functions for gray code

Step 3 : Implementation
Ex. 9.3.6 Design a combinational circuit using PLA. The circuit accepts 3-bit
number and generates an output binary number equal to square of input
number.

Sol . :

Step 1 : Derive the truth table

Step 2 : Simplify Boolean functions of square output
Step 3 : Implementation
Ex. 9.3.7 Implement the following two Boolean functions with a PLA.

F1 (A, B, C) = ∑ (0, 1, 2, 4)

F2 (A, B, C) = ∑ (0, 5, 6, 7)

Sol . :

Step 1 : Simplify the Boolean function

Step 2 : Implementation
Ex. 9.3.8 A combinational circuit is defined by functions.

F1 (A, B, C) = ∑ (3, 5, 6, 7)

F1 (A, B, C) = ∑ (0, 2, 4, 7).

Implement the circuit with a PLA having three inputs, four product terms and
two outputs.

AU : Dec.-05, Marks 6

Sol . :

Step 1 : Simplify the Boolean functions

Here, we have 6 product terms so we check for complement functions.

If we take outputs of two functions, we need only four product

terms since product terms are common between them.

Step 2 : Implementation
Ex. 9.3.9 Design a PLA structure using AND and OR logic for the following
functions.

F1 = ∑m (0, 1, 2, 3, 4, 7, 8, 11, 12, 15)

F2 = ∑m (2, 3, 6, 7, 8, 9, 12, 13)

F3 = ∑m (1, 3, 7, 8, 11, 12, 15)

F4 = ∑ m (0, 1, 4, 8, 11, 12, 15)

Sol. :

Step 1 : Simplify Boolean functions

AU : Dec.-16, Marks 10

Step : 2 Implementation
Examples for Practice

Ex. 9.3.10 Implement the following Boolean functions with a PLA

F1 (A, B, C) = ∑ (0, 1, 2, 4)

F2 (A, B, C) = ∑ (0, 5, 6, 7)
F3 (A, B, C) = ∑ (0, 3, 5, 7).

Ex. 9.3.11 A combinational circuit is defined as the functions

F1 = AB’C’ + AB’C + ABC

F2 = A’BC + AB’C + ABC

Implement the digital circuit with a PLA having 3 inputs, 3 product terms, and 2
outputs.

Ex. 9.3.12 Draw a PLA circuit to implement the functions

F1 = A'B + AC + ABC ; F2 = (AC + AB + BC).

Ex. 9.3.13 Design and implement a 4-bit binary to Gray code converter
using a PLA.

Ex. 9.3.14 Design an AND-OR-PLA that implements the functions

f(x, y, z) = ∑m (0, 2, 4, 6)

g(x, y, z) = ∑m (1, 3, 5, 7).

PAL (Programmable Array Logic)

PAL (Programmable Array Logic)
AU : Dec.-04, 05, 15, 17, May-05, 12

• We have seen that PLA is a device with a programmable AND array and
programmable OR array. However, PAL programmable array logic is a
programmable logic device with a fixed OR array and a programmable AND
array. Because only AND gates are programmable, the PAL is easier to
program, but is not as flexible as the PLA. Fig. 9.4.1 shows the array logic of a
typical PAL. It has four inputs and four outputs. Each input has buffer and an
inverter gate. It is important to note that two gates are shown with one
composite graphic symbol with normal and complement outputs. There are
four sections. Each section has three programmable AND gates and one fixed
OR gate. The output of section 1 is connected to a buffer-inverter gate and
then fed back into the inputs of the AND gates, through fuses. This allows the
logic designer to feed an output function back as an input variable to create a
new function. Such PALs are referred to as Programmable I/O PALs.

• The commercial PAL devices has more gates than the one shown in Fig. 9.4.1.
A typical PAL integrated circuit may have eight inputs, eight outputs, and eight
sections, each consisting of an eight wide AND-OR array.
1. Implementation of combinational Logic Circuit using

PAL
• Let us see the implementation of a combinational circuit using PAL with the
help of examples.

Examples for Understanding

Ex. 9.4.1 Implement the following Boolean functions using PAL.

w (A, B, C,D) = ∑ m (0, 2, 6, 7, 8, 9, 12, 13),

x ( A,B,C,D) = ∑ m (0, 2, 6, 7, 8, 9, 12, 13, 14)

y ( A,B,C,D) = ∑ m (2, 3, 8, 9, 10, 12,13),

z ( A,B,C,D) = ∑ m (1, 3, 4, 6, 9, 12, 14)

Sol. :

Step 1 : Simplify the four functions

Note that function x has four product terms. Three of them are equal to w.
Therefore we can write

Step 2 : Implementation
In the last section we have seen the PLA program table. The program table for
PAL is similar to PLA program table. Table 9.4.1 shows PAL program table with
product terms, AND inputs and outputs.
Ex. 9.4.2 Design BCD to Excess-3 converter using PAL.

Sol. : Step 1 : Derive the truth table of BCD to Excess-3 converter

Step 2 : Simplify the Boolean functions for Excess-3 code outputs.

Step 3 : Implementation
Ex. 9.4.3 Generate the following Boolean functions with a PAL with 4 inputs
and 4 outputs.

Sol. :

Step 1 : Simplify the Boolean functions

Step 2 : Implementation
Ex. 9.4.4 Show how to program the fusible links to get a 4 bit gray code from
the binary inputs using PLA and PAL and compare the design requirements
with PROM.

Sol. : Implementation using PROM

Table 3.21.4 shows the truth table for binary to gray code converter. There are
four binary inputs, i.e. 24 = 16 minterms. These minterms can be implemented
using fixed AND array of 16 AND gates of the PROM. Since there is four bit
Gray code output, we need four OR gates. Thus we need 16x4 PROM. We
know that in PROM OR-Array is programmable and hence there are 16x4 = 64
fusible links. These 64 fusible links are programmed according to gray code
column of Table 3.21.4.

Referring example 3.21.4 we have simplified expressions for 4-bit binary to

gray code conversion are as follows :

Implementation using PLA

For PLA both AND-array and OR-Array have fusible links. From simplified
Boolean expression we have seven product terms and these can be
implemented using seven eight-input AND gates. We need four OR-gates for
four-bit gray code output. Thus we need 4 × 7 × 4 PLA in place of 16 × 4 PROM.
There are (8 + 4) × 7 = 84 fusible links compared to 64 fusible links in PROM.
Fig. 9.4.7 shows implementation of 4-bit binary to gray code converter using 4
× 7 × 4 PLA.
Implementation using PAL

For PAL, AND array is programmable and has fusible links. From simplified
Boolean expression we have seven product terms and these can be
implemented using seven eight input AND gates. We need four OR-gates for
four-bit gray code output. Thus we need 7x4 PAL in place of 16x4 PROM. There
are 7 x 8 = 56 fusible links compared to 64 fusible links in PROM. Fig. 9.4.8
shows implementation of 4-bit binary to gray code converter using PAL.
Example for Practice

Ex. 9.4.5 A combinational logic circuit is defined by the following function.

f1(a,b,c) ∑ (0,1,67), f2 (a,b,c) = ∑ (2, 3,5,7).

Implement the circuit with a PAL having three inputs, three product terms
and two

AU : May-05, 12, Marks 10

Comparison between PROM, PLA and

PAL
Comparison between PROM, PLA and PAL

CPLD (Complex Programmable Logic

Devices)
CPLD (Complex Programmable Logic Devices)
Simple PLDs (SPLDs) include PLAs, PALs and other similar types of devices.

• SPLDs have limitations of number of input product terms and outputs. For
applications which requires more number of inputs or product terms or output
we have to expand the capacity of PLDs by cascading them.

• The Complex Programmable Logic Devices (CPLDs) are introduced to solve

the above mentioned difficulty of SPLDs. A typical CPLD is merely a collection
of multiple PLDs and an interconnection structure, all on the same chip, as
shown in the Fig. 9.6.1.

• In CPLDs, in addition to the individual PLDs the on-chip interconnection

structure is also programmable. Therefore, unlike PLDs, the CPLDs can be
scaled to larger sizes by increasing the number of individual PLDs.

1. Block Diagram
• The Fig. 9.6.2 shows the block diagram of a Complex Programmable Logic
Device (CPLD).
• It consists of collection of PAL like blocks, I/O blocks and a set of
interconnection wires, called programmable interconnection structure.

• The PAL like blocks are connected to the programmable interconnect

structure and to the I/O blocks. The chip input-output pins are attached to the
I/O blocks.

• A PAL like block in the CPLD usually consists of about 16 macrocells. Like
other macrocells, the macrocell in CPLD consists of AND-OR configuration, an
EX-OR gate, a flip-flop, a multiplexer, and a tri-state buffer.

• The Fig. 9.6.3 shows the typical macrocell for CPLD. Each AND-OR
configuration usually consists of 5-20 AND gates and an OR gate with 5-20
inputs.
• The EX-OR gate provides the output of OR-gate in inverted or non-inverted
form as per the fuse link status.

• AD flip-flop stores the output of EX-OR gate.

• A multiplexer selects either the output of the D flip-flop or the output of the
EX-OR gate depending upon its select input (either 1 or 0).

• The tri-state buffer acts as a switch which enables or disables the output.

2. Architecture of XC9572 CPLD

• The XC9572 is a device from XC9500 CPLD family. It consists of 4 functional
blocks (FBs), 72 macrocells, 1600 usable gates and 72 registers. The XC9572
device is available in several different packages. Different I/O packages have
different number of I/O pins. For example, 44-pin PLCC has 34 I/O pins and
100-pin TQFP has 72 I/O pins.
• In XC9572, the functional blocks and I/O blocks are fully interconnected by
the FastCONNECT switch matrix. The IOB provides buffering for device inputs
and outputs. Each FB provides programmable logic capacity with 36 inputs and
18 outputs. The Fast CONNECT switch matrix connects all FB outputs and input
signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package
pin-count) and associated output enable signals drive directly to the IOBs. This
is illustrated in Fig. 9.6.4.
 FPGA (Field Programmable Gate
Arrays)

FPGA (Field Programmable Gate Arrays)

• Field Programmable Gate Arrays (FPGA) provide the next generation in the
programmable logic devices. The word field in the name refers to the ability of
the gate arrays to be programmed for a specific function by the user instead of
by the manufacturer of the device. The word array is used to indicate a series of
columns and rows of gates that can be programmed by the end user.

• As compared to standard gate arrays, the field programmable gate arrays are
larger devices. The basic cell structure for FPGA is some what complicated than
the basic cell structure of standard gate array. The programmable logic blocks
of FPGAs are called logic blocks or Configurable Logic Blocks(CLBs).

• The basic architecture of FPGA consists of an array of logic blocks with

programmable row and column interconnecting channels surrounded by
programmable I/O blocks as shown in Fig. 9.7.1. Many FPGA architectures are
based on a type of memory called LUT (look-up table) rather than on (sum of
product) SOP AND/OR arrays as CPLDs are. Another approach found on some
FPGAs is the use of multiplexers to generate logic functions.
LUT : It is the look-up table used in FPGAs is actually a memory device that
can be programmed to perform logic functions. The LUT essentially replaces
the AND/OR array logic in a CPLD. As an example of how an LUT can be used
to produce a logic function. Fig. 9.7.2 shows a simple diagram of an 8 bit by 1
bit (8 × 1) memory programmed to produce to SOP
function When any one of the three product terms
appears on the LUT inputs, the corresponding memory cell storing a 1 is
selected and the 1 (HIGH) appears on the output. For any product terms that are
not part of the SOP function, the LUT output is 0 (LOW).
The Logic Block : Each logic block in a generic FPGA contains several logic
elements, as shown in Fig. 9.7.3. Generally there can be well over ten thousand
logic elements in a single chip.
The Logic Element : simplified diagram of a typical FPGA logic element is
shown in Fig. 9.7.4. It contains an LUT, associated logic, and a flip-flop. In this
case, each logic element contains a 4-input LUT that can be programmed as
logic function generator. It can be used to produce SOP functions or logic
functions such as adders and comparators. When configured as an adder, the
carry in and carry out allow for adder expansion. Using the cascade logic, an
LUT can be expanded by cascading with LUT's in other logic elements. The
programmable selects let you choose either combinational functions form the
LUT output or registered functions from the flip-flop output.
Ex. 9.7.1 Explain two input LUT with implementation of the function : F (A,
B) = ∑ m (0, 3).

Sol. : Two input LUT has 22 × 1-bit memory, i.e. 4 × 1-bit memory. We can
implement the given function with 2-input LUT as shown in the Fig. 9.7.5.

The bit corresponding of the two-inputs of one bit wide memory array are
available at the output of LUT. For example, if inputs AB are 00, the bit from
first location is available at the output. Storing logic 1 at bit 0 and bit 3
positions, and storing logic 0 at bit 1 and bit 2 positions we can implement the
given function.
Ex. 9.7.2 Explain the three input LUT with implementation of a full adder.

Sol. : Fig. 9.7.6 shows an 8 × 2 LUT is programmed as a full adder. The sum
and carry out expressions for a full-adder are as follows :

Interconnection Technology

FPGAs use either SRAM or antifuse methods to provide interconnections

between logic blocks. The antifuse is normally open and is shorted to create a
connection when programmed, compared to the fuse which is normally shorted
and is opened to create no connection when programmed.

In SRAM method, a transistor is controlled by the state of an on-chip SRAM

cell. When SRAM cell contains zero, the transistor is off and connection is
open. When SRAM cell contains one, the transistor is ON and connection is
shorted.
 Comparison between CPLDs and
FPGAs
Comparison between CPLDs and FPGAs
Two Marks Questions with Answers

Q.1 Define PLD.

Ans. : Programmable Logic Devices consist of a large array of AND gates and
OR gates that can be programmed to achieve specific logic functions.

Q.2 Give the classification of PLDs.

Ans. : PLDs are classified as :

• PROM (Programmable Read Only Memory),

• Programmable Logic Array (PLA),

• Programmable Array Logic (PAL), and

• Generic Array Logic (GAL)

Q.3 What is a PLA?

Ans. : PLA stands for Programmable Logic Array, which is a LSI component.
In PLA, both AND and OR gates have fuses at the inputs, therefore in PLA both
AND and OR gates are programmable. The outputs from OR gates go through
fuses as inputs to output inverters so that final output can be programmed as
either AND-OR or AND-OR-INVERT.

Q.4 Whether PAL is same as PLA ? Explain.

(Refer sections 9.4 and 9.5)

Q.5 What is the advantage of PLA over ROM ?

(Refer section 9.5)

Q.6 How does the architecture of a PLA different from a PROM ?

(Refer section 9.5)

Q.7 Why was PAL developed ?

Ans. : PAL is a PLD that was developed to overcome certain disadvantages of

PLA, such as longer delays due to additional fusible links that result from using
two programmable arrays and more circuit complexity.

Q.8 Why the input variables to a PAL are buffered ?

Ans. : The input variables to a PAL are buffered to prevent loading by the large
number of AND gate inputs to which available or its complement can be
connected.

Q.9 Draw the block diagram of PLA.

(Refer Fig. 9.3.1)

Q.10 What is PROM ?

Ans. : PROM stands for programmable read only memory. It has fixed AND
array and programmable OR array. It can be used to implement boolean
functions in standard SOP form.

Q.11 State the difference between PROM, PLA and

PAL. (Refer Table 9.5.1)

Q.12 What happens to the information stored in a memory location after it

has been read and write operation ?

Q.13 Define modularity.

Q.14 Outline about PLA.

(Refer section 9.3)

(Long Answered Questions)

(Regulation 2013)

Dec.-16

Q.1 Compare PLA and PAL circuits.

[Refer section 9.5] [3]

May-17

Q.2 Implement the following functions using programmable logic array:

f1(x,y,z) = ∑m(1,3,5,7)

f2 (x,y,z) = ∑ m(2,4,6)

(Refer similar example 9.3.3) [6]

Dec.-17

Q.3 Write short notes on PLA and PAL.

(Refer sections 9.3 and 9.4) [7]