DESIGN DFT ENGINEER
I applied for design DFT engineer position at AIONSI-Banglore
through my training institute
Exprience level is Entry Level and it is for freshers
1st Round of Technical(Virtual):
This interview is for about 40 - 45 mins. Topics covered in this interview
was Basics of Digital, Verilog, and DFT.
-They asked abt Scan Flops - significance of scan flops - working of
scan flop.
-about Jtag - Boundary scan
-Tools which I used in my project when I am in my institute
-MBIST, LBIST
-DRC and Violations
-Some Basics of Verilog like NBAs, Delays, some snippets of code
-Hold Time, Setup time, Calculation of max Freq
-Diff between Latch and FF
,
Call From HR:
Talked about company policies, remuneration, and finally got the offer
letter.
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DESIGN VERIFICATION ENGINEER
I applied for design verification engineer position at Synopsys-pune
through my training institute
Exprience level is Entry Level and it is for freshers
Written Test (Online):
It was for about 90 mins and questions are basic digital questions like gate
level questions and couple of aptitude questions and also covered some analog
questions also like opamp,cmos all are mostly in par with gate level
1st Round of Technical(Virtual):
This interview is for about 40 - 45 mins. Topics covered in this interview
was Basics of Digital, Verilog and STA.
-They asked abt diff between Latch and FF, Setup and hold time with
example,Priority Encoder and its RTL and difference between if-else and case in
priority encoder RTL. Also, asked about my project
2nd Round of Technical(Physical F2F at Synopsys Office Banglore)
It was about 1hr 45 mins where they again covered topics like digital,
system verilog and UVM
-They told me to explain about universal gates(NAND and NOR) and
told to give an example.
-Diff between FF and Latch and told me to explain SR FF using nand
or nor gates
- Asked about FIFO and its application used in my project and aksed
me to explain about Syn FIFO gave some different cases and asked me
questions about it like empty full what happens if the pointers are pointing to this
specific location.
- Polymorphism Inheritance and Constrains(Soft)
-Asked me about UVM Testbench Architecture
-Complete ASIC Design Flow
3rd Round of Interview:
This round was mixed with few HR and few Tech questions. Asked about
verification and how to find verification is successful. Then, asked about syn and
asyn reset using FF and few general HR questions.Kinda of Managerial Round
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Qualcomm
Two round interview of around 30 minute each ROUND 1:
1. Briefly tell me about your CV.
2. Can you draw any transmission gate logic and draw the truth table. 3. Write
Verilog code for D latch. After writing code he has given me waveform and told
me to draw the output according to the code which I have written.
4. What is Noise Margin.
5. Draw NAND using MUX.
6. What is setup and hold time.
7. Draw the VTC curve of inverter and explain it.
Note : basically question were asked about digital ic design and project
Round 2
1. #5 y=a+b; Y = #5 a+b; What is the difference between above two line code.
2. Draw NAND using MUX.
3. What will happen if you will replace PMOS with NMOS and NMOS with PMOS.
Is there will be any voltage degradation. Explain with Waveform and why there
will be voltage degradation.
4. What will be final voltage across capacitor if switccircuitsbe closed.
There is two circuit is as
note: questions were asked on digital ic design and sta
DESIGN VERIFICATION ENGINEER
I applied for design verification engineer position at EXCEL VLSI
through my training institute
Exprience level is Entry Level and it is for freshers
1st Round of Technical(Virtual):
Written Exam :
1 Hr exam
. Basic aptitude questions.
. Questions on melay state machines
. What is delay and types of delays in system verilog
. digital design questions and few on aplifiers.
2nd Rund of technical discussion (virtual) :
What is verilog and system verilog and uvm.
What are the delays.
What is static array and what is dynamic array and what
is associative array,
What type of array will be used in scoreboard
What is TLM in uvm what is mail box
Difference between mailbox and tlm
Sequence driver handshake
Virtual sequencer uses and construction.
Difference between subscriber and scoreboard
Write a code for d flipflop
What is latch can we implement filpflop using latch
What is metastability and how to remove it
What is difference between ssynchronous reset and
asynchronous reset
Call From HR:
Talked about company policies, remuneration, and finally got the offer
letter.
