UCEN – JNTUK DESIGNER TOOLS LAB

PROCEDURE TO OPEN MENTOR GRAPHICS TANNER EDA

1. Open VM ware and power on virtual private machine.

2. Login using root & root@123 as user ID and Password.
3. Right click on the page and click on the open terminal option a notepad will be opened.
4. Type ‘csh’ and click enter.
5. After that type the file path
‘source /home/software/MentorGraphics/cshrc/tanner_new_hep1_2.cshrc’
then click enter

6. Then type ‘sedit’ click enter then S-Edit window will open.

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PROCEDURE TO CREATE A SCHEMATIC DESIGN,

GENERATING A SYMBOL AND SIMULATING THE DESIGN
(INVERTER)
The basic steps in designing inverter (Example) using Mentor Graphics includes

➢ Creating a library and adding required libraries

➢ Creating cell & Schematic
➢ Generating Symbol
➢ Creating Test bench
➢ Run Simulation to generate wave forms.

Creating a library and adding required libraries:

• To create a library select new library then a window will pop up asking for
the library name enter the name (example:’ece’) and click ok.
• Once the library is created now right click on the library, select “add
Library” a pop up window will be appeared
• Add the following libraries using the path below.

• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Standard_Libraries_160/
SPICE_SOURCES
• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Standard_Libraries_160/
SPICE_PLOT
• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Standard_Libraries_160/
SPICE_MEASURE
• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Standard_Libraries_160/
MISC
• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Generic_250nm/Generic
_250nm_Devices
• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Generic_250nm/Generic
_250nm_AnalogLib
• /home/software/MentorGraphics/Tanner_Tools_v2021.3/Process/Generic_250nm/Generic
_250nm_LogicGates

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Creating cell & schematic:

• To create a new cell click on ‘cell’ option, select new view and name the cell
as ‘INV’
• To create inverter place PMOS25X and NMOS25X from
Generic_250nm_Devices library. (Just drag& place the
symbol. Do not double click)
• Wire the components using wiring tool.
• Give input as ‘a’ , ground as ‘gnd’ and supply as ‘vdd’ using input port icon.

• Mark output as ‘z’ using output port

• Save all
• The circuit will be as shown in the figure below.

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Generating symbol:
• To generate symbol, click on ‘cell’ option, select ‘generate symbol’.
• Add input and output given in Port placements by name table.
• Left side: a , Right side: z , Top side: vdd, Bottom side : gnd click replace and
save.

• Symbol will be generated as shown below.

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Creating Test-bench:
• To create test bench create a new cell as ‘inv_tb’
• Drag the symbol generated into this new cell.
• Place input and output ports as ‘a’ and ‘z’.
• From misc library place ‘gnd’ and ‘vdd’.s
• From spice sources library select vdc of 5 volts.
• Connect ‘gnd’ to negative terminal of vdc.
• Connect ‘vdd’ to positive terminal of vdc.
• From spice plot connect V_VoltagePrint to input and output.
• Right click on V_voltageprint symbol, change the type of analysis to
TRAN and DC in both input and output sides from properties column.
• Place vpulse from the spice_sources library to input and change the time period
as 100n,Save all.
• Now select settings, a pop up window will be displayed.
• Select general and add following path in library Files.
• ../../../../../../../software/MentorGraphics/TannerTools_v2021.2/Process/Generi
c_250nm/Models/Generi c_250nm.lib TT
• Select transient analysis and give the values for stop time, print start time, max
time step, print time step.
• Similarly select dc sweep analysis and add sweep type, parameter name, start
and stop values, step size.
• Save all. The testbench design is shown in figure below.

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Run Simulation to Generate waveforms:

• After saving the test bench click on run simulation.
• Errors will be displayed if errors are present.
• Otherwise, output wave forms will be obtained.
• The wave forms obtained are displayed below.

DC Analysis:

Transient Analysis:

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DESIGN AND SIMULATION OF INVERTER

Exp No: Date:

Aim:
To design an inverter using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
An inverter (also called a NOT gate) is a basic logic gate in digital circuits that performs
logical inversion. It converts a logical "1" (high voltage) to a logical "0" (low voltage) and vice
versa. The CMOS inverter (Complementary Metal-Oxide-Semiconductor inverter) is one of
the most fundamental building blocks in digital circuits, especially in CMOS technology, due
to its high efficiency and low power consumption.
A CMOS inverter consists of two types of transistors:
• PMOS (P-type Metal-Oxide-Semiconductor) transistor.
• NMOS (N-type Metal-Oxide-Semiconductor) transistor.
These transistors are connected in a complementary arrangement:
• The PMOS transistor is placed between the output node and the positive power supply
(VDD).
• The NMOS transistor is placed between the output node and ground (GND).
Both transistors share the same input node, which is the gate terminal of the transistors, and the
output node is the point where their drains are connected.
Basic configuration:
• Input (A): Connected to the gates of both the PMOS and NMOS transistors.
• Output (Z): Taken from the connection of the drains of the PMOS and NMOS.
• VDD: Connected to the source of the PMOS transistor.
• GND: Connected to the source of the NMOS transistor.

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Schematic:

Testbench Setup:

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Procedure:
1. Create a New Cell for the Inverter Design:

• Cell → New View: Assign a name to the new cell, such as "inv".

2. Design the Inverter Circuit:

• Open the Generic 250nm Devices library and select sym.

• Using pmos25x and nmos25x transistors, design the inverter circuit according to the
standard schematic diagram:
• Connect the PMOS transistor's substrate to VDD.
• Connect the NMOS transistor's substrate to GND.
• Connect the gates of both transistors together to form the input of the inverter.
• The output of the inverter is taken from the junction of the two transistors.

3. Attach Input and Output Ports:

• From the menu, attach the input port (A) and output port (Z).
• Also, attach GND and VDD from the misc library to provide power to the inverter.

4. Generate the Symbol for the Inverter:

• Select Cell → Generate Symbol.

• Enter the "port placements by name" details and click Replace to create the inverter
symbol.

5. Create a Test Bench for Simulation:

• Click on Cell, select New View, change the view type from Symbol to Schematic, and
rename "inv" to "inv_tb" to represent the test bench for the inverter.

6. Insert the Inverter Symbol into the Test Bench:

• Drag the generated inverter symbol from the "inv" cell into the "inv_tb" test bench
schematic.

7. Connect Input and Output Ports to the Inverter Symbol:

• Connect the input port (A) and output port (Z) to the appropriate terminals of the
inverter symbol.
• Attach GND and VDD connections from the misc library.

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8. Add a DC Voltage Source (VDC):

• Add a VDC source from the Spice Sources library next to the inverter symbol.
• Connect VDC to VDD and GND to provide power.

9. Add VPULSE Source for Input Simulation:

• Add a VPULSE source from the Spice Sources library to simulate the input signal.
• Attach the positive terminal of VPULSE to the input wire (A) and the negative
terminal to GND.

10. Adjust Properties for VPULSE:

• Select VPULSE and change its properties:

• Set the rise time and fall time to 0.01ns.

11. Add Voltage Print Labels:

• From the Spice Plot library, place voltage print labels on the input wire (A) and the
output wire (Z) to monitor the signals during simulation.

12. Set Properties for Analysis Types:

• On the input voltage print label, set the property to TRAN (transient analysis).
• On the output voltage print label, set the property to DC analysis.

13. Add the Library File Path:

• Click on Settings, select General, and add the library file path:
• Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250nm/Mod
els/Generic_250nm.lib TT.

14. Set Parameters for Transient Analysis:

• Select Transient Analysis and enter the following values:

• Stop time: 1000ns
• Print start time: 0ns
• Maximum time step: 5ns
• Print time step: 5ns

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Simulation Setup:

Output Waveforms:

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15. Set Parameters for DC Sweep Analysis:

• Select DC Sweep Analysis and enter the following values:

• Sweep type: Linear Step
• Source or parameter name: V2 (input voltage)
• Start value: 5V
• Stop value: 0V
• Step: 0.01V
• Click OK to confirm the settings.

16. Run the Simulation & Verify Timing Waveforms:

• Click on Simulation to execute both transient and DC sweep analyses.

• A new simulation window will open, and if there are 0 errors, the simulation will
proceed smoothly.
• If any errors occur, double-check the schematic connections and make sure everything
is wired correctly before re-simulating.
• Once the simulation completes, verify the timing waveforms.

Result:

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DESIGN AND SIMULATION OF NAND GATE

Exp No: Date:

Aim:
To design a NAND GATE using Mentor Graphics Tanner-Tools v2021.2 and to verify it’s
timing simulation.

Software Required:
Mentor Graphics Tanner-Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A NAND gate (Not AND) is a fundamental digital logic gate that outputs a logical 0
only when all its inputs are logically 1. Otherwise, the output is 1. It is one of the basic building
blocks in digital electronics and is used in many combinational and sequential logic circuits.
The operation of the NAND gate is the inverse of an AND gate.
A NAND gate can be implemented at the transistor level using complementary metal-oxide-
semiconductor (CMOS) technology, which consists of:
• PMOS transistors: Used for pulling the output to the high voltage (logic 1).
• NMOS transistors: Used for pulling the output to the low voltage (logic 0).
In a 2-input NAND gate:
• The PMOS transistors are connected in parallel between the output and the power
supply (VDD).
• The NMOS transistors are connected in series between the output and ground (GND).
• When both inputs are 1 (high), the NMOS transistors conduct, and the output is pulled
to 0 (low).
• If any input is 0, at least one PMOS transistor conducts, pulling the output to 1 (high).

Input A Input B Output (Y)

0 0 1
0 1 1
1 0 1
1 1 0

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Schematic:

Testbench Setup:

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Procedure:
1. Create New Cell for NAND Gate Design
• Select Cell: Click on New View and name it "nand".
2. Design the NAND Gate Using PMOS and NMOS Transistors
• Open the Generic 250nm Devices library, select sym, and use pmos25x and nmos25x
transistors to design the NAND gate as shown in the schematic diagram:
o Connect two PMOS transistors in parallel, followed by two NMOS transistors
in series, which is the standard NAND gate configuration.
3. Attach Input, Output, and Power Ports
• Attach input ports (A and B) for the inputs and an output port (Z) for the output of
the NAND gate.
• Connect GND and VDD from the misc library for power and ground connections.
4. Generate the Symbol for the NAND Gate
• Navigate to Cell → Generate Symbol.
• Use the port placements by name option, then click Replace to create the symbol for
the NAND gate.
5. Create Test Bench for NAND Gate Simulation
• Go to Cell → New View and change the view type from Symbol to Schematic.
• Rename this schematic as "nand_tb" for the test bench.
6. Insert NAND Gate Symbol into the Test Bench
• Drag the generated NAND gate symbol from the "nand" cell into the "nand_tb"
schematic.
7. Connect Power (VDD) and Ground (GND)
• From the misc library, connect VDD and GND to the appropriate power pins of the
NAND gate symbol.
8. Add DC Voltage Source
• Add a VDC source from the Spice Sources library and connect it to the VDD and GND
terminals to provide the necessary supply voltage for the circuit.
9. Simulate Inputs Using VPULSE
• Add two VPULSE sources from the Spice Sources library to simulate the input signals
for A and B.
• Connect the positive terminal of each VPULSE and the negative terminal to GND.

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Simulation Setup:

Output Waveforms:

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10. Adjust VPULSE Properties

• Change the rise time and fall time of the VPULSE sources from 5ns to 0.01ns.
• Set different period values for inputs A and B to ensure the NAND gate receives all
input combinations.
11. Add Voltage Print Labels
• From the Spice Plot library, add voltage print labels at the input wires (A and B) and
the output wire (Z).
12. Set Up Transient Analysis
• Set the analysis type to TRAN (transient analysis) on the voltage print labels to
evaluate the time-domain response of the NAND gate as inputs vary.
13. Add Device Models Path
• Go to Settings → General and add the library file path for the 250nm process models:
o Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250n
m/Models/Generic_250nm.lib TT.
14. Set Transient Analysis Parameters
• Enter the following values for transient analysis:
o Stop time: 1000ns
o Print start time: 0ns
o Maximum time step: 5ns
o Print time step: 5ns
15. Run the Simulation
• Click Simulation to run the transient analysis.
• If any errors occur, check your schematic connections and the wiring of PMOS, NMOS,
and input/output ports, then rerun the simulation.
16. Verify the Output
• After the simulation completes, verify the timing waveforms against the NAND gate
truth table.

Result:

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DESIGN AND SIMULATION OF NOR GATE

Exp No: Date:

Aim:
To design a NOR GATE using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s
timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A NOR gate (Not OR) is another fundamental digital logic gate. It outputs a logical 1
only when all of its inputs are 0. Otherwise, the output is 0. It is the inverse of an OR gate and
is used widely in combinational logic circuits.
Transistor-Level Design: A NOR gate can be implemented using CMOS technology with the
following components:
• PMOS transistors: Used to pull the output to the high voltage (logic 1).
• NMOS transistors: Used to pull the output to the low voltage (logic 0).
For a 2-input NOR gate:
• The PMOS transistors are connected in series between the output and the power
supply (VDD).
• The NMOS transistors are connected in parallel between the output and ground
(GND).
• When both inputs are 0, both PMOS transistors conduct, pulling the output to 1 (high).
• If either input is 1, at least one NMOS transistor conducts, pulling the output to 0 (low).

Input A Input B Output (Y)

0 0 1
0 1 0
1 0 0
1 1 0

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Schematic:

Testbench Setup:

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Procedure:
1. Create New Cell for NOR Gate Design
• Select Cell: Click on New View and name it "nor".
2. Design the NOR Gate Using PMOS and NMOS Transistors
• Open the Generic 250nm Devices library, select sym, and use pmos25x and nmos25x
transistors to design the NOR gate as shown in the schematic diagram:
o Connect two PMOS transistors in parallel, followed by two NMOS transistors
in series.
3. Attach Input, Output, and Power Ports
• Attach input ports (A and B) for the inputs and an output port (Z) for the output of
the NOR gate.
• Connect GND and VDD from the misc library for power and ground connections.
4. Generate the Symbol for the NOR Gate
• Navigate to Cell → Generate Symbol.
• Use the port placements by name option, then click Replace to create the symbol for
the NOR gate.
5. Create Test Bench for NOR Gate Simulation
• Go to Cell → New View and change the view type from Symbol to Schematic.
• Rename this schematic as "nor_tb" for the test bench.
6. Insert NOR Gate Symbol into the Test Bench
• Drag the generated NOR gate symbol from the "nor" cell into the "nor_tb" schematic.
7. Connect Power (VDD) and Ground (GND)
• From the misc library, connect VDD and GND to the appropriate power pins of the
NOR gate symbol.
8. Add DC Voltage Source
• Add a VDC source from the Spice Sources library and connect it to the VDD and GND
terminals to provide the necessary supply voltage for the circuit.
9. Simulate Inputs Using VPULSE
• Add two VPULSE sources from the Spice Sources library to simulate the input signals
for A and B.
• Connect the positive terminal of each VPULSE to the input wires A and B, and the
negative terminal to GND.

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Simulation Setup:

Output Waveforms:

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10. Adjust VPULSE Properties

• Change the rise time and fall time of the VPULSE sources from 5ns to 0.01ns.
• Set different period values for inputs A and B to ensure the NOR gate receives all input
combinations.
11. Add Voltage Print Labels
• From the Spice Plot library, add voltage print labels at the input wires (A and B) and
the output wire (Z).
12. Set Up Transient Analysis
• Set the analysis type to TRAN (transient analysis) on the voltage print labels to
evaluate the time-domain response of the NOR gate as inputs vary.
13. Add Device Models Path
• Go to Settings → General and add the library file path for the 250nm process models:
o Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250n
m/Models/Generic_250nm.lib TT.
14. Set Transient Analysis Parameters
• Enter the following values for transient analysis:
o Stop time: 1000ns
o Print start time: 0ns
o Maximum time step: 5ns
o Print time step: 5ns
15. Run the Simulation
• Click Simulation to run the transient analysis.
• If any errors occur, check your schematic connections and the wiring of PMOS, NMOS,
and input/output ports, then rerun the simulation.
16. Verify the Output
• After the simulation completes, verify the timing waveforms against the NOR gate
truth table.

Result:

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DESIGN AND SIMULATION OF AND GATE

Exp No: Date:

Aim:
To design a AND GATE using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
An AND gate is a basic digital logic gate that performs a logical multiplication
operation. The output of an AND gate is 1 (high) only when all its inputs are 1 (high). If any
input is 0 (low), the output will be 0 (low). The AND gate plays a fundamental role in digital
circuits, including arithmetic operations, control systems.
An AND gate can be implemented using CMOS technology. It consists of:
• PMOS transistors: These transistors pull the output to the high voltage (logic 1).
• NMOS transistors: These transistors pull the output to the low voltage (logic 0).
• The PMOS transistors are connected in series between the output and the power
supply (VDD).
• The NMOS transistors are connected in parallel between the output and ground
(GND).
• When both inputs are 1 (high), both NMOS transistors conduct, pulling the output to 0
(low).
• If either input is 0 (low), at least one PMOS transistor will conduct, pulling the output
to 1 (high).

Input A Input B Output (Y)

0 0 0
0 1 0
1 0 0
1 1 1

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Schematic:

Testbench Setup:

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Procedure:
1. Create New Cell for AND Gate Design
• Cell → New View: Create a new view and name it "and".
2. Design the AND Gate Using PMOS and NMOS Transistors
• Open the Generic 250nm Devices library and select pmos25x and nmos25x
transistors from the sym section.
• Use these transistors to design a NAND gate first (two PMOS in series and two NMOS
in parallel).
• After the NAND gate, add an inverter to create the AND gate.
3. Attach Input, Output, and Power Ports
• Attach input ports (A and B) for the inputs and an output port (Z) for the output of
the AND gate.
• Connect VDD and GND from the misc library for the power and ground connections
of the circuit.
4. Generate the Symbol for the AND Gate
• Navigate to Cell → Generate Symbol.
• Use the port placements by name option, and click Replace to generate a symbol
representing the AND gate.
5. Create Test Bench for AND Gate Simulation
• Go to Cell → New View and change the view type from Symbol to Schematic.
• Rename this schematic as "and_tb" for the test bench.
6. Insert AND Gate Symbol into the Test Bench
• Drag the generated AND gate symbol from the "and" cell into the "and_tb" schematic.
7. Connect Power (VDD) and Ground (GND)
• From the misc library, add and connect VDD and GND to the appropriate power pins
of the AND gate symbol.
8. Add DC Voltage Source
• Add a VDC source from the Spice Sources library and connect it to the VDD and GND
terminals to provide the necessary supply voltage for the circuit.
9. Simulate Inputs Using VPULSE
• Add two VPULSE sources from the Spice Sources library to simulate the input
signals for A and B.

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Simulation Setup:

Output Waveforms:

16. Run the Simulation

• Click Simulation to run the transient analysis.
• If any errors occur, double-check your schematic connections, especially the
wiring of PMOS, NMOS, and input/output ports, and rerun the simulation.
17. Verify the Output
• After the simulation completes, check the timing waveforms of the inputs (A
and B) and the output (Z) against the AND gate truth table

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• Connect the positive terminal of each VPULSE to the input wires A and B, and the
negative terminal to GND.
10. Adjust VPULSE Properties
• Change the rise time and fall time of the VPULSE sources from 5ns to 0.01ns.
• Set different period values for inputs A and B to ensure the AND gate gets all the input
combinations.
11. Add Voltage Print Labels
• From the Spice Plot library, add voltage print labels at the input wires (A and B) and
the output wire (Z).
12. Set Up Transient Analysis
• Set the analysis type to TRAN (transient analysis) on the voltage print labels to
measure the time-domain response of the AND gate as inputs vary.
13. Add Device Models Path
• Go to Settings → General and add the library file path for the 250nm process models:
o Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250n
m/Models/Generic_250nm.lib TT.
14. Set Transient Analysis Parameters
• Set the following values for transient analysis:
o Stop time: 1000ns
o Print start time: 0ns
o Maximum time step: 5ns
o Print time step: 5ns
15. Run the Simulation
• Click Simulation to run the transient analysis.
• If any errors occur, double-check your schematic connections, especially the wiring of
PMOS, NMOS, and input/output ports, and rerun the simulation.
16. Verify the Output
• After the simulation completes, check the timing waveforms.

Result:

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DESIGN AND SIMULATION OF OR GATE

Exp No: Date:

Aim:
To design a OR GATE using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
An OR gate is a fundamental digital logic gate that outputs a logical 1 (high) when
at least one of its inputs is 1 (high). If all inputs are 0 (low), the output is 0 (low). OR gates are
essential components in digital circuits, allowing for various functionalities like decision-
making, data routing, and signal processing.

In CMOS technology, an OR gate can be implemented using PMOS and NMOS transistors:
• PMOS transistors connect in parallel between the output and the power supply
(VDD).
• NMOS transistors connect in series between the output and ground (GND).

• When either input is 1, at least one PMOS transistor will conduct, pulling the output to
1.
• If both inputs are 0, both NMOS transistors conduct, pulling the output to 0.

Input A Input B Output (Y)

0 0 0
0 1 1
1 0 1
1 1 1

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Schematic:

Testbench Setup:

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Procedure:
1. Create New Cell for OR Gate Design
• Cell → New View: Create a new view and name it "or".
2. Design the OR Gate Using PMOS and NMOS Transistors
• Open the Generic 250nm Devices library and select pmos25x and nmos25x
transistors from the sym section.
• Using the standard NOR circuit (two PMOS in parallel and two NMOS in series), create
the OR gate by inverting the output of the NOR gate (adding an inverter).
3. Attach Input, Output, and Power Ports
• Attach input ports (A and B) for the inputs and output port (Z) for the output of the
OR gate.
• Connect VDD (power) and GND (ground) from the misc library to the respective
power and ground connections of the circuit.
4. Generate the Symbol for the OR Gate
• Navigate to Cell → Generate Symbol.
• Use the port placements by name option, and click Replace to generate a symbol
representing the OR gate.
5. Create Test Bench for OR Gate Simulation
• Go to Cell → New View and change the view type from Symbol to Schematic.
• Rename this schematic as "or_tb" for the test bench.
6. Insert OR Gate Symbol into the Test Bench
• Drag the generated OR gate symbol from the "or" cell into the "or_tb" schematic.
7. Connect Power (VDD) and Ground (GND)
• From the misc library, add and connect VDD and GND to the appropriate power pins
of the OR gate symbol.
8. Add DC Voltage Source
• Add a VDC source from the Spice Sources library and connect it to the VDD and GND
terminals to provide the necessary supply voltage for the circuit.
9. Simulate Inputs Using VPULSE
• Add two VPULSE sources from the Spice Sources library to simulate the input signals
for A and B.
• Connect the positive terminal of each VPULSE to the input wires A and B, and the
negative terminal to GND.

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Simulation Setup:

Output Waveforms:

Output Waveforms:

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10. Adjust VPULSE Properties

• Change the rise time and fall time of the VPULSE sources from 5ns to 0.01ns.
• Set different period values for the inputs A and B to ensure the OR gate gets all the
input combinations.
11. Add Voltage Print Labels
• From the Spice Plot library, add voltage print labels at the input wires (A and B) and
the output wire (Z).
12. Set Up Transient Analysis
• Set the analysis type to TRAN (transient analysis) on the voltage print labels to
measure the response of the OR gate over time as the inputs vary.
13. Add Device Models Path
• Go to Settings → General and add the library file path for the 250nm process models:
o Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250n
m/Models/Generic_250nm.lib TT.
14. Set Transient Analysis Parameters
• Set the following values for transient analysis:
o Stop time: 1000ns
o Print start time: 0ns
o Maximum time step: 5ns
o Print time step: 5ns
15. Run the Simulation
• Click Simulation to run the transient analysis.
• If any errors occur, double-check your schematic connections, especially the wiring of
PMOS, NMOS, and input/output ports, and rerun the simulation.
16. Verify the Output
• After the simulation completes, check the timing waveforms of the inputs (A and B)
and the output (Z) against the OR gate truth table

Result:

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DESIGN AND SIMULATION OF XOR GATE

Exp No: Date:

Aim:
To design a XOR GATE using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
The XOR (exclusive OR) gate is a fundamental digital logic gate that outputs true or 1
when the number of true inputs is odd, i.e., when the inputs are different. The XOR gate is
widely used in digital circuits, such as arithmetic logic units, error detection, and cryptography,
due to its unique behavior of distinguishing between identical and different inputs.

The XOR gate is a type of binary gate with two inputs and one output. It performs a logical
operation where the output is high (1) when the inputs are different (one input is high, and the
other is low), and the output is low (0) when the inputs are the same (both high or both low).
The XOR gate is often referred to as a parity checker. In circuits, XOR is commonly used to
check whether an even or odd number of inputs are high. When multiple XOR gates are
combined, they can perform parity checks on binary data streams, which is critical for error
detection and correction in communication systems.

For example, if we XOR all the bits in a binary number, the result will be:
• 0 if the number of 1’s is even (even parity).

• 1 if the number of 1’s is odd (odd parity)

Input A Input B Output (Y)

0 0 0
0 1 1
1 0 1
1 1 0

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Schematic:

Testbench Setup:

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Procedure:
1. Create New Cell for XOR Gate

• Cell → New View: Create a new view and name it "xor". This will be used for the
XOR gate design.

2. Design XOR Circuit Using NAND Gates

• Open the Generic 250nm Devices library and select NAND gates from the sym
section.
• Use 4 NAND gates to design the XOR gate, based on the standard schematic for XOR
using NAND gates.

3. Attach Input and Output Ports

• Attach input ports labeled A and B for the XOR gate's inputs.
• Attach an output port labeled Z for the XOR gate’s output.

4. Generate the Symbol for XOR Gate

• Navigate to Cell → Generate Symbol.

• Use the port placements by name feature, and click Replace to generate a symbol for
the XOR gate.

5. Create Test Bench for XOR Simulation

• Go to Cell → New View and change the view type from Symbol to Schematic.
• Rename the schematic as "xor_tb" for the test bench.

6. Insert XOR Symbol into Test Bench

• Drag the generated XOR gate symbol from the "xor" cell into the "xor_tb" schematic.

7. Connect Power (VDD) and Ground (GND)

• From the misc library, add and connect VDD (positive power) and GND (ground) to
the power pins of the XOR gate.

8. Add DC Voltage Source

• Add a VDC source from the Spice Sources library and connect it to the VDD and
GND terminals. This will provide the necessary supply voltage.

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9. Set Up Additional VDC for Ground Reference

• Add an additional VDC symbol for the ground reference.

o Connect Vss_inherent (ground pin) to the negative terminal of the VDC.
o Connect GND to the positive terminal using the Misc library.

10. Simulate Inputs Using VPULSE

• Add two VPULSE sources from the Spice Sources library. These will generate
variable input signals for A and B.
• Connect the positive terminal of each VPULSE to the input wires A and B, and connect
the negative terminal to GND.

11. Adjust VPULSE Properties

• Change the rise time and fall time of the VPULSE sources from 5ns to 0.01ns.
• Set different pulse periods for inputs A and B, so that all possible input combinations
are covered:
o (A, B) = (0,0), (0,1), (1,0), (1,1).

12. Add Voltage Print Labels

• From the Spice Plot library, add voltage print labels at the input wires (A and B) and
at the output wire (Z).

13. Set Up Transient Analysis

• Set the analysis type to TRAN (transient analysis) on the voltage print labels to track
the XOR gate’s behavior over time as the inputs change.

14. Add Device Models Path

• Go to Settings → General and add the library file path for the 250nm process models:
o Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250n
m/Models/Generic_250nm.lib TT.

15. Set Transient Analysis Parameters

• Set the following values for transient analysis:

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Simulation Setup:

o Stop time: 1000ns

o Print start time: 0ns
o Maximum time step: 5ns
o Print time step: 5ns

Output Waveforms:

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16. Run Simulation

• Click Simulation to run the transient analysis.

• If errors occur, check for issues such as incorrect wiring of NAND gates or improper
connections, and rerun the simulation after making corrections.

17. Verify Output

• After the simulation completes, verify the timing waveforms of the inputs (A and B)
and the output (Z) against the XOR truth table.

Result:

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DESIGN AND SIMULATION OF XNOR GATE

Exp No: Date:

Aim:
To design a XNOR GATE using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s
timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
The XNOR (exclusive NOR) gate is a fundamental digital logic gate that outputs true
or 1 when the number of true inputs is even, i.e., when the inputs are the same. The XNOR gate
is widely used in digital circuits such as equality checkers, data comparators, and certain types
of error detection due to its behavior of identifying when inputs are identical.

The XNOR gate is a binary gate with two inputs and one output. It performs a logical operation
where the output is high (1) when the inputs are the same (both high or both low), and the
output is low (0) when the inputs are different (one input is high, and the other is low).
Essentially, the XNOR gate is the complement of the XOR gate, as it produces the opposite
output for the same input conditions.
The XNOR gate is commonly referred to as an equality gate or equivalence gate because it
checks for the equivalence of the inputs. In digital circuits, XNOR gates are often used in
comparison operations, as they indicate when two binary values are identical.
An example of XNOR output in a binary number would be:

• 1 if the number of 1’s is even (even parity).

• 0 if the number of 1’s is odd (odd parity).

Input A Input B Output (Y)

0 0 1
0 1 0
1 0 0
1 1 1

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Procedure:
1. Create New Cell for the XNOR Design
• Cell → New View: Create a new view, give it the name "xnor".
2. Select NAND Gates from the Library
• Open the Generic 250nm Devices library and select NAND gates from the sym
section.
• Instead of using PMOS and NMOS transistors, build the XNOR gate using 5 NAND
gates, as per the XNOR schematic (common design to use NAND for XNOR logic).
3. Attach Input and Output Ports
• Attach input and output ports to serve as the inputs A and B, and the output Z,
which will be the final XNOR output.
4. Generate the Symbol for XNOR Gate
• Go to Cell → Generate Symbol.
• Use the port placements by name feature, and click Replace to generate a symbol
for your XNOR gate.
5. Create Test Bench for Simulation
• Select Cell → New View, change the view type from Symbol to Schematic.
• Rename the schematic to "xnor_tb" for the test bench design.
6. Insert XNOR Symbol in Test Bench
• Drag the generated XNOR symbol (from your "xnor" design) into the "xnor_tb"
schematic.
7. Add Power Connections (VDD and GND)
• From the misc library, connect VDD (positive power supply) and GND (ground) to
the appropriate power pins of the XNOR gate.
8. Add DC Voltage Source
• Add a VDC source from the Spice Sources library and connect it to the VDD and
GND connections, providing the necessary supply voltage for the circuit.
9. Set Up Additional VDC for Ground
• Add an additional VDC symbol for ground reference, connecting vss_inherent
(ground pin) to the negative terminal of VDC and ground to the positive terminal
from the misc library.

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Schematic:

Testbench Setup:

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10. Simulate Inputs with VPULSE

• Add two VPULSE sources from the Spice Sources library, which will simulate the
varying input signals for A and B.
o Connect the positive terminal of each VPULSE to the input wires (A and B),
and the negative terminal to GND.
11. Modify Pulse Properties
• Adjust the rise time and fall time of the VPULSE sources from 5ns to 0.01ns.
• Assign different periods for inputs A and B, so the XNOR gate receives all the correct
input combinations (0,0 → 0,1 → 1,0 → 1,1).
12. Add Voltage Print Labels
• From the Spice Plot library, place voltage print labels at the input wires (A and B)
and at the XNOR output wire (Z).
13. Set Up Transient Analysis
• On the voltage print labels, set the analysis type to TRAN (transient analysis) to
evaluate the circuit’s time-domain response (how the output changes over time based
on the inputs).
14. Add Library File Path for Device Models
• In Settings → General, add the library file path for the 250nm process technology
models:
o Path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250n
m/Models/Generic_250nm.lib TT.
15. Set Transient Analysis Parameters
• Enter the following values for the transient analysis:
o Stop time: 1000ns
o Print start time: 0ns
o Maximum time step: 5ns
o Print time step: 5ns
16. Run Simulation
• Click on Simulation to run the transient analysis.
• A new window will open, and if no errors occur, the simulation will proceed.

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Simulation Setup:

Output Waveforms:

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• If errors are encountered, check your wiring and connections between the NAND gates
and ports, and then re-run the simulation.
17. Verify the Output
• After the simulation is complete, verify the timing waveforms against the XNOR truth
table to ensure that the output (Z) matches the expected results for different
combinations of inputs A and B.

Result:

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DESIGN AND SIMULATION OF HALF ADDER

Exp No: Date:

Aim:
To design a Half Adder using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A Half Adder is one of the basic building blocks in digital electronics, used for the
addition of two single-bit binary numbers. The half adder is a combinational logic circuit,
meaning its output depends only on the present input values and not on any previous history or
state.

The primary purpose of a half adder is to add two binary digits and provide two results:
• Sum: The result of the addition (without considering the carry).

• Carry: The overflow from the sum, which is carried to the next more significant bit in
case of multi-bit addition.

Since NAND gates are universal gates, any logic circuit, including a half adder, can be
implemented using only NAND gates. This is significant in the design of integrated circuits
because NAND gates are often more efficient to manufacture.

Input A Input B Sum (S) Carry(C)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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Procedure:
1. Select the Cell Option:
• Click on New View and assign a name to the view, such as "HA" (Half Adder).
2. Select Logic Gates:
• Click on the Generic 250nm Devices library and select the symbol (sym) for NAND
gates.
• Instead of using PMOS and NMOS devices, use 5 NAND gates to design the Half
Adder logic circuit as per the schematic for a Half Adder.
o Inputs: A and B.
o Outputs: Sum and Carry (Cout).
• Wire the gates properly to create the Half Adder logic:
o Sum = A ⊕ B (using NAND gates).
o Carry = A · B (using NAND gates).
3. Attach Input and Output Ports:
• Attach input ports for A and B from the menu.
• Attach output ports for Sum and Cout (Half Adder outputs).
• Connect the inputs and outputs accordingly to complete the Half Adder circuit.
4. Generate Symbol:
• Select Cell, click on Generate Symbol, enter the "port placements by name" details
for the inputs (A, B) and outputs (Sum, Cout), and click Replace.
• This will generate a symbol for your Half Adder circuit.
5. Create a Test Bench:
• Select Cell, click on New View, change the view type from Symbol to Schematic, and
rename "HA" to "HA_tb" (test bench for the Half Adder).
• Drag the generated Half Adder symbol from "HA" to the schematic of "HA_tb".
6. Connect Ports and Power:
• Connect the input and output ports (A, B for inputs and Sum, Cout for outputs) to
the Half Adder symbol.
• Also, connect gnd and vdd from the misc library to power the Half Adder.

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Schematic:

Testbench Setup:

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7. Add DC Voltage Supply:

• Add vdc from the Spice Sources library and connect vdc to the vdd_inherent and gnd
terminals to provide DC voltage for the circuit.
8. Add Negative DC Supply (Optional):
• Add vdc symbol0 and connect the vss_inherent terminal to the negative terminal of
vdc symbol0, and gnd to the positive terminal from the misc library.
9. Add Clock Pulse Inputs:
• Add vpulse from the Spice Sources library, and attach the positive terminal of vpulse
to the input wires (A and B) and the negative terminal to gnd.
• Use a vpulse source for both A and B to simulate changing input signals.
10. Set Properties for vpulse:
• Select vpulse and modify its properties:
o Rise time: Set from 5ns to 0.01ns.
o Fall time: Set from 5ns to 0.01ns.
o Define the period differently for the two input terminals A and B, ensuring that
the Half Adder gets the correct input combinations over time.
11. Add Voltage Print Labels:
• Attach voltage print labels to the input wires (A and B) and the output wires (Sum and
Cout) using the Spice Plot library.
• This will allow observation of the input/output behavior during simulation.
12. Set Up Transient Analysis:
• Set the property to TRAN (transient analysis) on both the input and output voltage
print labels to analyze the time-domain response of the Half Adder circuit.
13. Add Library File Path:
• Click on Settings, select General, and add the library file path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250nm/Mod
els/Generic_250nm.lib TT.

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Simulation Setup:

Output Waveforms:

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14. Configure Transient Analysis:

• Select Transient Analysis and enter the following values:
o Stop time: 1000n
o Print start time: 0n
o Maximum time step: 5n
o Print time step: 5n
15. Run Simulation:
• Click on Simulation to run the simulation. A window should open showing 0 errors.
• If any errors occur, carefully recheck the schematic connections, especially the wiring
of the NAND gates.
16. Check Timing Simulation Waveforms:
• Observe the timing simulation waveforms for inputs (A and B) and outputs (Sum
and Cout).
o Verify that the waveforms match the Half Adder truth table:
▪ Sum = A ⊕ B (XOR using NAND gates).
▪ Cout = A · B (AND using NAND gates).
17. Save the Design:
• Once the Half Adder operates correctly according to its truth table, save the design.

Result:

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DESIGN AND SIMULATION OF FULL ADDER

Exp No: Date:

Aim:
To design a Full Adder using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A full adder is a combinational logic circuit used to add three binary bits, producing a
sum and a carry. The three bits are the two input bits to be added and a carry bit from a previous
addition. A full adder is composed of two half adders and an OR gate when using basic logic
gates. However, the full adder can also be implemented using only NAND gates, which are
considered universal gates because any logic gate can be constructed using just NAND gates.
A full adder takes three inputs:
• A: First binary input
• B: Second binary input
• Cin: Carry input (from the previous stage of addition)
And produces two outputs:
• Sum: The sum bit
• Cout: The carry output, which is passed to the next stage.

A B Cin Sum Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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Schematic:

Testbench Setup:

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Procedure:
1. Select the Cell Option:
• Click on New View and assign a name to it, such as "FA" (Full Adder).
2. Select Logic Gates:
• Click on the Generic 250nm Devices library, and select the symbol (sym) for NAND
gates. Instead of using PMOS and NMOS devices, use these NAND gates to design
the Full Adder circuit.
• The Full Adder logic using NAND gates requires at least 10 NAND gates, arranged
according to the schematic for a Full Adder.
o 3 input signals: A, B, and Cin (carry-in).
o 2 output signals: Sum and Cout (carry-out).
• Build the Full Adder by following a schematic that uses only NAND gates for the logic.
3. Attach Input and Output Ports:
• Attach input ports from the menu for inputs A, B, and Cin.
• Attach output ports for Sum and Cout to represent the outputs.
• Ensure that the wiring for the inputs and outputs is properly connected.
4. Generate Symbol:
• Select Cell, click on Generate Symbol, enter the "port placements by name" details
for the input (A, B, Cin) and output (Sum, Cout) signals, and click Replace.
• A symbol representing your Full Adder circuit will be generated.
5. Create Test Bench:
• Click on the Cell option, select New View, change the view type from Symbol to
Schematic, and rename "FA" to "FA_tb" for the test bench.
• Drag the generated Full Adder symbol from "FA" into the schematic of "FA_tb".
6. Connect Ports and Power:
• Connect the input ports (A, B, Cin) and output ports (Sum, Cout) to the Full Adder
symbol.
• Also connect gnd and vdd from the misc library to power the Full Adder circuit.
7. Add DC Voltage Supply:
• Add vdc from the Spice Sources library next to the symbol, and connect vdc to the
vdd_inherent and gnd terminals to provide the necessary DC voltage for the circuit.

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8. Add Negative DC Supply:

• Add vdc symbol0 and connect the vss_inherent terminal to the negative terminal of
vdc symbol0 and gnd to the positive terminal from the misc library.
9. Add Clock Pulse Inputs:
• Add vpulse from the Spice Sources library, and attach the positive terminals of the
vpulse sources to the input wires (A, B, Cin) and the negative terminals to gnd.
• Each vpulse will simulate the changing input signals for A, B, and Cin.
10. Set Properties for vpulse:
• Select vpulse and change its properties:
o Rise time: 5ns to 0.01ns.
o Fall time: 5ns to 0.01ns.
o Set the period differently for each input terminal to ensure the Full Adder
receives the correct input combinations (such as A and B changing at different
times relative to Cin).
11. Add Voltage Print Labels:
• Attach voltage print labels to the input wires (A, B, Cin) and the output wires (Sum,
Cout) using the Spice Plot library.
• This will allow you to observe the input and output behavior during the simulation.
12. Set Up Transient Analysis:
• Set the property to TRAN (transient analysis) on the output and input voltage print
labels to analyze the time-domain response of the Full Adder circuit.
13. Add Library File Path:
• Click on Settings, select General, and add the library file path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250nm/Mod
els/Generic_250nm.lib TT
14. Configure Transient Analysis:
• Select Transient Analysis and enter the following values:
o Stop time: 1000n
o Print start time: 0n
o Maximum time step: 5n
o Print time step: 5n

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Simulation Setup:

Output Waveforms:

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15. Run Simulation:

• Click on Simulation to run the simulation. A simulation window should open with 0
errors.
• If any errors occur, recheck the schematic connections, especially the correct wiring of
the NAND gates in the Full Adder.
16. Check Timing Simulation Waveforms:
• Observe the timing simulation waveforms for the inputs (A, B, Cin) and outputs
(Sum, Cout).
o Verify that the Full Adder works according to its truth table:
▪ Sum = A ⊕ B ⊕ Cin (XOR operation using NAND gates).
▪ Cout = A · B + (A ⊕ B) · Cin (Carry-out logic using NAND gates).
17. Save the Design:
• Once the Full Adder is working correctly, save the design.

Result:

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DESIGN AND SIMULATION OF D-FLIP FLOP

Exp No: Date:

Aim:
To design a D Flip Flop using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s timing
simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A D flip-flop (Data or Delay flip-flop) is one of the most commonly used types of flip-
flops in digital circuits. It captures the value of the data input (D) on the rising or falling edge
of a clock signal (CLK) and stores that value until the next clock cycle.
1. D Input: The input to the D flip-flop is the D (Data) input. It represents the value that
needs to be stored in the flip-flop.
2. Clock Input (CLK): The flip-flop changes its state only when there is a transition in the
clock signal (typically on the rising or falling edge).
3. Q Output: The flip-flop's output is Q, which holds the value that was sampled at the D
input when the clock transitioned.
4. Q' Output: This is the complement (inverse) of the Q output.
The D flip-flop is designed such that the output Q takes the value of D only when the clock
signal allows it to do so.
When the clock signal is low, the master latch is transparent, and the D input is passed to the
master latch.
When the clock signal is high, the slave latch updates to hold the value that was stored in the
master latch, and the output Q is updated.

Clk D Qn
0 0 Qn
0 1 Qn
1 0 0
1 1 1

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Schematic:

Testbench Setup:

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Procedure:
1. Select the Cell Option:
• Click on New View and assign a name, such as "DFF" (D Flip-Flop).
2. Select Logic Gates:
• Instead of using PMOS and NMOS devices, select NAND gates or other gates
necessary to implement a D Flip-Flop from the Generic 250nm Devices library.
• Design the circuit for the D Flip-Flop using NAND gates or any other necessary
components. The typical D Flip-Flop logic requires at least 6 gates (2 NAND gates
for the latch and 2 for the clock gating mechanism).
• Reference the schematic for a D Flip-Flop logic circuit.
3. Attach Input and Output Ports:
• Add the input port D (data) and Clk (clock), as well as output ports Q and Q'
(complementary output) from the menu. These represent the inputs and outputs for
the D Flip-Flop.
• Connect the necessary wiring for the D input, clock signal, and the resulting Q and
Q' outputs.
4. Generate Symbol:
• Click on Cell, select Generate Symbol, and enter the "port placements by name"
details. Click Replace. A symbol representing the D Flip-Flop circuit will be
generated.
5. Create a Test Bench:
• Select Cell, click on New View, change the view type from Symbol to Schematic,
and rename "DFF" to "DFF_tb" for the test bench.
• Drag the generated D Flip-Flop symbol from "DFF" to "DFF_tb".
6. Connect Ports and Power:
• Connect the input and output ports (D, Clk, Q, and Q') to the symbol, and also
connect gnd and vdd from the misc library to power the circuit.
7. Add DC Voltage Supply:
• Add vdc from the Spice Sources library next to the symbol, and connect vdc to the
vdd_inherent and gnd terminals to provide the necessary DC voltage.
8. Add Clock Pulse:
• Add a vpulse from the Spice Sources library, and attach its positive terminal to the
Clk (clock) input wire and the negative terminal to gnd. This simulates the clock
signal.
• Set vpulse properties such as the rise time, fall time, pulse width, and period to
simulate the clock correctly.
9. Simulate Data Input:
• Add another vpulse for the D input. Attach the positive terminal of vpulse to the D
input wire and the negative terminal to gnd. This will simulate the changing data
input to the flip-flop.
• Make sure to adjust the properties (rise time, fall time, and period) to match the
timing behavior of the D input relative to the clock.

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Simulation Setup:

Output Waveforms:

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10. Add Voltage Print Labels:

• Attach voltage print labels to the input wires (D and Clk) and the output wires (Q
and Q') using the Spice Plot library. These will allow you to observe the input and
output behavior in the simulation.
11. Set Up Transient Analysis:
• Set the properties of the voltage print labels to TRAN (transient analysis) to
analyze the time-domain response of the circuit.
12. Add Library File Path:
• Click on Settings, select General, and add the library file path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250nm/
Models/Generic_250nm.lib TT
13. Configure Transient Analysis:
• Select Transient Analysis and enter the following values:
o Stop time: 1000n
o Print start time: 0n
o Maximum time step: 5n

o Print time step: 5n

14. DC Sweep Analysis:
• This step is not necessary for this experiment, as the D Flip-Flop design primarily
involves time-domain analysis.
15. Run Simulation:
• Click on Simulation to run the simulation. If any errors occur, recheck the
schematic connections, particularly the wiring of the NAND gates and flip-flop
logic.
16. Verify Timing Simulation Waveforms:
• Observe the timing simulation waveforms for the inputs (D and Clk) and outputs
(Q and Q') to verify the correct behavior of the D Flip-Flop. The output Q should
follow the input D when the clock Clk is active (e.g., rising edge-triggered or falling
edge-triggered depending on design).
17. Save the Design:
• Once the D Flip-Flop is working correctly, save the design.

Result:

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DESIGN AND SIMULATION OF T-FLIP FLOP

Exp No: Date:

Aim:
To design a T-Flip Flop using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s
timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A T flip-flop (Toggle flip-flop) is a fundamental building block in digital electronics
used in circuits that require toggling between two states. It is a variant of the JK flip-flop, but
with a single input (T). The T flip-flop changes (toggles) its output state with each clock pulse
if the input TTT is high. If TTT is low, the flip-flop retains its previous state.
o The T input controls whether the flip-flop toggles or holds its current state.
o When T=0, the flip-flop maintains its current output state.
o When T=1, the flip-flop toggles its state from 0 to 1 or from 1 to 0.
o The output toggling or holding only happens when there is a transition in the
clock signal.
o Q represents the current output of the flip-flop.
o The value of Q toggles if T=1 on the clock edge, or remains unchanged if T=0.
o Q′ is the complement (inverse) of the Q output. If Q=1, then Q′=0, and vice
versa.

Clk T Qn

0 0 Qn

0 1 Qn

1 0 0

1 1 Qn’

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Schematic:

Testbench Setup:

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Procedure:
1. Select the Cell Option:
• Click on New View and assign a name, such as "TFF" (T Flip-Flop).
2. Select Logic Gates:
• Instead of using PMOS and NMOS devices, select necessary gates from the Generic
250nm Devices library to implement a T Flip-Flop.
3. Attach Input and Output Ports:
• Add input ports T (data input), and Clk (clock), as well as output ports Q and Q'
(complementary output) from the menu.
• Connect the necessary wiring for the T input, clock signal, and the resulting Q and Q'
outputs.
4. Generate Symbol:
• Click on Cell, select Generate Symbol, and enter the "port placements by name" details.
Click Replace.
• A symbol representing the T Flip-Flop circuit will be generated.
5. Create a Test Bench:
• Select Cell, click on New View, change the view type from Symbol to Schematic, and
rename "TFF" to "TFF_tb" for the test bench.
• Drag the generated T Flip-Flop symbol from "TFF" to "TFF_tb."
6. Connect Ports and Power:
• Connect the input and output ports (T, Clk, Q, and Q') to the symbol, and also connect
gnd and vdd from the misc library to power the circuit.
7. Add DC Voltage Supply:
• Add vdc from the Spice Sources library next to the symbol and connect vdc to the
vdd_inherent and gnd terminals to provide the necessary DC voltage.
8. Add Clock Pulse:
• Add a vpulse from the Spice Sources library, and attach its positive terminal to the Clk
input wire and the negative terminal to gnd. This simulates the clock signal.
• Set vpulse properties such as rise time, fall time, pulse width, and period to simulate
the clock correctly.
9. Simulate T Data Input:
• Add another vpulse for the T input. Attach the positive terminal of vpulse to the T
input wire and the negative terminal to gnd. This will simulate the changing data
input to the flip-flop.

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Simulation Setup:

Output Waveforms:

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• Make sure to adjust the properties (rise time, fall time, and period) to match the
timing behaviour of the T input relative to the clock.
10. Add Voltage Print Labels:
• Attach voltage print labels to the input wires (T and Clk) and the output wires (Q
and Q') using the Spice Plot library. These will allow you to observe the input and
output behavior in the simulation.
11. Set Up Transient Analysis:
• Set the properties of the voltage print labels to TRAN (transient analysis) to
analyze the time-domain response of the circuit.
12. Add Library File Path:
• Click on Settings, select General, and add the library file path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250nm/
Models/Generic_250nm.lib TT
13. Configure Transient Analysis:
• Select Transient Analysis and enter the following values:
o Stop time: 1000n
o Print start time: 0n
o Maximum time step: 5n
o Print time step: 5n
14. Run Simulation:
• Click on Simulation to run the simulation. If any errors occur, recheck the
schematic connections, particularly the wiring of the NAND gates and flip-flop
logic.
15. Verify Timing Simulation Waveforms:
• Observe the timing simulation waveforms for the inputs (T and Clk) and outputs
(Q and Q') to verify the correct behavior of the T Flip-Flop. The output Q should
follow the input T when the clock Clk is active (e.g., rising edge-triggered or falling
edge-triggered depending on design).
16.Save the Design:
• Once the T Flip-Flop is working correctly, save the design.

Result:

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DESIGN AND SIMULATION OF 4-BIT COUNTER

Exp No: Date:

Aim:
To design a 4-bit counter using Mentor Graphics - Tanner Tools v2021.2 and to verify it’s
timing simulation.

Software Required:
Mentor Graphics - Tanner Tools v2021.2

Hardware Required:
Personal Computer

Theory:
A 4-bit asynchronous counter, also known as a ripple counter, is a sequential digital
circuit that counts in binary from 0 to 15 (for a 4-bit counter) and then resets back to 0.
Asynchronous counters are called "ripple counters" because the clock signal is applied only to
the first flip-flop, and the toggling of other flip-flops happens asynchronously in a ripple-like
fashion as the output of one flip-flop triggers the next.
• A 4-bit asynchronous counter is typically built using 4 D or JK flip-flops, each
representing one bit of the counter (Q0, Q1, Q2, Q3).
• The flip-flops are connected in such a way that each flip-flop toggles when the previous
one makes a transition from 1 to 0 (falling edge).
• The clock signal is applied only to the first flip-flop (LSB flip-flop, Q0). Subsequent
flip-flops get their clock from the output of the previous flip-flop.
• The counter produces a 4-bit binary output, represented by Q3 (MSB), Q2, Q1, and
Q0 (LSB).
• The count starts from 0000 (0 in decimal) and continues up to 1111 (15 in decimal),
after which it resets back to 0000.

Clock
Q3 Q2 Q1 Q0 Binary Decimal
Pulse
0 0 0 0 0 0 0
1 0 0 0 1 1 1
2 0 0 1 0 10 2
3 0 0 1 1 11 3
4 0 1 0 0 100 4
... ... ... ... ... ... ...
15 1 1 1 1 1111 15
16 0 0 0 0 0 0

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Procedure:
1. Select the Cell Option:
• Click on New View and assign a name, such as "Counter_4bit" for the 4-bit counter.
2. Select Logic Gates and Flip-Flops:
• For a 4-bit counter, you’ll need T or JK flip-flops to store each bit of the counter.
• Choose NAND gates, AND gates, and flip-flops from the Generic 250nm Devices
library.
• Design the circuit by cascading four flip-flops (one for each bit), with the clock input
of each flip-flop connected to the output of the previous one (for a ripple counter).
o A 4-bit counter typically uses the output of one flip-flop to clock the next in
sequence, resulting in a binary count from 0 to 15.
• Reference the schematic for a 4-bit binary counter to guide your design.
3. Attach Input and Output Ports:
• Add the clock input port (Clk) and output ports Q0, Q1, Q2, and Q3 to represent the
counter outputs.
• Connect the necessary wiring for the clock signal (Clk) and the resulting 4-bit outputs
(Q0, Q1, Q2, Q3) from the flip-flops.
• Optionally, add a Reset input to reset the counter to 0.
4. Generate Symbol:
• Click on Cell, select Generate Symbol, and enter the "port placements by name"
details. Click Replace.
• A symbol representing the 4-bit counter circuit will be generated.
5. Create a Test Bench:
• Select Cell, click on New View, change the view type from Symbol to Schematic, and
rename "Counter_4bit" to "Counter_4bit_tb" for the test bench.
• Drag the generated 4-bit counter symbol from "Counter_4bit" to "Counter_4bit_tb."
6. Connect Ports and Power:
• Connect the input port (Clk) and output ports (Q0, Q1, Q2, Q3) to the symbol, and also
connect gnd and vdd from the misc library to power the circuit.
7. Add DC Voltage Supply:
• Add vdc from the Spice Sources library next to the symbol, and connect vdc to the
vdd_inherent and gnd terminals to provide the necessary DC voltage.

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Schematic:

Testbench Setup:

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8. Add Clock Pulse:

• Add a vpulse from the Spice Sources library, and attach its positive terminal to the Clk
input wire and the negative terminal to gnd. This simulates the clock signal that drives
the counter.
• Set vpulse properties such as rise time, fall time, pulse width, and period to simulate
the clock correctly.
• You may want to set a periodic clock signal with a fast enough period to allow the
counter to go through several cycles.
9. Simulate Data Inputs (Optional):
• If you included a Reset input, add another vpulse for the Reset signal. Attach the
positive terminal of vpulse to the Reset input wire and the negative terminal to gnd.
Adjust the properties to simulate the Reset signal.
10. Add Voltage Print Labels:
• Attach voltage print labels to the input wire (Clk) and the output wires (Q0, Q1, Q2,
Q3) using the Spice Plot library. These will allow you to observe the input clock and
output behavior in the simulation.
11. Set Up Transient Analysis:
• Set the properties of the voltage print labels to TRAN (transient analysis) to analyze
the time-domain response of the circuit.
12. Add Library File Path:
• Click on Settings, select General, and add the library file path:
/home/software/MentorGraphics/TannerTools_v2021.2/Process/Generic_250nm/Mod
els/Generic_250nm.lib TT
13. Configure Transient Analysis:
• Select Transient Analysis and enter the following values:
o Stop time: 1000n (this will depend on how many cycles you want to observe)
o Print start time: 0n
o Maximum time step: 5n
o Print time step: 5n

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Simulation Setup:

Output Waveforms:

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14. Run Simulation:

• Click on Simulation to run the simulation. If any errors occur, recheck the schematic
connections, particularly the wiring of the flip-flops and gates.
• Ensure that the clock signal properly drives the flip-flops, and that each flip-flop is
connected to the output of the previous one.
15. Verify Timing Simulation Waveforms:
• Observe the timing simulation waveforms for the inputs (Clk) and outputs (Q0, Q1,
Q2, Q3) to verify the correct behavior of the 4-bit counter.
o The Q0, Q1, Q2, and Q3 outputs should represent a binary count from 0 to 15.
o Q0 is the least significant bit (LSB) and toggles with every clock pulse.
o Q1 toggles after every two clock pulses, Q2 after four, and Q3 after eight,
resulting in a 4-bit binary count.
16. Save the Design:
• Once the 4-bit counter is working correctly, save the design.

Result:

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