TC7660S

Super Charge Pump DC-to-DC Voltage Converter

Features Package Types
• Oscillator boost from 10 kHz to 45 kHz PDIP/SOIC
• Converts +5V Logic Supply to ±5V System
• Wide Input Voltage Range: +1.5V to +12V BOOST 1 8 V+
• Efficient Voltage Conversion (99.9%, typical)
CAP+ 2 7 OSC
• Excellent Power Efficiency (98%, typical) TC7660S LOW
GND 3 6
• Low Power Consumption: 80 µA (typical) @ VIN = 5V VOLTAGE (LV)
• Low Cost and Easy to Use CAP- 4 5 VOUT
- Only Two External Capacitors Required
• Available in 8-Pin Small Outline (SOIC) and 8-Pin
PDIP Packages General Description
• Improved ESD Protection (10 kV HBM)
• No External Diode Required for High-Voltage The TC7660S device is a pin-compatible replacement
Operation for the industry standard 7660 charge pump voltage
converter. It converts a +1.5V to +12V input to a corre-
Applications sponding -1.5V to -12V output using only two low-cost
capacitors, eliminating inductors and their associated
• RS-232 Negative Power Supply cost, size and electromagnetic interference (EMI).
• Simple Conversion of +5V to ±5V Supplies Added features include an extended supply range to
• Voltage Multiplication VOUT = ± n V+ 12V, and a frequency boost pin for higher operating fre-
quency, allowing the use of smaller external capacitors.
• Negative Supplies for Data Acquisition Systems
and Instrumentation The on-board oscillator operates at a nominal fre-
quency of 10 kHz. Frequency is increased to 45 kHz
when pin 1 is connected to V+. Operation below 10 kHz
(for lower supply current applications) is possible by
connecting an external capacitor from OSC to ground
(with pin 1 open).
The TC7660S is available in 8-Pin PDIP and 8-Pin
Small Outline (SOIC) packages in commercial and
extended temperature ranges.

 2001-2015 Microchip Technology Inc. DS20001467C-page 1

TC7660S
Functional Block Diagram

V+ CAP+

8 2
1
BOOST

7 RC Voltage 4
OSC 2 Level CAP-
Oscillator Translator
6
LV 5
VOUT
Internal
Internal
Voltage
Voltage
Regulator
Regulator

Logic
Network
TC7660S
3
GND

DS20001467C-page 2  2001-2015 Microchip Technology Inc.

 TC7660S
1.0 ELECTRICAL Notice†: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
CHARACTERISTICS
This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings† indicated in the operational sections of this
Supply Voltage ................................................................+13V specification is not intended. Exposure to maximum
LV, Boost, and OSC Inputs Voltage: (Note 1) rating conditions for extended periods may affect
...................................-0.3V to (V+ + 0.3V) for V+ < 5.5V device reliability.
......................... (V+ – 5.5V) to (V+ + 0.3V) for V+ > 5.5V
Current into LV ......................................... 20 µA for V+ > 3.5V Note 1: Connecting any input terminal to
Output Short Duration (VSUPPLY  5.5V)............... Continuous voltages greater than V+ or less than
Package Power Dissipation: (TA  +70°C) (Note 2) GND may cause destructive latch-up. It
8-Pin PDIP ..........................................................730 mW is recommended that no inputs from
8-Pin SOIC ..........................................................470 mW
sources operating from external
Lead Temperature (Soldering, 10s) .... ....................... +300°C
supplies be applied prior to “power up” of
the TC7660S.
2: Derate linearly above +50°C by
5.5 mW/°C.

ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with
V+ = 5V, COSC = 0, refer to test circuit in Figure 4-1.
Parameters Sym. Min. Typ. Max. Units Conditions
Supply Current I+ — 80 160 µA RL = 
(Boost pin OPEN or GND)
— — 180 0°C  TA  +70°C
— — 180 -40°C  TA  +85°C
— — 200 -55°C  TA  +125°C
+
Supply Current I — — 300 µA 0°C  TA  +70°C
(Boost pin = V+)
— — 350 -40°C  TA  +85°C
— — 400 -55°C  TA  +125°C
Supply Voltage Range, V+H 3.0 — 12 V Min. TAMax, RL = 10 k, LV Open
High
Supply Voltage Range, Low V+L 1.5 — 3.5 V Min. TAMax, RL = 10 k, LV to GND
Output Source Resistance ROUT — 60 100  IOUT = 20 mA
— 70 120 IOUT = 20 mA, 0°C  TA  +70°C
— 70 120 IOUT = 20 mA, -40°C  TA  +85°C
— 105 150 IOUT = 20 mA, -55°C  TA  +125°C
— — 250 V+ = 2V, IOUT = 3 mA, LV to GND
0°C  TA  +70°C
— — 400 V+ = 2V, IOUT = 3 mA, LV to GND
-55°C  TA  +125°C
Oscillator Frequency fOSC — 10 — kHz Pin 7 open, Pin 1 open or GND
45 Boost Pin = V+
Power Efficiency PEFF 96 98 — % RL = 5 kBoost Pin Open
95 98 — TMIN  TA  TMAX; Boost Pin Open
— 88 — Boost Pin = V+

 2001-2015 Microchip Technology Inc. DS20001467C-page 3

TC7660S
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with
V+ = 5V, COSC = 0, refer to test circuit in Figure 4-1.
Parameters Sym. Min. Typ. Max. Units Conditions
Voltage Conversion VOUTEFF 99 99.9 — % RL = 
Efficiency
Oscillator Impedance ZOSC — 1 — M V+ = 2V
— 100 — k V+ = 5V

TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with
V+ = 5V, COSC = 0, refer to test circuit in Figure 4-1.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature Range TA 0 — +70 °C C suffix
TA -40 — +85 °C E suffix
TA -40 — +125 °C V suffix
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8LD PDIP JA — 89.3 — °C/W
Thermal Resistance, 8LD SOIC JA — 148.5 — °C/W

DS20001467C-page 4  2001-2015 Microchip Technology Inc.

 TC7660S
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 4-1.

IN
12 60

OSCILLATOR FREQUENCY (kHz)

OSCILLATOR FREQUENCY (kHz)

10 50

8 40
VIN = 5V
6 VIN = 5V 30
VIN = 12V
4 20
VIN = 12V
2 10

0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 2-1: Unloaded Oscillator FIGURE 2-4: Unloaded Oscillator

Frequency vs. Temperature. Frequency vs. Temperature with Boost Pin = VIN.
VOLTAGE CONVERSION EFFICIENCY (%)

1000 101.0

800 100.5
Without Load
VIN = 12V 100.0
600
IDD (μA)

99.5
400
10K Load
99.0
200
VIN = 5V 98.5
TA = 25°C
0 98.0
-40 -20 0 20 40 60 80 100 1 2 3 4 5 6 7 8 9 10 11 12
TEMPERATURE (°C) INPUT VOLTAGE VIN (V)

FIGURE 2-2: Supply Current vs. FIGURE 2-5: Voltage Conversion.

Temperature (with Boost Pin = VIN).

100 100
OUTPUT SOURCE RESISTANCE (Ω)
OUTPUT SOURCE RESISTANCE (Ω)

70 80 VIN = 2.5V
50
60
VIN = 5.5V
30
40

IOUT = 20mA 20
TA = 25°C
10 0
1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12 -40 -20 0 20 40 60 80 100
SUPPLY VOLTAGE (V) TEMPERATURE (°C)

FIGURE 2-3: Output Source Resistance FIGURE 2-6: Output Source Resistance
vs. Supply Voltage. vs. Temperature.

 2001-2015 Microchip Technology Inc. DS20001467C-page 5

TC7660S
Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 4-1.

100
0
90
Boost Pin = Open
-2 80
OUTPUT VOLTAGE VOUT (V)

Boost Pin = V+

POWER EFFICIENCY (%)

70
-4 60
50
-6
40
-8 30
20
-10 10
0
-12

4.5

15.0

50.0
3.0

10.0

40.0

60.0
2.0

35.0
1.5

9.0

30.0
1.0

7.5

25.0
6.0

20.0

55.0
0 10 20 30 40 50 60 70 80 90 100
OUTPUT CURRENT (mA)
LOAD CURRENT (mA)
FIGURE 2-7: Output Voltage vs. Output FIGURE 2-10: Power Conversion
Current. Efficiency vs. Load.

200 200
175 175
SUPPLY CURRENT IDD (μA)

150 SUPPLY CURRENT IDD (μA) 150

125 125
100 VIN = 12.5V VIN = 12.5V
100
75 75
50 50
VIN = 5.5V VIN = 5.5V
25 25
0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

FIGURE 2-8: Supply Current vs. FIGURE 2-11: Supply Current vs.
Temperature. Temperature.

200
175
SUPPLY CURRENT IDD (μA)

150
125
100 VIN = 12.5V

75
50
VIN = 5.5V
25
0
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)

FIGURE 2-9: Supply Current vs.

Temperature.

DS20001467C-page 6  2001-2015 Microchip Technology Inc.

 TC7660S
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Pin No. Symbol Description
1 BOOST Switching Frequency boost pin
2 CAP+ Charge pump capacitor positive terminal
3 GND Ground terminal
4 CAP- Charge pump capacitor negative terminal
5 VOUT Output voltage
6 LV Low voltage pin. Connect to GND for V+ < 3.5V
7 OSC Oscillator control input. Bypass with an external capacitor to slow the oscillator.
8 V+ Power supply positive voltage input

3.1 Switching Frequency Boost Pin It is recommended that a low ESR capacitor be used.
(Boost) Additionally, larger values will lower the output ripple.

By connecting the boost pin (pin 1), the switching 3.6 Low Voltage Pin (LV)
frequency of the charge pump is increased from 10 kHz
typical to 45 kHz typical. By connecting the boost pin The low voltage pin ensures proper operation of the
(pin1), to the V+ pin (pin 8), the switching frequency of internal oscillator for input voltages below 3.5V. The low
the charge pump is increased from 10 kHz typical to voltage pin should be connected to ground (GND) for
45 kHz typical. input voltages below 3.5V. Otherwise, the low voltage
pin should be allowed to float.
3.2 Charge Pump Capacitor (CAP+) 3.7 Oscillator Control Input (OSC)
Positive connection for the charge pump capacitor, or The oscillator control input can be utilized to slow down
flying capacitor, used to transfer charge from the input or speed up the operation of the TC7660S. Refer to
source to the output. In the voltage-inverting Section 5.4 “Changing the TC7660S Oscillator
configuration, the charge pump capacitor is charged to Frequency”, for details on altering the oscillator
the input voltage during the first half of the switching frequency.
cycle. During the second half of the switching cycle, the
charge pump capacitor is inverted and charge is 3.8 Power Supply (V+)
transferred to the output capacitor and load.
Positive power supply input voltage connection. It is
It is recommended that a low ESR (equivalent series
recommended that a low ESR capacitor be used to
resistance) capacitor be used. Additionally, larger
bypass the power supply input to ground (GND).
values will lower the output resistance.

3.3 Ground (GND)

Input and output zero volt reference.

3.4 Charge Pump Capacitor (CAP-)

Negative connection for the charge pump capacitor, or
flying capacitor, used to transfer charge from the input
to the output. Proper orientation is imperative when
using a polarized capacitor.

3.5 Output Voltage (VOUT)

Negative connection for the charge pump output
capacitor. In the voltage-inverting configuration, the
charge pump output capacitor supplies the output load
during the first half of the switching cycle. During the
second half of the switching cycle, charge is restored to
the charge pump output capacitor.

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TC7660S
4.0 DETAILED DESCRIPTION S1 S2
V+
4.1 Theory of Operation +
C1
The TC7660S contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF +
GND S C2
polarized electrolytic capacitors. Operation is best S4
3
understood by considering Figure 4-2, which shows an VOUT = -VIN
idealized voltage inverter. Capacitor C1 is charged to a
voltage V+ for the half cycle when switches S1 and S3
are closed. (Note that switches S2 and S4 are open
during this half cycle.) During the second half cycle of
operation, switches S2 and S4 are closed, with S1 and
S3 open, thereby shifting capacitor C1 negatively by V+ FIGURE 4-2: Ideal Charge Pump Inverter.
volts. Charge is then transferred from C1 negatively by To improve low-voltage operation, the “LV” pin should
V+ volts. Charge is then transferred from C1 to C2, such be connected to GND, disabling the regulator. For
that the voltage on C2 is exactly V+ assuming ideal supply voltages greater than 3.5V, the LV terminal must
switches and no load on C2. be left open to ensure latch-up-proof operation and
The four switches in Figure 4-2 are MOS power prevent device damage.
switches; S1 is a P-channel device, and S2, S3 and S4 4.2 Theoretical Power Efficiency
are N-channel devices. The main difficulty with this
approach is that in integrating the switches, the sub-
Considerations
strates of S3 and S4 must always remain In theory, a capacitive charge pump can approach
reverse-biased with respect to their sources, but not so 100% efficiency if certain conditions are met:
much as to degrade their ON resistances. In addition, (1) The drive circuitry consumes minimal power.
at circuit start-up, and under output short circuit condi- (2) The output switches have extremely low ON
tions (VOUT = V+), the output voltage must be sensed resistance and virtually no offset.
and the substrate bias adjusted accordingly. Failure to
(3) The impedances of the pump and reservoir
accomplish this will result in high power losses and
capacitors are negligible at the pump frequency.
probable device latch-up.
The TC7660S approaches these conditions for nega-
This problem is eliminated in the TC7660S by a logic tive voltage multiplication if large values of C1 and C2
network which senses the output voltage (VOUT) are used. Energy is lost only in the transfer of charge
together with the level translators, and switches the between capacitors if a change in voltage occurs. The
substrates of S3 and S4 to the correct level to maintain energy lost is defined by:
necessary reverse bias.
E = 1/2 C1 (V12 – V22)
V1 and V2 are the voltages on C1 during the pump and
V+ IS transfer cycles. If the impedances of C1 and C2 are rel-
1 8 atively high at the pump frequency (refer to Figure 4-2)
2 7 V+ compared to the value of RL, there will be a substantial
IL
C1 + TC7660S (+5V)
3 6 COSC difference in voltages V1 and V2. Therefore, it is desir-
10 µF able not only to make C2 as large as possible to
4 5 RL
eliminate output voltage ripple, but also to employ a
VOUT correspondingly large value for C1 in order to achieve
maximum efficiency of operation.
C2
+ 10 µF
4.3 Dos and Don'ts
• Do not exceed maximum supply voltages.
Note: For large values of COSC (>1000 pF), the • Do not connect the LV terminal to GND for supply
values of C1 and C2 should be increased to voltages greater than 3.5V.
100F.
• Do not short circuit the output to V+ supply for
voltages above 5.5V for extended periods; how-
FIGURE 4-1: TC7660S Test Circuit.
ever, transient conditions including start-up are
The voltage regulator portion of the TC7660S is an okay.
integral part of the anti-latch-up circuitry. Its inherent • When using polarized capacitors in the inverting
voltage drop can, however, degrade operation at low mode, the + terminal of C1 must be connected to
voltages. pin 2 of the TC7660S and the + terminal of C2
must be connected to GND.

DS20001467C-page 8  2001-2015 Microchip Technology Inc.

 TC7660S
5.0 APPLICATIONS INFORMATION The dynamic output impedance of the TC7660S is due,
primarily, to capacitive reactance of the charge transfer
5.1 Simple Negative Voltage capacitor (C1). Since this capacitor is connected to the
Converter output for only half of the cycle, the equation is:

Figure 5-1 shows typical connections to provide a EQUATION

negative supply where a positive supply is available. A
similar scheme may be employed for supply voltages 2
X C = ----------- = 3.18 
anywhere in the operating range of +1.5V to +12V, 2fC 1
keeping in mind that pin 6 (LV) is tied to the supply where:
negative (GND) only for supply voltages below 3.5V. f = 10 kHz and C1 = 10 µF.

V+ 5.2 Paralleling Devices

1 8 Any number of TC7660S voltage converters may be
paralleled to reduce output resistance (Figure 5-2). The
2 7 VOUT*
+ reservoir capacitor, C2, serves all devices, while each
C1 TC7660S C2
10 µF 3 6 device requires its own pump capacitor, C1. The resul-
+ 10 µF
4 5 tant output resistance would be approximately:
EQUATION
* VOUT = -V+ for 1.5V  V+  12V
R OUT  of TC7660S 
ROUT = ---------------------------------------------------
FIGURE 5-1: Simple Negative Converter. n  number of devices 
The output characteristics of the circuit in Figure 5-1
are those of a nearly ideal voltage source in series with
a 70resistor. Thus, for a load current of -10 mA and
a supply voltage of +5V, the output voltage would be
-4.3V.

V+
1 8
2 7 1 8
+ TC7660S
C1 3 6 2 7 RL
+ TC7660S
4 “1” 5 C1 3 6
4 “n” 5

C2
+

FIGURE 5-2: Paralleling Devices Lowers Output Impedance.

V+
1 8
2 7 1 8
+ TC7660S
10 µF 3 6 2 7
+ TC7660S
4 “1” 5 10 µF 3 6
4 “n” 5 VOUT *
10 µF
+
10 µF
+
* VOUT = -n V+ for 1.5V  V+  12V
FIGURE 5-3: Increased Output Voltage By Cascading Devices.

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TC7660S
5.3 Cascading Devices
The TC7660S may be cascaded as shown (Figure 5-3)
to produce larger negative multiplication of the initial 1 8 V+
supply voltage. However, due to the finite efficiency of 2 7
each device, the practical limit is 10 devices for light + TC7660S
loads. The output voltage is defined by: C1 3 6 COSC

EQUATION 4 5 VOUT
+ C2
VOUT = – n  V  +

where n is an integer representing the number of

devices cascaded. The resulting output resistance
would be approximately the weighted sum of the FIGURE 5-5: Lowering Oscillator
individual TC7660S ROUT values. Frequency.
5.4 Changing the TC7660S Oscillator
5.5 Positive Voltage Multiplication
Frequency
It may be desirable in some applications (due to noise The TC7660S may be employed to achieve positive
or other considerations) to increase the oscillator fre- voltage multiplication using the circuit shown in
quency. Pin 1, frequency boost pin, may be connected Figure 5-6. In this application, the pump inverter
to V+ to increase oscillator frequency to 45 kHz from a switches of the TC7660S are used to charge C1 to a
nominal of 10 kHz for an input supply voltage of 5.0V. voltage level of V+–VF (where V+ is the supply voltage
The oscillator may also be synchronized to an external and VF is the forward voltage drop of diode D1). On the
clock as shown in Figure 5-4. In order to prevent possi- transfer cycle, the voltage on C1 plus the supply voltage
ble device latch-up, a 1 kΩ resistor must be used in (V+) is applied through diode D2 to capacitor C2. The
series with the clock output. In a situation where the voltage thus created on C2 becomes (2V+) – (2VF), or
designer has generated the external clock frequency twice the supply voltage minus the combined forward
using TTL logic, the addition of a 10 kΩ pull-up resistor voltage drops of diodes D1 and D2.
to V+ supply is required. Note that the pump frequency The source impedance of the output (VOUT) will depend
with external clocking, as with internal clocking, will be on the output current, but for V+ = 5V and an output
half of the clock frequency. Output transitions occur on current of 10 mA, it will be approximately 60Ω.
the positive-going edge of the clock.

V+ V+
V+
1 8 1 8
1 k CMOS
2 7 GATE 2 7 VOUT =
+ D1
10 µF 3
TC7660S
6
TC7660S D2 (2 V+) - (2 VF)
3 6
4 “1” 5 VOUT 4 5 + +
C1 C2
10 µF
+
FIGURE 5-6: Positive Voltage Multiplier.
FIGURE 5-4: External Clocking.
It is also possible to increase the conversion efficiency
of the TC7660S at low load levels by lowering the
oscillator frequency. This reduces the switching losses,
and is achieved by connecting an additional capacitor,
COSC, as shown in Figure 5-5. Lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C1) and the reservoir (C2)
capacitors. To overcome this, increase the values of C1
and C2 by the same factor that the frequency has been
reduced. For example, the addition of a 100 pF
capacitor between pin 7 (OSC) and pin 8 (V+) will lower
the oscillator frequency to 1 kHz from its nominal
frequency of 10 kHz (a multiple of 10), and necessitate
a corresponding increase in the values of C1 and C2
(from 10 µF to 100 µF).

DS20001467C-page 10  2001-2015 Microchip Technology Inc.

 TC7660S
5.6 Combined Negative Voltage
Conversion and Positive Supply VOUT = -V -

Multiplication
1 8
+
Figure 5-7 combines the functions shown in Figure 5-3 2 7 10 µF
C1 + 1 M
and Figure 5-6 to provide negative voltage conversion TC7660S
and positive voltage multiplication simultaneously. For 10 µF 3 6
example, this approach would be suitable for generat- 4 5
ing +9V and -5V from an existing +5V supply. In this
instance, capacitors C1 and C3 perform the pump and V - input
reservoir functions, respectively, for the generation of
the negative voltage, while capacitors C2 and C4 are FIGURE 5-8: Positive Voltage
pump and reservoir, respectively, for the multiplied pos- Conversion.
itive voltage. There is a penalty in this configuration
which combines both functions, however, in that the 5.8 Voltage Splitting
source impedances of the generated supplies will be
The same bidirectional characteristics used in
somewhat higher due to the finite impedance of the
Figure 5-8 can also be used to split a higher supply in
common charge pump driver at pin 2 of the device.
half, as shown in Figure 5-9. The combined load will be
evenly shared between the two sides. Once again, a
V+ high value resistor to the LV pin ensures start-up.
VOUT Because the switches share the load in parallel, the
1 8 output impedance is much lower than in the standard
= -V+
2 7 C3 circuits, and higher currents can be drawn from the
+
TC7660S D1 device. By using this circuit, and then the circuit of
3 6
Figure 5-3, +15V can be converted (via +7.5V and -7.5V)
4 5 VOUT = to a nominal -15V, though with rather high series
+ D2 (2 V+) - (2 VF)
C1 resistance (~250Ω).
+
C2 +
C4 V
+

+
R 50μF
L1 1 8
FIGURE 5-7: Combined Negative
50μF 2 7
Converter and Positive Multiplier. V
OUT
+
=
– +
100 kΩ 1 MΩ
V –V 3 TC7660S 6
2 –

5.7 Efficient Positive Voltage R

4 5
L2
Multiplication/Conversion
+
Since the switches that allow the charge pumping 50μF
–
operation are bidirectional, the charge transfer can be V
–

performed backwards as easily as forwards.

Figure 5-8 shows a TC7660S transforming -5V to +5V
(or +5V to +10V, etc.). The only problem is that the FIGURE 5-9: Splitting a Supply in Half.
internal clock and switch-drive section will not operate
until some positive voltage has been generated. An ini- 5.9 Negative Voltage Generation for
tial inefficient pump, as shown in Figure 5-7, could be
Display ADCs
used to start this circuit up, after which it will bypass the
other (D1 and D2 in Figure 5-7 would never turn on), or The TC7106 is designed to work from a 9V battery.
else the diode and resistor shown dotted in Figure 5-8 With a fixed power supply system, the TC7106 will
can be used to “force” the internal regulator on. perform conversions with input signal referenced to
power supply ground.

5.10 Negative Supply Generation for

4½ Digit Data Acquisition System
The TC7135 is a 4½ digit ADC operating from ±5V
supplies. The TC7660S provides an inexpensive -5V
source. (See AN16 and AN17 for TC7135 interface
details and software routines.)

 2001-2015 Microchip Technology Inc. DS20001467C-page 11

TC7660S
6.0 PACKAGING INFORMATION
6.1 Package Marking Information

8-Lead PDIP (300 mil) Example Example

XXXXXXXX TC7660S TC7660S

XXXXXNNN CPA e3 256 EPA e3256
YYWW 1545 1545

8-Lead SOIC (3.90 mm) Example

TC7660SE
OA e3 1545
NNN 256

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.

DS20001467C-page 12  2001-2015 Microchip Technology Inc.

 TC7660S

/HDG3ODVWLF'XDO,Q/LQH 3$ PLO%RG\>3',3@

1RWH For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A
N B

E1

NOTE 1
1 2
TOP VIEW

C A A2

3/$1(
L c
A1

e eB
8X b1
8X b
.010 C

SIDE VIEW END VIEW

Microchip Technology Drawing No. C04-018D Sheet 1 of 2

 2001-2015 Microchip Technology Inc. DS20001467C-page 13

TC7660S

/HDG3ODVWLF'XDO,Q/LQH 3$ PLO%RG\>3',3@

1RWH For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)

DATUM A DATUM A

b b
e e
2 2

e e

Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing No. C04-018D Sheet 2 of 2

DS20001467C-page 14  2001-2015 Microchip Technology Inc.

 TC7660S

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2001-2015 Microchip Technology Inc. DS20001467C-page 15

TC7660S

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20001467C-page 16  2001-2015 Microchip Technology Inc.

 TC7660S

     !"#$%&

 '   ! "#  $% &"' ""    ($ )  %
 *++&&&!    !+ $

 2001-2015 Microchip Technology Inc. DS20001467C-page 17

TC7660S
NOTES:

DS20001467C-page 18  2001-2015 Microchip Technology Inc.

 TC7660S
APPENDIX A: REVISION HISTORY

Revision C (November 2015)

The following is the list of modifications.
1. Updated Section 1.0 “Electrical Characteris-
tics”.
2. Added Temperature Specifications table.
3. Updated Product Identification System
section.
4. Minor typographical errors.

Revision B (August 2013)

The following is the list of modifications.
1. Added Appendix A and the “Product Identifi-
cation System” page.
2. Updated Section 6.0 “Packaging
Information”.

Revision A (May 2001)

• Original release of this document.

 2001-2015 Microchip Technology Inc. DS20001467C-page 19

TC7660S
NOTES:

DS20001467C-page 20  2001-2015 Microchip Technology Inc.

 TC7660S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX [X](1) Examples:

a) TC7660SCPA: Commercial temperature,
Device Temperature Package Tape and Reel PDIP package
Range Option a) TC7660SCPA: Commercial temperature,
PDIP package
a) TC7660SEPA: Extended temperature, PDIP
Device: TC7660S: DC-to-DC Voltage Converter package
b) TC7660SCOA: Commercial temperature,
SOIC package
Temperature C = 0°C to +70°C (Commercial) c) TC7660SCOA713: Tape and Reel,
Range: E = -40°C to +85°C (Extended) Commercial temperature, SOIC package
V = -40°C to +125°C (Various)
d) TC7660SEOA: Extended temperature, SOIC
package
Package: PA = 8-Lead Plastic Dual In-Line - 300 mil Body (PDIP) e) TC7660SEOA713: Tape and Reel, Extended
OA = 8-Lead Plastic Small Outline - Narrow, 3.90 mm Body (SOIC) temperature, SOIC package
f) TC7660SEOA723: Reverse Tape and Reel,
Tape and Blank = Tube
Extended temperature, SOIC package
Reel 713 = Tape and Reel (SOIC only)
723 = Reverse Tape and Reel (SOIC only)
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and
Reel option.

 2001-2015 Microchip Technology Inc. DS20001467C-page 21

TC7660S
NOTES:

DS20001467C-page 22  2001-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
conveyed, implicitly or otherwise, under any Microchip Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
intellectual property rights unless otherwise stated. Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2001-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0013-4

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2001-2015 Microchip Technology Inc. DS20001467C-page 23

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office China - Xiamen Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 86-592-2388138 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 Tower 6, The Gateway Fax: 86-592-2388130 Fax: 43-7242-2244-393
Tel: 480-792-7200 Harbour City, Kowloon China - Zhuhai Denmark - Copenhagen
Fax: 480-792-7277 Hong Kong Tel: 86-756-3210040 Tel: 45-4450-2828
Technical Support: Tel: 852-2943-5100 Fax: 86-756-3210049 Fax: 45-4485-2829
http://www.microchip.com/ Fax: 852-2401-3431 India - Bangalore France - Paris
support
Australia - Sydney Tel: 91-80-3090-4444 Tel: 33-1-69-53-63-20
Web Address:
Tel: 61-2-9868-6733 Fax: 91-80-3090-4123 Fax: 33-1-69-30-90-79
www.microchip.com
Fax: 61-2-9868-6755 India - New Delhi Germany - Dusseldorf
Atlanta Tel: 91-11-4160-8631 Tel: 49-2129-3766400
China - Beijing
Duluth, GA
Tel: 86-10-8569-7000 Fax: 91-11-4160-8632 Germany - Karlsruhe
Tel: 678-957-9614
Fax: 86-10-8528-2104 India - Pune Tel: 49-721-625370
Fax: 678-957-1455
China - Chengdu Tel: 91-20-3019-1500 Germany - Munich
Austin, TX Tel: 86-28-8665-5511
Tel: 512-257-3370 Japan - Osaka Tel: 49-89-627-144-0
Fax: 86-28-8665-7889 Tel: 81-6-6152-7160 Fax: 49-89-627-144-44
Boston Fax: 81-6-6152-9310
China - Chongqing Italy - Milan
Westborough, MA
Tel: 86-23-8980-9588 Japan - Tokyo Tel: 39-0331-742611
Tel: 774-760-0087
Fax: 86-23-8980-9500 Tel: 81-3-6880- 3770 Fax: 39-0331-466781
Fax: 774-760-0088
China - Dongguan Fax: 81-3-6880-3771 Italy - Venice
Chicago Tel: 86-769-8702-9880 Korea - Daegu Tel: 39-049-7625286
Itasca, IL
Tel: 630-285-0071 China - Hangzhou Tel: 82-53-744-4301 Netherlands - Drunen
Fax: 630-285-0075 Tel: 86-571-8792-8115 Fax: 82-53-744-4302 Tel: 31-416-690399
Fax: 86-571-8792-8116 Korea - Seoul Fax: 31-416-690340
Cleveland
China - Hong Kong SAR Tel: 82-2-554-7200
Independence, OH Poland - Warsaw
Tel: 216-447-0464 Tel: 852-2943-5100 Fax: 82-2-558-5932 or Tel: 48-22-3325737
Fax: 216-447-0643 Fax: 852-2401-3431 82-2-558-5934
Spain - Madrid
Dallas
China - Nanjing Malaysia - Kuala Lumpur Tel: 34-91-708-08-90
Tel: 86-25-8473-2460 Tel: 60-3-6201-9857 Fax: 34-91-708-08-91
Addison, TX
Tel: 972-818-7423 Fax: 86-25-8473-2470 Fax: 60-3-6201-9859
Sweden - Stockholm
Fax: 972-818-2924 China - Qingdao Malaysia - Penang Tel: 46-8-5090-4654
Tel: 86-532-8502-7355 Tel: 60-4-227-8870
Detroit UK - Wokingham
Fax: 86-532-8502-7205 Fax: 60-4-227-4068
Novi, MI Tel: 44-118-921-5800
Tel: 248-848-4000 China - Shanghai Philippines - Manila Fax: 44-118-921-5820
Tel: 86-21-5407-5533 Tel: 63-2-634-9065
Houston, TX
Tel: 281-894-5983 Fax: 86-21-5407-5066 Fax: 63-2-634-9069
China - Shenyang Singapore
Indianapolis
Tel: 86-24-2334-2829 Tel: 65-6334-8870
Noblesville, IN
Tel: 317-773-8323 Fax: 86-24-2334-2393 Fax: 65-6334-8850
Fax: 317-773-5453 China - Shenzhen Taiwan - Hsin Chu
Tel: 86-755-8864-2200 Tel: 886-3-5778-366
Los Angeles
Fax: 86-755-8203-1760 Fax: 886-3-5770-955
Mission Viejo, CA
Tel: 949-462-9523 China - Wuhan Taiwan - Kaohsiung
Fax: 949-462-9608 Tel: 86-27-5980-5300 Tel: 886-7-213-7828
Fax: 86-27-5980-5118 Taiwan - Taipei
New York, NY
Tel: 631-435-6000 China - Xian Tel: 886-2-2508-8600
Tel: 86-29-8833-7252 Fax: 886-2-2508-0102
San Jose, CA
Tel: 408-735-9110 Fax: 86-29-8833-7256 Thailand - Bangkok
Tel: 66-2-694-1351
Canada - Toronto
Tel: 905-673-0699 Fax: 66-2-694-1350
Fax: 905-673-6509
07/14/15

DS20001467C-page 24  2001-2015 Microchip Technology Inc.