'[This question paper contains 8 printed pages.

]
1039 8

content of memory at different addresses is as

.
Your Roll No...............
shown in the figure above. PC is a Program t
counter register with value 600, Rl is a general- Sr. No. of Question Paper: 1039 D
purpose register with value 904, XR is an
Index register with value 200. BR is the Base 23420tt102
Unique Paper Code
register with contenl 160. Determine the effective
address and the content of AC register after the
operation is performed for the following addressing Name of the Paper Computer System Architecture
modes:
Name of the Course B.Sc. (H) COMPUTER
(i) Direct Addressing SCIENCE (NEP.UGCF.
(ii) Indirect Addressing 2022)
(iii) Relative
I Semester I
(iv) Indexed
(v) Register Indirect I Duration : 3 Hours Maximum Marks : 90
(vi) Base Register addressing. (6)
Instructions for Cgnrlirlallcs

7 (a) What is cache memory? How is it different from Write your Roll No. on the top immediately on receipt
auxiliary memory? (4)
of this question paper.
(b) Given the Boolean function:
2, Question No. I is compulsory.
F(A, B, C) = A'B'C + AB'C' + A'BC + ABC'
3. Attempt any 4 questions from Question 2 to Question
(i) List the truth table of the function. 7.

(ii) Simplify the algebraic expression. 4. Parts of a question must be answered together.

(iii) Draw the logic diagram of thesimplified

expression using NAND gates only.
(5) (a) Give the Boolean expression for the following logic
diagram.
(c) Explain programmed I/O with the help of a
flowchart. How is it different from Interrupt driven (3)
UO? (6)
(s00) P,T.O,
r 039 2 1039 7

Determine the 8-bit values in each register after

the execution of the following micro-operat ions in
sequential manner:
T, :R,+-R,nR.
B X r, , nl - ({, " n])" no (s)
(c) Consider the fragment of memory as shown below :

Addr63 Mairory

600 ADD ro AC PC - 600

(b) State DeMorgan's law and prove it using truth @l I Addnri - 84o
table. (3) @2 Naxt Rl - 9Gl

(c) Name the register: XR -20o

440 850
1
(i) Instruction from memory will be transferred AC- lr0
to this register. ;;; 840

BR- 160
(ii) The address part of the memory-reference 903 toJ2
instruction is transferred to this register.
904 I
(iii) This register contains the address of next
instruction that will be executed. (3) 1000
l- toC6-
(d) What is a register-reference instruction? Give any 1040 l220
two examples. Name the addressing mode used
by these instructions? (3) 1442 lro

(e) Perform the arithmetic operation (-5) + (-6) in

binary using 2's complement and 4-bit register.
Show if there is any overflow. (3) Assume that all the addresses and register /
memory contents are in decimal. A two-word
(0 (i) Find 8's complement of (542)r. instruction is stored at an address 600 with address
part stored at address 601 . The first word consists
(ii) Subtract (0100 l01l)2 from (01l0 0110), of a 'mode bit' and the op-code for ADD to AC
(3) machine instruction, whereas second word of the
instruction contains the value 840. Further, the
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1039 6 1039 3

would it take to execute an instruction over 100 (g) Write the microinstructions for fetch and decode
pairs of data in the pipeline? What will be the phase of the instruction cycle along with control
speedup ratio if the time taken to execute same signals. (4)
instruction in a non-pipelined system is 300 ns.
(6) (h) Briefly explain the working of encoder? How is it
different from decoder? (4)
5. (a) List any four characteristics of GPU. (4)
(i) Explain control command, status command, data
(b) What is DMA? How cycle stealing is different input command, data output command in relation
from burst transfer. (5) to I/O communication. (4)

(c) Draw the diagram of a 4-bit binary adder-

subtractor. Explain its working with the help of an 1
2 (a) Draw the logic diagram ofa 8-to-1 line multiplexer.
example. (6) Explain its working with the help of function
table. (4)

6 (a) Specify the fourteen-bit control word for the basic (b) Simplify the following Boolean function F, together
computer that must be applied to the processor to with the don't-care condition d in SOP form and
implement the following micro-operation, given the draw the logic diagram for the simplified F.
operation code for the operations are as follows: F(A, B, C, D) = t(4, s,7,12, 13,14)
(i) Ru <- shr R, d(A, B, C, D) = :(1,9, 11, rs) (s)

(ii) R, +- Rr + Rr (c) An instruction at address 021 in the basic

computer has l=0, an operation code specifying
Operation OPCODE the AND operation, and an address part equal to
ADD 00010 (4) 083 (all numbers are in hexadecimal). The memory
SIIR 10000 word at address 083 contains the operand B8F2
and the content of AC is 4937. Go over the
instruction cycle and determine the contents of
(b) Assume that the following 8-bit registers R,, R,, the following registers: PC, AR, DR, AC and IR
R, and Ro, initially have the following unsigned at the end of each timing signal starting from Tn
values: to the end of execule cycle. (6)

Rr=llll 0011, Rr=1110 0011, R3=0011 1010,

R4=1010 l0l0

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3. (a) Perform the following conversions: (i) The following control inputs are active in
the given bus system
(i) Convert the decimal number 245.25 to
hexadecimal. For each case, specify the register transfer
that will be executed during the next clock
(ii) Convert (101101.11), to decimal. (4) transition.

(b) How many 2-to-4-line decoders will be used to S.No. Sr Sr So LD ofregister Memory Adder
construct a 4-to-16-line decoder? Give the block a. I 1 I TR Read
diagram of the same. (5) b. 0 I 0 AR
c. 1 0 0 DR Write
Add
(c) Consider the bus system shown below : (6) d. 0 0 0 AC

(ii) Write the microinstruction to set the flip-

fL flop R to 1 including the control conditions.

4 (a) Write the excitation tables for the JK flip flop.

How can you derive D flip-flop from a JK flip-
flop? Show with the help of a block diagram.
(4)
(b) The memory unit of a computer has 256K words
of 32 bits each. The computer has an instruction
format with four fields: an operation code field, a
mode field to specify one of seven addressing
modes, a register field to specify one of the 56
processor registers, and a memory address
Specify the instruction format and the number of
bits in each field if the instruction is in one memory
word. (5)

(c) Assuming the time delay of the four segments in

a pipeline are as follows:
t, = 50 ns, t, = 30 ns, t., = 95 ns, to = 45 ns. The
ihterface relisters delay time t,=5 ns. How long
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