Papper 1
Part a
Q.1 What is meant by RISC?
Q.2 What do you mean by ALU?
Q.3 What is a control memory?
Q.4 What is an instruction cycle?
Q.5 Define a bus.
Q.6 What is a micro-operation?
Q.7 What do you mean by multicomputer ?
Q.8 What is parallel processing?
Q.9 What is a register?
Q.10 What is auxiliary memory?
Part b
Q.1 Design a 4×3 RAM.
Q.2 Explain set-associative mapping with a suitable example.
Q.3 Design a 4×3 ROM for a table of contents of your choice.
Q.4. Write 4 logic micro-operations.
Q.5 Explain memory hierarchy.
Q.6 Explain serial communication with an example.
Q.7 Explain arithmetic pipeline with an example.
Part c
Q. 1 Explain DMA with suitable example.
Q.2 Show the steps of Booth's algorithm for 8*(-8).
Q.3 Describe Flynn's taxonomy.
Q.4 Explain the design of a vector processor.
Q.5 Explain cache coherence with a suitable example.
Papper 2
Part a
Q. 1. Describe the purpose of the buffer gate in the clock input of
a register.
Q. 2. Differentiate computer organization and computer
architecture.
Q. 3. Describe the purpose of buffer gate.
Q. 4. Differentiate instruction code and operation code.
Q. 5. Differentiate memory reference and register reference
computer instructions.
Q. 6. What is the difference between a direct and an indirect
address instruction ?
Q. 7. What are the two instructions needed in the basic computer
in order to set the
flip-flop to 1 ?
Q. 8. Differentiate between assembly language and machine
language.
Q. 9. Show how the MRI and non-MRI tables can be stored in
memory.
Q. 10. Explain the difference between hardwired control and
microprogrammed control.
Part b
Q. I, Draw the block diagram of a dual 4-to-1-line multiplexers and
explain its operation by means of a function table.
Q. 2. Represent the following conditional control statement by
two register transfer
statements with control functions.If (P = I) then (RI + R2) else If
(Q= 1) then (RI + R3)
Q. 3. Draw a timing diagram assuming that SC is cleared to 0 at
time T3 if control signal is active. C 7 T 3 : SC ->0 C 7 is activated
with the positive clock transition associated with T7 .
Q. 4. An output program resides in memory starting from address
230. It is executed after the computer recognizes an interrupt
when FGO becomes a 1 (while IEN = 1).
(a) What instruction must be placed at address 1 ??
(b) What must be the last two instructions of the output
program""
Q. 5. The memory unit of a computer has 256K words of 32 bits
each. The computer has an instruction format with four fields: an
operation code field, a mode field to specify one of seven
addressing modes, a register address field to specify one of 60
processor registers. and a memory address. Specify the
instruction format and the number of bits in each field if the in
instruction is in one memory word.
Q. 6. How many times does the control unit refer to memory when
it fetches and executes an indirect addressing mode instruction if
the instruction is (a) a computational type requiring an operand
from memory: (b) a branch type. Explain with the help of an
example.
Q. 7. Write the RISC I instruction in assembly language that will
cause a jump to address 3200 if the Z (zero) status bit is equal to
1.
(a) Using immediate mode
(b) Using a relative address mode (assume that PC = 3400)
Part C
Q.1. An instruction at address 021 in the basic computer has I =
0. an operation code of the AND instruction. and an address part
equal to 083 (all numbers are in hexadecimal). The memory word
at address 083 contains the operand B8F2 and the content of AC
is A937. Go over the instruction cycle and determine the contents
of the following registers at the end of the execute phase: PC. AR.
DR. AC. and IR. Repeat the problem three more times starting
with an operation code of another memory-reference instruction.
Q.2. Write a program to evaluate the arithmetic statement :
X=A-B+C*(D*E-F) / G+H*K
(a) Using a general register computer with three address
instructions.
(b) Using a general register computer with two address
instructions.
(c) Using an accumulator type computer with one address
instructions.
(d) Using a stack organized computer with zero-address operation
instructions.
Q. 3. Give an example of a RISC I instructions that will perform
the following operations :
(a) Decrement a register
(b) Complement a register
(c) Negate a register
(d) Clear a register to 0
(e) Divide a signed number by 4
(f) No operation.
Q. 4. Formulate a six-segment instruction pipeline for a computer.
Specify the operations to be performed in each segment.
Q. 5. How many characters per second can be transmitted over a
1200-baud line in each of the following modes? (Assume a
character code of eight bits.)
(a) Synchronous serial transmission.
(b) Asynchronous serial transmission with two stop bits.
(c) Asynchronous serial transmission with one stop bit.
PAPPER 3
PART A
1. What do you mean by computer performance?
2. If the memory is represented in 12 bits > 16 bits then how
many words can be accommodated in the memory?
3. Describe subroutine?
4. What do you mean by Hit Ratio in cache memory?
5. Write a quick note on Interrupt intiated input - output?
6. Discuss on concept of parallel processing?
7. Explain the concept of microprogrammed control unit?
8. Convert +1001.11 in 8 bit fraction and 6 bit exponent as per
floating point representation.
9. Describe the three fields (Mode, Opcode and Address field)
of 16 bit instruction format.
10. Perform selective component over A = 1011 0110 and B
=0110 1110.
PART B
1. Draw the flow diagram for the hardware that implements
the following statements - X + yz : AR +- AR + BR Where AR
and BR are two n - bit registers and x y and z are control
variable. Include the logic gates for the control function.
(Remember that the symbol '+' designates an OR operation
in a control or Boolean function but that it represents and
arithmetic plus in a micro-operation.
2. What is priority interrupt? Explain Daisy chaining Priority
Interrupt's polling logic using its block diagram and logical
diagram both.
3. A non - pipeline system takes 100 ns to process a task. The
same task can be
processed in a six - segment pipeline with a clock cycle of 20
ns. Determine the speed - up ratio of pipeline for 200 tasks.
What is maximum speed - up that can be achieved?
4. Explain the functional units of an architecture of computer
with diagram?
5. Explain the types of instructions?
6. Differentiate between Hardwired and Micro - programmed
control unit?
7. Explain significance of data register, address register,
instruction register, temporary register, program counter
and accumulator in common bus system.
PART C
1. Perform Multiplication of - 13 and +9 using Booth
Algorithm. With the help of diagram. Explain line coding
schemes.
2. A digital computer has a common bus system for 8
registers and 16 bits each. The bus is constructed with
multiplexers.
a. How many selection inputs are there in each
multiplexer?
b. How many multiplexers are there in the bus?
c.What size of multiplexers is needed?
d. Draw the diagram of the mentioned problem
definition.
3. Explain the need of cache memory. What is Hit Ratio?
Elaborate over the three types of mapping under cache
memory with neat diagram.
4. Why pipeline is useful in processing? Explain instruction
pipeline including the processing steps used in pipeline.
Explain speedup, efficiency and through put in pipelining.
Prove that ratio of non pipeline based architecture and
pipeline based architecture depends upon the no. of
segments (k).
5. a. How many 128×8 RAM chips are needed to provide a
memory capacity of 2048 bytes?
b. How many lines of address bus must be used to access
2048 bytes of memory? How many of These lines will be
common to all chips?
c. How many lines must be decoded for chip select?
d. Specify the size of the decoders?
