Table of content

S. No. List of Content Page No.

1 Vision & Mission of Institute 1
2 Vision & Mission of Department 2
3 Program educational Objectives 3
4 Program Outcomes 4-5
5 Course Outcomes with Bloom Taxonomy 6
6 Program Specific Outcomes 7
7 Course Scheme as per university 8
8 Course Syllabus as per university 9
9 Mapping of Cos- Pos & PSOs 10
10 Rubrics used for Continuous Evaluation for lab sessions. 11
11 Experiment List (1 ……… n) (all programs as per university list mapped with 12-46
COs & PSOs)
Each experiment contains followings.
a) Objective of the Experiment
b) Theory & Circuit Diagram
c) Output (Snapshot)
12 Course Beyond syllabus (at least 2 experiments mapped with COs & PSOs) 47-54
Each experiment contains followings.
a) Objective of the Experiment
b) Theory & Circuit Diagram
c) Output (Snapshot)
 Institute Vision & Mission

VISION

● To be an institute of repute, providing professionally competent and socially sensitive

engineers.

MISSION

● To equip with the latest technologies to be globally competitive professionals.

● To inculcate qualities of leadership, professionalism, corporate understanding and

executive competence.

● To imbibe and enhance human values, ethics and morals in our students.

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 DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

VISION OF THE DEPARTMENT

To build strong teaching environment that responds the need of industry and challenges of society.

MISSION OF THE DEPARTMENT

Developing strong mathematical & computing skill set among the students.

M2: Extending the role of computer science and engineering in diverse areas like Internet of things (IoT),
Artificial intelligence & Machine Learning and Data Analytics.

M3: Imbibing the students with a deep understanding of professional ethics and high integrity to serve the
Nation.

M4: Providing an environment to the students for their growth both as individuals and as globally
competent Computer Science professional and encouragement for innovation & start-up culture.

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 PROGRAM EDUCATIONAL OUTCOMES (PEOs)

PEO1: Graduates will work in the area of application software development, artificial intelligence &
Machine learning, data analytics, and Internet of things.

PEO2: Graduates will become successful software professional with leadership and managerial quality
in the modern software industry based on their strong skill on theoretical and practical foundation.

PEO3: Graduates will exhibit professional ethics and moral value with capability of working as an
individual and as a team to contribute towards the needs of the industry and society.

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 PROGRAMME OUTCOMES (POs)

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and

design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, healthy, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.

7. Environment and sustainability: Understand the impact of professional engineering solutions

in societal and environmental contexts and demonstrate the knowledge of and need for sustainable
development.

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8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.

9. Individual and teamwork: Function effectively as an individual, and as a member or leader in

diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

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 Computer Organization and Architecture Lab (BCS-352)

Bloom’s Level
COURSE OUTCOMES
COs
Implement circuits (e.g., HALF ADDER, 4x1 MULTIPLEXER) K3
BCS-352.1 using logic gates in simulators

Analyse and evaluate the functionality of implemented circuits for K4

BCS-352.2 various operations

Design and develop complex systems (e.g., DECODER, ALU) for K4

BCS-352.3 specific functionalities

Executing the correctness and reliability of digital systems through K3

BCS-352.4 simulation

Apply control and design principles to create functional computer K3

BCS-352.5 architectures

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 PROGRAM SPECIFIC OUTCOMES (PSOS)

PSO.1: Student will be able to use problem solving skills to develop efficient algorithmic solutions.

PSO.2: Student will be able to develop solution for a given problem in the area of artificial intelligence,
data analytics, computer vision and IOT through conducive environment and infrastructure.

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 Course Scheme

End
Evaluation Scheme Semester
S.No L-T-P
Subject Subject C T
Code Name T A Total(CT+TA) ESE Total Credit

Computer
BCS- Organizatio
1 n and 0 0 2 0 50 50 50 100 1
352
Architecture
lab

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 Course Syllabus
1. Implementing HALF ADDER, FULL ADDER using basic logic gates
2. Implementing Binary -to -Gray, Gray -to -Binary code conversions.
3. Implementing 3-8 line DECODER.
4. Implementing 4x1 and 8x1 MULTIPLEXERS.
5. Verify the excitation tables of various FLIP-FLOPS.
6. Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.
7. Design of an 8-bit ARITHMETIC LOGIC UNIT.
8. Design the data path of a computer from its register transfer language description.
9. Design the control unit of a computer using either hardwiring or microprogramming based on its
register transfer language description.
10. Implement a simple instruction set computer with a control unit and a data path.

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 Mapping of Program Outcomes with Course Outcomes (COs)

CO-PO Matrix
Course
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Outcomes

BCS-352.1 3 - - - 3 - - - - - - 2

BCS-352.2 - 2 - - 3 - - - - - - 2

BCS-352.3 2 2 2 - 3 - - - - - - 3

BCS-352.4 3 2 - 3 3 - - - - - - 3

BCS-352.5 3 2 3 3 3 - - - - - - 2

CO-PSO Matrix

POs PSO1 PSO2

BCS-352.1 3 2

BCS-352.2 3 2

BCS-352.3 3 2

BCS-352.4 3 2

BCS-352.5 3 2

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 Grade Policy for Laboratory

We give the grades to the students i.e. A/α, B/β, C/γ for their performance in lab as per the given table:

Performance Record Viva-Voce

Attention Time line Experimental Knowledge

Effectiveness Presentation Expression

Discipline Quality of Content Communication

Dedication Competence Confidence

The grades α, β, γ/ A, B, C are awarded in lab record, lab performance and viva voce as per the above
define table.

Grade Range of marks

A/α 4-5 Marks

B/β 3-4 Marks

C/γ 2-3 marks

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 List of Experiments

S. No. List of Experiments as per AKTU recommendation CO Blooms

level

1. Implementing HALF ADDER, FULL ADDER using BCS352.1 K3

basic logic gates by simulator
2. Implementing Binary -to -Gray, Gray -to -Binary code BCS352.2 K3
conversions
3. BCS352.3 K3
Implementing 3–8-line DECODER

4. BCS352.3 K3
Implementing 4x1 and 8x1 MULTIPLEXERS

5. BCS352.1 K3
Verify the excitation tables of various FLIP-FLOPS

6. Design of an 8-bit Input/ Output system with four 8-bit BCS352.1, BCS352.4 K4
Internal Registers
7. BCS352.4 K4
Design of an 8-bit ARITHMETIC LOGIC UNIT

8. Design the data path of a computer from its register BCS352.1 K4

transfer language description.
Design the control unit of a computer using either BCS352.5 K4
9. hardwiring or microprogramming based on its register
transfer language description.
10. Implement a simple instruction set computer with a BCS352.5 K3
control unit and a data path.

Course Beyond Syllabus

S. CO Blooms
List of Experiments
No. Level

1. Design and Implement basic Logic Gates BCS352.1, BCS352.3 K4

2. Design and implementation of Carry Look ahead Adders. BCS352.1, BCS352.3 K4

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 Experiment No.:1

Objective: -Implementing HALF ADDER, FULL ADDER using basic logic gates.

Theory:
Binary adder is one of the basic combinational logic circuits. The outputs of a combinational logic circuit
depend on the present input only. In other words, outputs of combinational logic circuit do not depend
upon any previously applied inputs. It does not require any memory like component. Binary adder is one
of the basic combinational logic circuits as present state of input variables.

Procedure:
Half Adder
Before designing a binary adder, let us know some basic rules of binary addition. The most basic binary
addition is the addition of two single bit binary numbers that is addition of two binary digits.
The binary digits are 0 and 1. Hence, there must be four possible combinations of binary addition.

of two binary bits in the above list, first three binary operations result in one bit but fourth one result in
two bits. In one-bit binary addition, if augend and addend are 1, the sum will have two digits. The higher
significant bit (HSB) or Left side bit is called carry and the list significant bit (LSB) or right-side bit of
the result is called sum bit. The logical circuit performs this one-bit binary addition is called half
adder.

Design of Half Adder

For designing a half adder logic circuit, we first have to draw the truth table for two input variables i.e.,
the augend and addend bits, two outputs variables carry and sum bits.
In first three binary additions, there is no carry hence the carry in these cases are considered as 0.

Table 1.1 : Truth Table for Half Adder

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K-map for Half Adder

Now from this truth table we can draw K-map for carries and sums separately.

Figure 1.1: K-map representation for carry and sum (Half Adder)

For above K-maps we get,

Hence the logical design of Half Adder would be

Figure 1.2: Logic diagram for half Adder

Although from truth table it is clearly seen that carry (C) column signifies AND operation and sum (S)
column signifies XOR operation between input variables but till we went through K-map as it is general
practice to do so for more complex binary logic operations.

Full Adder

Full adder is a conditional circuit which performs full binary addition that means it adds two bits and a
carry and outputs a sum bit and a carry bit. Any bit of augend can either be 1 or 0 and we can represent
with variable A, similarly any bit of addend we represent with variable B. The carry after addition of
same significant bit of augend and addend can represent by C. Hence truth table for all combinations of
A, B and C is as follows,

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 Table 1.2 : Truth Table for Full Adder

From the above table, we can draw K-map for sum (s) and final carry (Cout)

Figure 1.3 : K-map representation for carry and sum (Half Adder)
Hence, from K-maps,

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 Figure 1.4: Logic diagram for Full Adder

Figure 1.5: Logic diagram for Full Adder using Half Adder

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Output:-

Figure 1.6: Logic diagram for half Adder and Full Adder

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 Experiment No.:2
Objective: -Implementing Binary -to -Gray, Gray -to -Binary code conversions.

Theory:

Binary Codes:

A symbolic representation of data/ information is called code. The base or radix of the binary number is
2. Hence, it has two independent symbols. The symbols used are 0 and 1. A binary digit is called as a bit.
A binary number consists of sequence of bits, each of which is either a 0 or 1. Each bit carries a weight
based on its position relative to the binary point. The weight of each bit position is one power of 2 greater
than the weight of the position to its immediate right. e. g. of binary number is 100011 which is equivalent
to decimal number 35.

Gray Codes:

It is a non-weighted code; therefore, it is not suitable for arithmetic operations. It is a cyclic code because
successive code words in this code differ in one bit position only i.e., it is a unit distance code.

Applications of Gray Code:

1. In instrumentation and data acquisition system where linear or angular displacement is measured.

2. In shaft encoders, input-output devices, A/D converters and the other peripheral equipment.

Procedure: Binary to gray code:

No. Binary Gray

D C B A G3 G2 G1 G0

0 0 0 0 0 0 0 0 0

1 0 0 0 1 0 0 0 1

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 0 1 0

4 0 1 0 0 0 1 1 0

5 0 1 0 1 0 1 1 1

6 0 1 1 0 0 1 0 1

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 7 0 1 1 1 0 1 1 0

8 1 0 0 0 1 1 0 0

9 1 0 0 1 1 1 0 1

10 1 0 1 0 1 1 1 1

11 1 0 1 1 1 1 1 0

12 1 1 0 0 1 0 1 0

13 1 1 0 1 1 0 1 1

14 1 1 1 0 1 0 0 1

15 1 1 1 1 1 0 0 0

Table 2.1: Binary to Gray Converter

Binary to Gray:

Equations:

Diagram:

Logic diagram for Binary to Gray Convertor is given below:

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 Figure 2.1: Logic diagram for Binary to Gray Convertor

Gray to Binary:

No. Gray Binary

G3 G2 G1 G0 D C B A
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 1 0 0 1 0
3 0 0 1 0 0 0 1 1
4 0 1 1 0 0 1 0 0
5 0 1 1 1 0 1 0 1
6 0 1 0 1 0 1 1 0
7 0 1 1 0 0 1 1 1
8 1 1 0 0 1 0 0 0
9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0

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 13 1 0 1 1 1 1 0 1
14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1

Table 2.2: Gray to Binary Converter

Equations:

Diagram:

Figure 2.2: Logic diagram for Grey to Binary Convertor

Output: -

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Figure 2.2: Logic diagram for Binary to Grey Convertor

Figure 2.3: Logic diagram for Grey to Binary Convertor

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 Experiment No.:3

Objective: Implementing 3-8-line DECODER

Theory:-
Decoder

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that
converts coded inputs into coded outputs, where the input and output codes are different e.g. n-to-2n,
binary-coded decimal decoders. Decoding is necessary in applications such as data multiplexing, 7
segment display and memory address decoding.

The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1)
only when all its inputs are "High." Such output is called "active High output". If instead of AND gate,
the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output
is called "active low output".

A slightly more complex decoder would be the n-to-2n type binary decoders. These types of decoders
are combinational circuits that convert binary information from 'n' coded inputs to a maximum of 2n
unique outputs. In case the 'n' bit coded information has unused bit combinations, the decoder may have
less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.

The input to a decoder is a parallel binary number and it is used to detect the presence of a particular
binary number at the input. The output indicates the presence or absence of specific number at the decoder
input.

Procedure:

3:8 decoder

It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs, NAND gates
are used. It has 3 input lines and 8 output lines. It is also called as binary to octal decoder it takes a 3-bit
binary input code and activates one of the 8(octal) outputs corresponding to that code. The truth table is
as follows:

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Table 3.1: Truth Table of 3:8 decoder

Fig 3.1: Logic Diagram of 3:8 decoder

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Output:

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 Experiment No.:4

Objective: Implementing 4x1and 8x1 MULTIPLEXERS.

Theory:

Multiplexer

In electronics, a multiplexer or mux is a device that selects one of several analog or digital input signals
and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines, which are
used to select which input line to send to the output. An electronic multiplexer can be considered as a
multiple-input, single-output switch i.e., digitally controlled multi-position switch. The digital code
applied at the select inputs determines which data inputs will be switched to output.

A common example of multiplexing or sharing occurs when several peripheral devices share a single
transmission line or bus to communicate with computer. Each device in succession is allocated a brief
time to send and receive data. At any given time, one and only one device is using the line. This is an
example of time multiplexing since each device is given a specific time interval to use the line.

In frequency multiplexing, several devices share a common line by transmitting at different frequencies.

Table 4.1: Truth Table of 8:1 MUX

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 Fig 4.1: Logic Diagram of 8:1 MUX

Output:-

Figure 4.2: Logic Diagram of 8:1 MUX

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Fig 4.3: Logic Diagram of 8:1 MUX

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 Experiment No.:5
Objective: -Verify the excitation tables of various FLIP-FLOPS.
Theory:
Flip-flop
The memory elements in a sequential circuit are called flip-flops. A flip-flop circuit has two outputs, one
for the normal value and one for the complement value of the stored bit. Binary information can enter a
flip-flop in a variety of ways and gives rise to different types of flip-flops
SR flip-flop
The clocked SR flip-flop shown in Figure consists of a basic NOR flip-flop and two AND gates. The
outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and
R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to
the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to
momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either
state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the
transition to 0 at the end of the pulse.

Figure 5.1: Logic diagram for S-R Flip Flop

Table 5.1 : Truth Table for S-R Flip Flop

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 Q(t Q(t+1 S R
) )
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Table 5.2: Excitation Table for S-R Flip Flop

D- FLIP FLOP: - To avoid the forbidden case that occur in R-S Flip Flop. When R=S=1, DFlip Flop is
implemented, in the D Flip Flop. There is only one output. We can transmit the value of D at the output
the Flip Flop when CLK in high.
The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input
and the complement of the D input goes to the R input. The D input is sampled during the occurrence of
a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the
flip-flop switches to the clear state.

Figure 5.2:: Logic diagram for D Flip Flop

Table 5.3 : Truth Table for D Flip Flo

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 Q(t Q(t+1) D
)
0 0 0
0 1 1
1 0 0
1 1 1

Table 5.4: Excitation Table for D Flip Flop

JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined
in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK
flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and
K simultaneously, the flip-flop switches to its complement state, i.e., if Q=1, it switches to Q=0 and vice
versa.
A clocked JK flip-flop is shown in Figure; Output Q is ANDed with K and CP inputs so that the flip-flop
is cleared during a clock pulse only if Q was previously 1. Similarly, output Q' is ANDed with J and CP
inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.

Figure 5.3: Logic diagram for J-K Flip Flop

Table 5.5: Truth Table for J-K Flip Flop

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 Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Table 5.6: Excitation Table for J-K Flip Flop

T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure, the T flip-flop is obtained
from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock
pulse.

Figure 5.4:: Logic diagram for T Flip Flop

Table 5.7: Truth Table for T Flip Flop

Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0

Table 5.8: Excitation Table for T Flip Flop

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Output:

Fig 5.5: S-R Flip-Flop

Fig5.6:- D Flip-Flop

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Fig 5.7: J-K Flip-Flop

Fig 5.8: T Flip-Flop

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 Experiment No.:6
Object: - Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.

Theory:

An 8-bit Input/Output (I/O) system with four 8-bit internal registers is a fundamental digital system
designed to facilitate data input, output, and temporary data storage. Such a system can be implemented
using various hardware platforms, including input and output registers for storage flip flops. Normally D
flip flop is used in data transfer.
Introduction:
An 8-bit I/O system with four 8-bit internal registers is a versatile digital system that plays a crucial role
in various applications, from microcontrollers in embedded systems to data processing units in
computers. It serves as a bridge between the external world and the internal processing unit, enabling
data acquisition, manipulation, and transfer.
Circuit Diagram

Fig. 6.1: 8-bit input output using 4, 8-bit registers

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Output:-

Fig. 6.2: - An 8-bit Input/ Output system with four 8-bit Internal Registers

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 Experiment No.:7
Objective: Design of an 8-bit ARITHMETIC LOGIC UNIT
Theory:
Design of ALU:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition, subtraction,
division, multiplication and logical operations like and, or, XOR, NAND, NOR etc. A simple block
diagram of a 4 bit ALU for operations AND ,OR ,XOR and Add is shown here :

Figure7.1: The 4-bit ALU block is combined using 4 1-bit ALU block.
Design Issues:
The circuit functionality of a 1-bit ALU is shown here, depending upon the control signal S1 and S0 the
circuit operates as follows:
for Control signal S1 = 0, S0 = 0, the output is A AND B,
for Control signal S1 = 0, S0 = 1, the output is A OR B,
for Control signal S1 = 1, S0 = 0, the output is A XOR B,
for Control signal S1 = 1, S0 = 1, the output is A Add B.

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 Experiment No.:8
OBJECTIVE: Design the Data path of a computer from its register transfer Language Description.
Theory: The Register Transfer Language is the symbolic representation of notations used to specify the
sequence of micro-operations.

In a computer system, data transfer takes place between processor registers and memory and between
processor registers and input-output systems. These data transfer can be represented by standard notations
given below:

o Notations R0, R1, R2..., and so on represent processor registers.

o The addresses of memory locations are represented by names such as LOC, PLACE, MEM, etc.
o Input-output registers are represented by names such as DATA IN, DATA OUT and so on.
o The content of register or memory location is denoted by placing square brackets around the name
of the register or memory location.

Generally, computers use many registers for different purposes. We need to transfer the data and
instructions between these registers. So, To transfer the data between the registers, the common bus
system is used. For this purpose, we connect all registers with a common BUS through Multiplexer.
The 4-bit register means that the size of the register is 4-bit. These 4-bit register uses 4 multiplexers
because number of bits in the register is always equal to the number of multiplexers. This mechanism is
also known as a “4×1” multiplexer. The 4×1 Multiplexer means that there are four inputs to each
multiplexer from four registers and one output to the common bus.
There are 4 registers and 4 multiplexers, each register is of 4 bits, numbering from 0 to 3. There are 2
select lines S0 and S1. These lines are connected to the select inputs of the multiplexers from registers.
How are the bits transferred from the multiplexer to the common bus?
We give values to select lines and select lines are connected with every multiplexer. So the value of the
select line activates the relevant bit of each multiplexer and transfers it to the common bus. A table for
all combinations of select lines (S1S0) is given below.

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 SELECTED REGISTER TO TRANSFER
SELECT LINES COMBINATION S1S0
DATA

00 Register A

01 Register B

10 Register C

11 Register D

Table 8.1: Combinations of select lines (S1S0)

When S1S0=00, then Register “A” is activated. Select lines are connected to every multiplexer so, it
activates the zero (0) bit of every multiplexer because the Zero bit of each multiplexer is connected with
register A. So one output from each multiplexer will be sent to the common bus as shown in the following
diagram.

Figure 8.1: Representation of one output from each multiplexer

Output “A3” from Multiplexer 3, Output “A2” from Multiplexer 2, Output “A1” from Multiplexer 1, and
Output “A0” from Multiplexer 0, arrive at common bus from 4 multiplexers which are the values of
register A. So, data of register A is loaded now in a common bus which can be accessed by any other
register in the system, or any other part of the system i.e., ALU, memory, etc. And so on for other
registers.
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Output:-

Fig8.1: -Data path representation of a computer

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 Experiment No.:9
Object: - Design the control unit of a computer using either hardwiring or microprogramming
based on its register transfer language description.
Hardwired Control Unit: The control hardware can be viewed as a state machine that changes from one
state to another in every clock cycle, depending on the contents of the instruction register, the condition
codes, and the external inputs. The outputs of the state machine are the control signals. The sequence of
the operation carried out by this machine is determined by the wiring of the logic elements and hence
named “hardwired”.
● Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the
control signals.
● Hardwired control is faster than micro-programmed control.
● A controller that uses this approach can operate at high speed.
● RISC architecture is based on the hardwired control unit

Fig. 9.1 Harwired Control Unit

Microprogrammed Control Unit:

The control signals associated with operations are stored in special memory units inaccessible
by the programmer as Control Words.
Control signals are generated by a program that is similar to machine language programs.
The micro-programmed control unit is slower in speed because of the time it takes to fetch
microinstructions from the control memory.
Some Important Terms
41
Control Word: A control word is a word whose individual bits represent various control
signals.
Micro-routine: A sequence of control words corresponding to the control sequence of a
machine instruction constitutes the micro-routine for that instruction.
Micro-instruction: Individual control words in this micro-routine are referred to as
microinstructions.
Micro-program: A sequence of micro-instructions is called a micro-program, which is
stored in a ROM or RAM called a Control Memory (CM).
Control Store: the micro-routines for all instructions in the instruction set of a computer are
stored in a special memory called the Control Store.

Figure 9.2: Microprogrammed Control Unit

Output:-
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Fig 9.2: - Design the control unit of a computer

Experiment No.:10

43
Object: - Implement a simple instruction set computer with a control unit and a data path.

Theory:

Designing a simple Instruction Set Computer (ISC) with a control unit and a data path without
writing code involves understanding the basic architecture and components involved. Here's a
conceptual description of such a system:

Components of a Simple ISC:

Control Unit: The control unit manages the operation of the ISC. It's responsible for fetching
instructions, decoding them, and controlling the data path's operations.

Data Path: The data path consists of registers and components that perform arithmetic and logical
operations. It's where data is manipulated.

Registers: The ISC typically includes registers to store data temporarily. Common registers
include the Program Counter (PC), Instruction Register (IR), and general-purpose registers (e.g.,
R1, R2, R3).

Memory: The memory stores both program instructions and data. It's essential for reading
instructions and storing results.

Basic Instruction Set:

For this simple ISC, we'll define three instructions:

ADD: Add the values in two registers and store the result in a destination register.

Example: ADD R1, R2, R3 would add the contents of R1 and R2 and store the result in R3.

SUB: Subtract the value of one register from another and store the result in a destination register.

Example: SUB R2, R1, R3 would subtract the contents of R1 from R2 and store the result in R3.

LOAD: Load a value from memory into a register.

Example: LOAD R1, 42 would load the value 42 into R1.

Execution Steps:
Here are the high-level steps for executing instructions in this simple ISC:

Fetch: The control unit fetches the next instruction from memory based on the Program Counter
(PC).
Decode: The control unit decodes the fetched instruction to determine the operation (ADD, SUB,
LOAD) and the operands involved.
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Execute: The data path performs the specified operation, such as addition, subtraction, or loading,
based on the decoded instruction.

Write Back: The result of the operation is written back to the specified destination register or
memory location.

Update PC: The Program Counter is updated to point to the next instruction.

Repeat: Steps 1-5 are repeated until a halt or branching instruction is encountered.

Fig. 10.1: Central Processing Unit

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Output:-

Fig.10.2:- Simple instruction set computer with a control unit

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 Course Beyond Syllabus
S. CO Blooms Level
List of Experiments
No.

1 Design and Implement basic Logic BCS352.1, BCS352.3 K4

Gates
2 Design and implementation of Carry BCS352.1, BCS352.3 K4
Look ahead Adders.

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 Experiment No.:1
Objective: - Design and Implement basic Logic Gates.

Theory:
Boolean functions may be practically implemented by using electronic gates. The following points are
important to understand.

● Electronic gates require a power supply.

● Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and 5V
representing logic 0 and logic 1 respectively.
● The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5V
representing logic 0 and logic 1 respectively. In general, there is only one output to a logic
gate except in some special cases.
● There is always a time delay between an input being applied and the output responding.

Procedure:

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT,
NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid
of truth tables.

AND gate: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs
are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is
sometimes omitted i.e. AB

Figure 1.1: Logic Diagram for AND gate

Table 1.1: Truth table for AND Gate

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 OR gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show the OR operation.

Figure 1.2: Logic Diagram for AND gate

Table 1.2: Truth Table for OR gate

NOT gate: The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT
A. This is also shown as A', or A with a bar over the top, as shown at the outputs.

Figure 1.3: Logic Diagram for NOT gate

Table 1.3: Truth Table for NOT gate

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NAND gate: This is a NOT-AND gate which is equal to an AND gate followed by a NOT
gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND
gate with a small circle on the output. The small circle represents inversion.

Figure 1.4: Logic Diagram for AND gate

Table 1.4: Truth Table for NAND Gate

NOR gate: This is a NOT-OR gate which is equal to an OR gate followed by a NOT
gate. The outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

Figure 1.5: Logic Diagram for NOR gate

Table 1.5: Truth Table for NOR Gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs
of all NOR gates are low if any of the inputs are high.
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The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

EX-OR Gate: The 'Exclusive-OR' gate is a circuit which will give a high output if either,
but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the
EOR operation.

Figure 1.6: Logic Diagram for EX-OR gate

Table 1.6: Truth Table for EX-OR Gate

EXNOR gate: The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It
will give a low output if either, but not both, of its two inputs are high. The symbol is an
EXOR gate with a small circle on the output. The small circle represents inversion.

Figure 1.7: Logic Diagram for EX-NOR gate

Table 1.7: Truth Table for EX-NOR Gate

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 The NAND and NOR gates are called universal functions since with either one the AND
and OR functions and NOT can be generated.
Output: -

Fig 1.8:- Circuit diagram for various logic gates

Experiment: -2
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OBJECTIVE: Design of Carry Look ahead Adders.

Theory: To reduce the computation time, there are faster ways to add two binary numbers by using carry
look ahead adders. They work by creating two signals P and G known to be Carry Propagator and
Carry Generator. The carry propagator is propagated to the next level whereas the carry generator is
used to generate the output carry, regardless of input carry. The block diagram of a 4-bit Carry Look
ahead Adder is shown here below -
Figure
2.1:
Logic
Diagram
for Carry
Look
ahead
Adder

The number of gate

levels for the carry
propagation can be found from the circuit of full adder. The signal from input carry C in to output carry
Cout requires an AND gate and an OR gate, which constitutes two gate levels. So if there are four full
adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate levels from C1 to C5. For an
n-bit parallel adder, there are 2n gate levels to propagate through.

Design Issues:

The corresponding boolean expressions are given here to construct a carry look ahead adder.
In the carry-look ahead circuit we need to generate the two signals carry propagator(P) and
carry generator(G),

Pi = Ai⊕ Bi

Gi = Ai · Bi

The output sum and carry can be expressed as

Sumi = Pi⊕ Ci

Ci+1 = Gi + ( Pi · Ci)

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 Having these we could design the circuit. We can now write the Boolean function for the carry
output of each stage and substitute for each Ci its value from the previous equations:

C1 = G0 + P0 · C0

C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0

C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0

C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0

Output:

Fig 2.2:- Logic diagram for Carry Look ahead Adder

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