CSE 331: Microprocessor Interfacing and

Embedded Systems

Lecture 10
Instruction Representation
 Stored-Program Concept

❖ Computers built on 2 key principles:

1) Instructions are represented as
numbers.
2) Therefore, entire programs can be
stored in memory to be read or
written just like numbers (data).
❖ Simplifies Software/Hardware of computer
systems:
❖Memory technology for data also used for
programs
 Consequence #1: Everything Addressed

❖Since all instructions and data are stored in memory as

numbers, everything has a memory address: instructions,
data words
❖ both branches and jumps use these
❖ One register keeps address of instruction being executed:
“Program Counter” (PC)
❖Basicallya pointer to memory: Intel calls it Instruction
Address Pointer, a better name
 Consequence #2: Binary Compatibility

❖ Programs are distributed in binary form

❖ Programs bound to specific instruction set
❖ Different version for Macintosh and IBM PC

❖ Leads to instruction set evolving over time

❖Selection of Intel 8086 in 1981 for 1st IBM PC is
major reason latest PCs still use 80x86
instruction set (Pentium 4); could still run program
from 1981 PC today
 Instructions as Numbers

❖Most of the data that we work with is in

words (32-bit blocks):
❖ Each register is a word.
❖LDR and STR both access memory one word
at a time.
❖ So how do we represent instructions?
❖Remember: Computer only understands 1s and
0s, so “ADD r0,r0,#0” is meaningless.
❖ “Regular”
ARM instructions are 32 bits.
❖ Thumb ARM instructions are 16 bits.
 Instructions as Numbers
❖ Divide instruction word into “fields”
❖Each field tells computer something about
instruction
❖There is an attempt to reuse fields across
instructions as much as possible.
❖Simple = less complex hardware which
generally leads to better performance
 Data Processing Instructions

❖ Define “fields”:

❖Important: Each field is viewed as an independent

unsigned integer, not as part of a 32-bit integer.
❖Consequence: 5-bit fields can represent any number 0-
31, while 6-bit fields can represent any number 0-63.
 Data Processing Instructions

❖ What do these field integer values tell us?

❖OpCode: specifies the specific data processing instruction
 Data Processing Instructions

❖ What do these field integer values tell us?

❖ Rd: Destination Register
❖ Rn: 1st Operand Register

❖Each register field is 4 bits, which means that it

can specify any unsigned integer in the range 0-
15. Each of these fields specifies one of the 16
registers by number.
 Data Processing Instructions

❖ More fields:
❖I (Immediate)
❖ 0: Operand 2 is a Register

❖ 1: Operand 2 is an Immediate
 Data Processing Instructions

❖ Operand 2:

❖ Shift field:
 Condition Field

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 Data Processing Instructions

❖ More fields:
❖S (Set Condition Fields)
❖ 0: Do not alter condition fields
❖ 1: Set condition fields

❖ These set the C, N, Z, V flags in the CPSR

❖ Cond (Condition Field)

❖Determines whether the instruction resulted is
committed
❖ Used with ADDEQ, ADDNE, ADDGT, etc.
 Data Processing Instructions

❖ Define “fields”:

❖Important: Each field is viewed as an independent

unsigned integer, not as part of a 32-bit integer.
❖Consequence: 5-bit fields can represent any number 0-
31, while 6-bit fields can represent any number 0-63.
 Loading Constants

❖ Constants can only be 8 bit numbers

❖ Allows assignment of numbers between 0-255 or
[0x00 – 0xFF]
❖ Why? Constants stored in code and there is limited
space (only 32 bits).
❖ Assignment in Assembly
❖ Example: MOV r0,#0xFF (in ARM)

Equivalent to: a = 255 (in C)

where ARM registers r0 C variable a

 Using a Barrel Shifter
Register, optionally with shift operation
Operand 1 Operand 2 ❖ Shift value can be either be:
❖ 5 bit unsigned integer
❖ Specified in bottom byte of
another register.
Barrel
❖ Used for multiplication by
Shifter
constant
Immediate value
❖ 8 bit number, with a range of
0-255.
ALU
❖ Rotated right through even
number of positions
❖ Allows increased range of 32-
Result
bit constants to be loaded
directly into registers
 Immediate Constants
❖ The data processing instruction format has 12 bits available for operand2

0xFF000000
x2
Shifter MOV r0, #0xFF, ROR #8
ROR

❖ Rule to remember is “8-bits rotated right by an

even number of bit positions”
 Shifts and Rotates
❖ LSL – logical shift left by n bits – multiplication by 2n
C … 0

❖ LSR–logical shift right by n bits–unsigned division by 2n

0 … C
❖ ASR – arithmetic shift right by n bits – signed
division by 2n
… C

❖ ROR – rotate right by n bits – 32 bit

rotate
… C
 Loading Constants
Rotate Value Binary Decimal Hexadecimal
0 000000000000000000000000xxxxxxxx 0-255 0-0xFF
Right, 30 bits 0000000000000000000000xxxxxxxx00 4-1020 0x4-0x3FC
Right, 28 bits 00000000000000000000xxxxxxxx0000 16-4080 0x10-0xFF0
Right, 26 bits 000000000000000000xxxxxxxx000000 128-16320 0x40-0x3FC0
… … … …
Right, 8 bits xxxxxxxx000000000000000000000000 16777216- 0x1000000-
255x224 0xFF000000
Right, 6 bits xxxxxx0000000000000000000000xx - -
Right, 4 bits xxxx0000000000000000000000xxxx - -
Right, 2 bits xx0000000000000000000000xxxxxx - -

❖ This scheme can generate a lot, but not all, constants.

❖ ❖ Others must be done using literal pools (more on that later)
 Data Processing Example
❖ ARM Instruction: ADD r0,r1,r2
cond = 1110 (always – unconditional)
S = 0 (not ADDS)
I = 0 (second operand not a constant)
opcode = 0100 (look up)
rd = 0 (destination operand)
rn = 1 (first operand) operand 2
shift = 0
Rm = 2
 Data Processing Example
❖ ARM Instruction: ADD r0,r1,r2

1110 0100
0 0 0000 0001 00000000 0001

Binary number per field representation:

hex representation: 0xE0810002

❖ Called a Machine Language Instruction

 Data Processing Example
❖ ARM Instruction:SUBEQ r0,r10,r2,LSL #3
cond = 0000 (equal)
S = 0 (not SUBEQS)
I = 0 (second operand not a constant)
opcode = 0010 (look up)
rd = 0000 (destination operand: r0)
rn = 1010 (1st operand: r10)
operand 2
rm = 0010 (2nd operand: r2)
shift amount = 00011
Shift Type = 00
 Data Processing Example
❖ ARM Instruction: SUBEQ a1,v7,r2,LSL
##3
3
0000 0010 0 1010 0000 00011 00 0 0010
0

Hex representation: 0x004A0182

 Data Processing Example
❖ ARM Instruction:BIC r9,r0,r1,ROR r5
cond = 1110 (always)
S = 0 (not BICS)
I = 0 (second operand not a constant)
opcode = 1110 (look up)
rd = 1001 (destination operand: r9)
rn = 0000 (1st operand: r0)
operand 2
rm = 0001 (2nd operand: r1)
rs = 0101 (shift operand: r5)
Shift Type = 11 (ROR)
 Data Processing Example
❖ ARM Instruction: BIC v6,a1,a2,ROR v2
❖#
3
1110 1110
0 0 0000 1001 0101 0 11 1 0001

Hex representation: 0xE1C09571

 Data Processing Example
❖ ARM Instruction:EORGTS r6,r2,#10
cond = 1100 (greater than)
S = 1
I = 1 (second operand is a constant)
opcode = 0001 (look up)
rd = 0110 (destination operand: r6)
rn = 0010 (1st operand: r2)
operand 2
rotate = 0000
imm = 0x0A
 Data Processing Example
❖ ARM Instruction: EORGTS r6,r2,#10
❖#
3
1100 0001 1
1 0010 0110 0000 0000 1010

Hex representation: 0xC232600A

 Branch Instructions
❖ What fields do we need for Branch Instructions?
❖ Opcode

❖ Label

❖ Condition
 Branch Instructions

❖ Opcode
❖ 101 for Branch
❖ Link bit is set if BL

❖ Condition – same as before (EQ, LT, GT,

etc.)
 Branch Instructions

❖ Label
❖ Uses offset, i.e., how far to branch. PC = PC + offset.
❖ As opposed to absolute address of the instruction.

❖ 24 bits allows us to branch +/- 8 Mbytes.

❖Instructions 32 bits = 4 bytes, so add implicit 00 at end.

Now can branch +/- 32 Mbytes.
❖ Equivalent to +/- 8 Minstructions.

❖Start counting 2 instructions later (due to pipelining).

 Branches: PC-Relative Addressing

❖Solution to branches in a 32-bit instruction:

PC-Relative Addressing
❖Let the 24-bit offset field be a signed
two’s complement integer to be added to the
PC if we take the branch.
❖Now we can branch +/- 223 bytes from the
PC, which should be enough to cover almost
any loop.
❖ Any ideas to further optimize this?

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 Branches: PC-Relative Addressing

❖Note: Instructions are words, so they’re word

aligned (byte address is always a multiple of
4, which means it ends with 00 in binary).
❖So the number of bytes to add to the PC will
always be a multiple of 4.
❖ So specify the offset in words.

❖Now, we can branch +/- 223 words from the

PC (or +/- 225 bytes), so we can handle loops
4 times as large.
 Branches: PC-Relative Addressing
❖ Branch Calculation:
❖ Observations
❖ offset field specifies the number of words to
jump, which is simply the number of instructions to
jump.
❖ offset field can be positive or negative.
 Branch Example
❖ ARM Instruction: BEQ offset
cond = 0000 (equal)
L = 0 (not a BL instruction)
Offset = -2 = 0xFFFFFE Number of
instructions subtract from) the PC

0000 0 1111 1111 1111 1111 1111 1110

Hex representation:
0x0AFFFFFE
 Data Transfer Instructions

❖Cond: condition field. Execute instruction

when condition is met.
❖ I: immediate field. Determines type of offset.
❖ 0: if offset is an immediate
❖ 1: if offset is a register

❖ P: pre/post indexing bit.

❖ 0: post - add offset after transfer
❖ 1: pre - add offset before transfer
 Data Transfer Instructions

❖ U: up/down bit.
❖ 0: down - subtract offset from base
❖ 1: up - add offset to base

❖ B: byte/word bit.
❖ 0: transfer word quantity
❖ 1: transfer byte quantity

❖ W: write-back bit.
❖ 0: no write-back
❖ 1: write address into base
 Data Transfer Instructions

❖ L: load/store bit.
❖ 0: store into memory
❖ 1: load from memory

❖ Rn: base register

❖ Rd: source/destination register
 Data Transfer Instructions

❖ Offset: source/destination register

❖I bit = 0

❖I bit = 1
Addressing Mode
 Data Transfer Example
❖ ARM Instruction: LDR r8,[sp]

cond = 1110 (always – unconditional)

I = 0 (immediate: there is no offset, or offset = 0)
P = 1 (pre-increment: there is no offset)
U = 1 (add offset to base; there is no offset)
B = 0 (transfer word)
W = 0 (no writeback)
L = 1 (load)
rd = 8 = 1000 (destination operand)
rn = 13 = 1101 (base register)
Offset = 0 (there is no offset)
 Data Transfer Example
❖ ARM Instruction: LDR r8,[sp]

0 1 1 0 0 1 1101
1110 1000 0000 0000 0000

Binary number per field representation:

hex representation: 0xE59D8000
 Data Transfer Example
❖ ARM Instruction: STRB r10,[sp,#-4]!

cond = 1110 (always – unconditional)

I = 0 (offset is an immediate value)
P = 1 (pre-index – add immediate before transfer)
U = 0 (subtract offset from base)
B = 1 (transfer byte)
W = 1 (write address into base)
L = 0 (store)
rd = 10 = 1010 (destination operand)
rn = sp = r13 = 1101 (base register)
Offset = 0x004
 Data Transfer Example
❖ ARM Instruction: STRB r10,[sp,#-4]!

1110 0 1 0 1 1 0 1101 1010 0000 0000 0100

Binary number per field representation:

hex representation: 0xE56DA004
 Data Transfer Example
❖ ARM Instruction: LDRB r2,[r1],-r3, LSR #4

cond = 1110 (always – unconditional)

I = 1 (offset is a register)
P = 0 (post-index – add immediate after transfer)
U = 0 (subtract offset from base)
B = 1 (transfer byte)
W = 1 (write address into base)
L = 1 (load)
rd = 2 = 0010 (destination operand)
rn = 1 = 0001 (base register)
 Data Transfer Example
❖ ARM Instruction: LDRB r2,[r1],-r3, LSR #4

Offset:
shift:
shift amount = 4 = 00100
shift type = 01
rm = 3 = 0011
 Data Transfer Example
❖ ARM Instruction: LDRB r2,[r1],-r3, LSR #4

1110 1 0 0 1 0 1 0001 0010 00100 01 0 0011

Binary number per field representation:

hex representation: 0xE651223
Addressing Mode
Instruction Format Summary
 Conclusion

❖Computer actually stores programs as a series of these

32-bit numbers.
❖Each instruction has different number of fields that
define it (opcode, registers, immediates, etc.)
❖ARM Machine Language Instruction:
32 bits representing a single instruction
Appendix
 Branches: PC-Relative Addressing
❖ Branch Calculation:
❖ If we don’t take the branch:
PC = PC+4 +Offset* 4

❖ If we do take the branch:

PC = (PC + 8) + (offset * 4)
Why two? Pipelining starts next two
following instructions before current one is
finished.
Further explanation:
https://docs.google.com/document/d/14h_Njrb
xrZioHhU6ruQBmt_Xtl7a_xlm0WrbMigEQe