Interrupt-Operations

• Interrupt is signals send by an external device to the

processor, to request the processor to perform a
particular task or work.
• Mainly in the microprocessor based system the
interrupts are used for data transfer between the
peripheral and the microprocessor.
• Need for Interrupt: Interrupts are particularly useful
when interfacing I/O devices that provide or require
data at relatively low data transfer rate.
 Interrupt Operations
• From the point of view of I/O unit • From the point of view of processor
• I/O device receives command from • The CPU issues command and then
CPU goes off to do its work.
• The I/O device then processes the • When the interrupt from I/O device
operation occurs, the processor saves its
• The I/O device signals an interrupt to program counter & registers of the
the CPU over a control line. current program and processes the
interrupt.
• The I/O device waits until the request
from CPU. • After completion for interrupt,
processor requires its initial task.
 Polling versus Interrupt
• Polling the device usually means reading its status register every so often until the device's status
changes to indicate that it has completed the request.
• Polling means the CPU keeps checking a flag to indicate if something happens.
• An interrupt driven device driver is one where the hardware device being controlled will cause a
hardware interrupt to occur whenever it needs to be serviced.
• With interrupt, CPU is free to do other things, and when something happens, an interrupt is
generated to notify the CPU. So it means the CPU does not need to check the flag.
• Polling is like picking up your phone every few seconds to see if you have a call. Interrupts are like
waiting for the phone to ring.
• Interrupts win if processor has other work to do and event response time is not critical.
• Polling can be better if processor has to respond to an event ASAP; may be used in device
controller that contains dedicated secondary processor.
 Interrupt • There are mainly two ways of
servicing multiple interrupts which
structures: are polled interrupts and daisy
chain (vectored) interrupts.
 • Polled interrupts are handled by using software
which is slower than hardware interrupts.
• Here the processor has the general (common)
interrupt service routine (ISR) for all devices.
• The priority of the devices is determined by the
polled order in which the routine polls each device.

interrupts • The processor checks the starting with the

highest priority device.
• Once it determines the source of the interrupt,
it branches to the service routine for that
device.
• Here several external devices are connected to a
single interrupt line (INTR) of the microprocessor.
• When INTR signal goes up, the processor saves the
contents of PC and other registers and then branches
to an address defined by the manufactures of the
processor.
• The user can write a program at this address to find
the source of the interrupt by starting the polled from
highest priority device.
Daisy chain (vectored) interrupt
• In polled interrupt, the time required to poll each device may exceed the time to
service the device through software.
• To improve this, the faster mechanism called vectored or daisy chain interrupt is used.
• Here the devices are connected in chain fashion.
• When INTR pin goes up, the processor saves its current status and then generates INTA
signal to the highest priority device.
• If this device has generated the interrupt, it will accept the INTA; otherwise it will push
INTA to the next priority device until the INTA is accepted by the interrupting device.
• When INTA is accepted, the device provides a means to the processor for
findings the interrupt address vector using external hardware.
• The accepted device responds by placing a word on the data lines which
becomes the vector address with the help of any hardware through which
the processor points to appropriate device service routine.
• Here no general interrupt service routine need first that means
appropriate ISR of the device will be called.
 • The interrupt driven I/O operation takes the following steps.
• The I/O unit issues an interrupt signal to the processor for
exchange of data between them.
• The processor finishes execution of the current instruction
before responding to the interrupt.

Interrupt • The processor sends an acknowledgement signal to the device

that it issued the interrupt.

Processing • The processor transfers its control to the requested routine

called “Interrupt Service Routine (ISR)” by saving the contents
Sequence of program status word (PSW) and program counter (PC).
• The processor now loads the PC with the location of interrupt
service routine and the fetches the instructions. The result is
transferred to the interrupt handler program.
• When interrupt processing is completed, the saved register’s
value are retrieved from the stack and restored to the register.
• Finally it restores the PSW and PC values from the stack.
• The figure summarizes these steps.
• The processor pushes the flag register on the
stack, disables the INTR input and does
essentially an indirect call to the interrupt
service procedure.
• An IRET function at the end of interrupt
service procedure returns execution to the
main program.
 • If the processor gets multiple interrupts,
then we need to deal these interrupts one at
a time and the dealing approaches are:
• a. Sequential processing of interrupts
• When user program is executing and an
Interrupt interrupt occurs interrupts are disabled
priority: immediately.
• After the interrupt service routine
completes, interrupts are enabled before
resuming the user program and the
processor checks to see if additional
interrupts have occurred.
• b. Priority wise processing of
interrupts:
 • An interrupt service routine (ISR) is
a software routine that hardware
invokes in response to an interrupt.

Interrupt • ISRs examine an interrupt and

determine how to handle it.
Service • ISR is responsible for doing the
Routine following things:
• 1. Saving the processor context
• 2. Acknowledging the interrupt
• 3. Restoring the processor context
Types of interrupt
• 1. External interrupts:
• These interrupts are initiated by external devices such as
A/D converters and classified on following types.
• Maskable interrupt :
• It can be enabled or disabled by executing instructions such
as EI and DI. In 8085, EI sets the interrupt enable flip flop
and enables the interrupt process. DI resets the interrupt
enable flip flop and disables the interrupt.
• Non-maskable interrupt:
• It has higher priority over maskable interrupt and cannot be
enabled or disabled by the instructions.
• 2. Internal interrupts:
• These are indicated internally by exceptional conditions such as overflow, divide
by zero, and execution of illegal op-code. The user usually writes a service routine
to take correction measures and to provide an indication in order to inform the
user that exceptional condition has occurred.
• There can also be activated by execution of TRAP instruction. This interrupt
means TRAP is useful for operating the microprocessor in single step mode and
hence important in debugging.
• These interrupts are used by using software to call the function of an operating
system. Software interrupts are shorter than subroutine calls and they do not
need the calling program to know the operating system’s address in memory.
Interrupt Processing in 8085
• Types of Interrupts:
• 1.Software interrupts:
• The software interrupts are program instructions. These instructions
are inserted at desired locations in a program.
• The 8085 has eight software interrupts from RST 0 to RST 7. The
vector address for these interrupts can be calculated as follows.
• Interrupt number * 8 = vector address
• For RST 5; 5 * 8 = 40 = 28H
• Vector address for interrupt RST 5 is 0028H
Interrupt Vector address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
• B.Hardware interrupts
• An external device initiates the
hardware interrupts and placing an
appropriate signal at the interrupt
pin of the processor.
• If the interrupt is accepted then
the processor executes an interrupt
service routine.
• The 8085 has five hardware
interrupts
Programmable Interrupt Controller (PIC) -8259A
• 8259 is Programmable Interrupt Controller (PIC)
• It is a tool for managing the interrupt requests.
• 8259 is a very flexible peripheral controller chip:
• PIC can deal with up to 64 interrupt inputs
• interrupts can be masked
• various priority schemes can also be programmed.
• originally (in PC XT) it is available as a separate IC
• Later the functionality of (two PICs) is in the motherboards chipset.
• In some of the modern processors, the functionality of the PIC is built in.