ASSOCIATION CONNECTING

ELECTRONICS INDUSTRIES ®
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IPC-9701A

Performance Test Methods

and Qualification Requirements
for Surface Mount Solder
Attachments

IPC-9701A
February 2006 A standard developed by IPC

Supersedes IPC-9701 3000 Lakeside Drive, Suite 309S, Bannockburn, IL 60015-1219

January 2002 Tel. 847.615.7100 Fax 847.615.7105
www.ipc.org

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 The Principles of In May 1995 the IPC’s Technical Activities Executive Committee (TAEC) adopted Principles of
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• Just include spec information • Tell you how to make something

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 IPC-9701A
ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

Performance Test
Methods and Qualification
Requirements for Surface
Mount Solder Attachments

Developed by the SMT Attachment Reliability Test Methods Task Group

(6-10d) of the Product and Reliability Committee (6-10) of IPC

Supersedes: Users of this publication are encouraged to participate in the

IPC-9701 - January 2002 development of future revisions.

Contact:

IPC
3000 Lakeside Drive, Suite 309S
Bannockburn, Illinois
60015-1219
Tel 847 615.7100
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Fax 847 615.7105
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 IPC-9701A February 2006

Acknowledgment
Any document involving a complex technology draws material from a vast number of sources. While the principal members
of the SMT Attachment Reliability Test Methods Task Group (6-10d) of the Product and Reliability Committee (610) are
shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them, the
members of the IPC extend their gratitude.

Product and Reliability SMT Attachment Reliability Technical Liaisons of the

Committee Test Methods Task Group IPC Board of Directors
Chair Chair
Reza Ghaffarian, Ph.D Reza Ghaffarian, Ph.D Peter Bigelow
Jet Propulsion Laboratory Jet Propulsion Laboratory IMI Inc.
Vice-Chair Vice-Chair Sammy Yi
Werner Engelmaier Werner Engelmaier Flextronics International
Engelmaier Associates, L.C. Engelmaier Associates, L.C. Sanmina

SMT Attachment Reliability Test Methods Task Group

Mudasir Ahmad, Cisco Systems, Inc. Jennie Hwang, Ph.D., Asahi America, Brett Ong, Sun Microsystems, Inc.
Patricia J. Amick, Boeing Aircraft & Inc. Michael D. Osterman, University of
Missiles Vincent B. Kinol, Umicore America Maryland
David Baker, Tessera, Inc. Inc. Deepak K. Pai, C.I.D.+, General
Jean Bobgan, Guidant Corporation Gregg Klawson, General Dynamics - Dynamics-Advanced Information
C4 Systems S.Y. Pai, Xilinx, Inc.
Nicole Butel, Agilent Technologies
Kuan-Shaur Lei, Hewlett-Packard Mel Parrish, STI Electronics, Inc.
Srinivas Chada, Ph.D, Jabil Circuit,
Company
Inc. Kumar Pavuluri, Texas Instruments
James F. Maguire, Intel Corporation Inc.
Beverley Christian, Ph.D., Research
In Motion Limited Wesley R. Malewicz, Draeger Vincent M. Rogers, IBM Corporation
Medical Systems, Inc.
Jean-Paul Clech, EPSI Olli Salmela, Nokia Corporation
John Manock, Lucent Technologies,
Thomas Clifford, Lockheed Martin Sundar Sethuraman, Solectron
Inc.
Space Systems Company Corporation
Susan S. Mansilla, Robisan
Roger Cox, Key Tronic Corporation Rocky Shih, Hewlett-Packard
Laboratory Inc.
Howard S. Feldmesser, Johns Company
Brian C. McCrory, Delsen Testing
Hopkins University Vern Solberg, Mico Electronic
Laboratories
Mahendra S. Gandhi, Northrop Engineering Services
Stephan Meschter, Ph.D., BAE
Grumman Vasu S. Vasudevan, Intel Corporation
Systems Platform Solutions
Luke J. Garner, Intel Corporation Dewey Whittaker, Honeywell Inc.
Frank Mortan, Texas Instruments
Phil Geng, Intel Corporation Leilei Zhang, Xilinx, Inc.
John Moylan, Delsen Testing
Denis Gignac, Nortel Networks Laboratories
Hana Hsu, Mitac International Keith G. Newman, Sun Microsystems
Corporation Inc.

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 February 2006 IPC-9701A

Table of Contents
1 SCOPE ...................................................................... 1 3.4.21 Wearout Failures ................................................. 5
1.1 Purpose ................................................................ 1 3.5 Statistical Failure Distribution Concepts ........... 6
1.2 Performance Classification ................................. 1 3.5.1 Statistical Failure Distribution ........................... 6
1.3 Definition of Terms ............................................ 1 3.5.2 Mean Fatigue Life, N(50%) ............................... 6
3.5.3 Failure Free Life, N0 .......................................... 6
2 APPLICABLE DOCUMENTS ................................... 1
3.5.4 Cumulative Failure Percentage .......................... 6
2.1 IPC ...................................................................... 1 3.5.5 Cumulative Failure Probability .......................... 6
2.2 Joint Industry Standards ..................................... 2 3.5.6 Acceptable Cumulative Failure Probability ....... 6
2.3 International Tin Research Institute ................... 2 3.6 Reliability Tests .................................................. 6
2.4 Other Publications .............................................. 2 3.6.1 Accelerated Reliability Test ............................... 6
2.4.1 Electronic Industries Association ....................... 2 3.6.2 Thermal Cycling ................................................. 6
2.4.2 OEM Working Group ......................................... 2 3.6.3 Thermal Shock .................................................... 6
3.6.4 Power Cycling .................................................... 6
3 TERMS, DEFINITIONS AND CONCEPTS ............... 2
3.7 Other Tests .......................................................... 6
3.1 General ................................................................ 2
3.7.1 Burn-In Test ........................................................ 6
3.2 Reliability Concepts ........................................... 2
3.7.2 Environmental Stress Screening (ESS) .............. 6
3.2.1 Reliability Definition .......................................... 3 3.7.3 Highly Accelerated Stress Testing (HAST) ....... 6
3.3 Physics-of-Failure Concepts ............................... 3 3.7.4 Mechanical Shock .............................................. 6
3.3.1 Creep ................................................................... 3 3.7.5 Vibration ............................................................. 7
3.3.2 Stress Relaxation ................................................ 3 3.7.6 Process Qualification .......................................... 7
3.3.3 Solder Creep-Fatigue Model .............................. 3 3.7.7 Process Verification ............................................ 7
3.3.4 Differential Thermal Expansion ......................... 3 3.8 Evaluation and Application Considerations ....... 7
3.4 Test Parameters ................................................... 3 3.9 Understanding of Solder Attachment Technology .... 7
3.4.1 Working Zone ..................................................... 3
4 PERFORMANCE TEST METHODS ......................... 7
3.4.2 Cyclic Temperature Range/Swing ...................... 3
4.1 General Requirements ........................................ 7
3.4.3 Sample Temperature: Ts ..................................... 5
4.2 Test Vehicles ....................................................... 7
3.4.4 Maximum Sample Temperature: Ts (max) ........ 5
4.2.1 Component Description ...................................... 7
3.4.5 Maximum Nominal Temperature: T (max) ....... 5
4.2.2 Printed Wiring (Circuit) Boards ....................... 10
3.4.6 Minimum Sample Temperature: Ts (min) ......... 5
4.2.3 Board Assembly ................................................ 11
3.4.7 Minimum Nominal Temperature: T (min) ......... 5
4.3 Accelerated Temperature Test Methods ........... 12
3.4.8 Mean Cyclic Temperature, TSJ ........................... 5
4.3.1 Preconditioning by Isothermal Aging .............. 12
3.4.9 Nominal ∆T ........................................................ 5
4.3.2 Temperature Cycling ........................................ 12
3.4.10 Dwell/Soak Time, tD .......................................... 5
4.3.3 Test Monitoring ................................................ 12
3.4.11 Dwell/Soak Temperature .................................... 5
3.4.12 Cycle Time .......................................................... 5 5 QUALIFICATION REQUIREMENTS ...................... 13
3.4.13 Temperature Ramp Rate ..................................... 5 5.1 Thermal Cycling Ranges .................................. 13
3.4.14 Maximum Cyclic Strain Range .......................... 5 5.2 Thermal Cycling Test Durations ...................... 14
3.4.15 Maximum Cyclic Stress Range .......................... 5 5.3 Number of Samples .......................................... 14
3.4.16 Hysteresis Loop .................................................. 5 5.4 Test Exemption Requirements ......................... 14
3.4.17 Design Service Life ............................................ 5 6 FAILURE ANALYSIS .............................................. 14
3.4.18 Projected Service Life Service ........................... 5 6.1 Failure Analysis Procedures ............................. 14
3.4.19 Infant Mortality Failures .................................... 5 6.2 Failure Analysis Documentation
3.4.20 Random Steady-State Failures ........................... 5 Requirements .................................................... 14

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 IPC-9701A February 2006

7 QUALITY ASSURANCE ......................................... 14 Tables

7.1 Responsibility for Inspection ........................... 14 Table 3-1 Product Categories and Worst-Case
7.2 Quality Conformance Inspection ..................... 14 Use Environments for Surface
Mounted Electronics ............................................ 4
7.2.1 As Assembled Inspection ................................. 14
Table 4-1 Temperature Cycling Requirements .................... 8
7.2.2 Thermal Cycling Inspection ............................. 15
Table 4-2 Daisy Chain Requirements ................................. 8
7.2.3 Failure Analysis Inspection .............................. 15 Table 4-3 Test Exemption Requirements ............................ 9
APPENDIX A .............................................................. 16 Table 4-4 Test Monitoring Requirements .......................... 13
Table A-1 Values for Exponent ‘‘m’’ for the Four
APPENDIX B .............................................................. 18 Test Condition Levels and for Four
Representative Product Use Conditions ........... 17
Figures Table A-2 Mean Fatigue Lives for a Given Component
Assembly for the Four Test Condition
Figure 3-1 Representative Temperature Profile for Levels and for Four Representative
Thermal Cycle Test Conditions ......................... 3 Product Use Conditions .................................... 17
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 February 2006 IPC-9701A

Performance Test Methods and Qualification

Requirements for Surface Mount Solder Attachments

1 SCOPE 1.5 Revision Level Changes Changes made to this revi-

This specification establishes specific test methods to sion of the IPC-9701 include Appendix B which establishes
evaluate the performance and reliability of surface mount guidelines for thermal cycle requirements for Pb-free sol-
solder attachments of electronic assemblies. It further der joints. Appendix B provides additional recommenda-
establishes different levels of performance and reliability of tions to existing IPC-9701 section requirements when uti-
the solder attachments of surface mount devices to rigid, lizing a Pb-free soldering process.
flexible and rigid-flex circuit structures. In addition, it pro-
vides an approximate means of relating the results from 2 APPLICABLE DOCUMENTS
these performance tests to the reliability of solder attach- The following documents are applicable and constitute a
ments for the use environments and conditions of elec- part of this specification to the extent specified herein. Sub-
tronic assemblies. sequent issues of, or amendments to, these documents will
become a part of this specification. Documents are grouped
1.1 Purpose The purpose of this document is: under categories as IPC, Joint Industry Standard, ITRI,
• To provide confidence that the design and the EIA and others depending on the source.
manufacturing/assembly processes create a product that is
capable of meeting its intended goals. 2.1 IPC1

• To permit the analytical prediction of reliability based on IPC-T-50 Terms and Definitions for Interconnecting and
a generic database and technical understanding. Packaging Electronic Circuits
• To provide standardized test methods and reporting pro-
IPC-D-279 Design Guidelines for Reliable Surface Mount
cedures.
Technology Printed Board Assemblies
1.2 Performance Classification This specification rec-
IPC-TM-650 Test Methods Manual2
ognizes that surface mount assemblies (SMAs) will be sub-
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ject to variations in performance requirements based on 2.1.1 Microsectioning

end use. While Performance Classes are defined in IPC- 2.4.1 Adhesion, Plating
6011, Generic Performance Specification for Printed 2.4.8 Peel Strength, Metal Foil
Boards, these performance classifications are not specific 2.4.21.1 Bond Strength, Surface Mount Land (Perpen-
as to the required reliability. At this point in time, the reli- dicular Pull Method)
ability requirements need to be established by agreement
between customer and supplier. 2.4.22 Bow and Twist
2.4.36 Rework Simulation, Plated-Through Holes
1.3 Definition of Terms The definition of all terms used 2.4.41.2 Coefficient of Thermal Expansion, Strain Gage
herein shall be as specified in IPC-T-50, except as other- Method
wise specified in Section 3.
2.5.7 Dielectric Withstanding Voltage, Printed Wiring
Material
1.4 Interpretation ‘‘Shall,’’ the imperative form of the
verb, is used throughout this specification whenever a 2.6.5 Physical (Mechanical) Shock, Multilayer Printed
requirement is intended to express a provision that is man- Wiring
datory. Deviation from a ‘‘shall’’ requirement may be con- 2.6.7.2 Thermal Shock-Rigid Printed Boards
sidered if sufficient data is supplied to justify the exception. 2.6.8 Thermal Stress, Plated-Through Holes
The words ‘‘should’’ and ‘‘may’’ are used whenever it is 2.6.9 Vibration, Rigid Printed Wiring
necessary to express non-mandatory provisions. ‘‘Will’’ is
used to express a declaration of purpose.’’ IPC-SM-785 Guidelines for Accelerated Reliability Testing
of Surface Mount Solder Attachments
To assist the reader, the word ‘‘shall’’ is presented in bold
characters. IPC-S-816 SMT Process Guideline and Checklist

1. www.ipc.org
2. Current and revised IPC Test Methods are available on the IPC website (www.ipc.org/html/testmethods.htm).

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 IPC-9701A February 2006

IPC-7711/21 Repair and Rework Guide cific product categories and environments. The more com-
plex the components or the assembly, the more testing may
IPC-9252 Guidelines and Requirements for Electrical
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be necessary to verify reliability.

Testing of Unpopulated Printed Boards
During use, surface mount solder attachments can be sub-
IPC-9501 PWB Assembly Process Simulation for Evalua- jected to a variety of loading conditions which can lead to
tion of Electronic Components premature failure. The underlying assumption is that the
solder joints have been properly wetted, forming a good
IPC-9502 PWB Assembly Soldering Process Guidelines metallurgical bond between the solder and the base metal
for Electronic Components of the component build and Printed Wiring (Circuit) Board
(PWB/PCB). This assures that early failures are not infant-
IPC-9504Assembly Process Simulation for Evaluation of
mortalities due to defective solder joints.
Non-IC Components (Preconditioning Non-IC Compo-
nents) The following load conditions could exist either singly,
sequentially or simultaneously and combine to be large
2.2 Joint Industry Standards1 enough to cause SMT solder joint failure:

J-STD-001 General Requirements for Soldering Electronic a) Differential thermal expansion.

Interconnections b) Vibration (transport).
c) Thermal shock (rapid temperature change causing tran-
J-STD-002 Solderability Tests for Component Leads, Ter- sient differential warpages) during cooling from solder-
minations, Lugs, Terminals and Wires ing operation or from severe use environments.
J-STD-003 Solderability Tests for Printed Boards d) Mechanical shock (high acceleration) from severe use
conditions or accidental misuse.
J-STD-020 Moisture-Induced Stress Sensitivity for Classi-
The reliability of a surface mount device mounted on a cir-
fication of Plastic Integrated Circuit Surface Mount cuit board is a function of solder attachment integrity and
Devices device/board interactions. Thermomechanical loading of
the package, imposed by the PWB through the soldered
2.3 International Tin Research Institute3
interconnects, may cause failures in other areas of the
ITRI Pub #580 Metallography of Tin and Tin Alloys package. The component-level testing in a socket does not
provide representative part-on-board loading. The
ITRI Pub #708 Metallurgy of Solder Joints in Electronics increased usage of non-wirebond die interconnects for
numerous CSP constructions and high lead count BGA
2.4 Other Publications packages may increase the likelihood of ‘‘unexpected’’
internal component failures during board-level testing.
2.4.1 Electronic Industries Association4
To ascertain that the solder attachment of surface mount
JESD22-A104-B ‘‘Temperature Cycling,’’ July 2000 circuit assemblies meet reliability expectations in the
intended use environments, it is often necessary to confirm
JESD22-B117 ‘‘BGA Ball Shear,’’ July 2000 the reliability for some specific applications even after
appropriate design for reliability (DfR) measures have been
2.4.2 OEM Working Group5 taken. Because of the time-dependent creep and stress
relaxation characteristics of solder, the fatigue damage and
SJR-01 Rev. 2 ‘‘Solder Joint Reliability Test Standard,’’
fatigue life in accelerated testing are not generally equiva-
February 2001
lent to those in operational use, but product reliability esti-
3 TERMS, DEFINITIONS AND CONCEPTS
mates can be obtained from accelerated test results through
the use of appropriate acceleration factors.
3.1 General To assure the reliability of the solder attach-
3.2 Reliability Concepts In the context of this document
ment of surface mounted electronic components to a circuit
board substrate requires the utilization of Design for Reli- it is important to have a working definition of reliability, as
ability (DfR)-procedures (see IPC-D-279), and in some well as good understanding of the physics-of-failure and
cases verification by testing to qualify a product for spe- statistical failure distribution.

3. www.itri.co.uk
4. www.eia.org
5. OEM Working Group. An informal working group of original equipment manufacturers (OEMs), Agilent Technologies, Cisco Systems, Dell, Hewlett-Packard,
IBM, Lucent Technologies, Nortel Networks and Sun Microsystems.

2
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 February 2006 IPC-9701A

3.2.1 Reliability Definition The ability of a product (sur- 3.3.4 Differential Thermal Expansion The difference in
face mount solder attachments) to function under given thermal expansion and contractions between materials
conditions and for a specified period of time without which occurs as a result of temperature changes encoun-
exceeding acceptable failure levels. tered during operational use or testing for reliability. Ther-
mal expansions or contractions are defined by the materi-
3.3 Physics-of-Failure Concepts
als’ coefficient of thermal expansion (CTE). Two (2) forms
3.3.1 Creep The time-dependent visco-plastic deforma- of differential thermal expansion are recognized:
tion as a function of applied stress and temperature. 1) The ‘‘global’’ thermal expansion mismatch, which is
the thermal expansion mismatch between components
3.3.2 Stress Relaxation The time-dependent visco- and substrates.
plastic deformation decreasing the stress by converting
2) The ‘‘local’’ thermal expansion mismatch, which is the
elastic strains into plastic strains for solder.
thermal expansion mismatch between the solder itself
3.3.3 Solder Creep-Fatigue Model Analytical models and the materials to which it is bonded.
based on empirical data that estimate the life of solder
joints subjected to cyclic creep-fatigue. The estimates of 3.4 Test Parameters Note: Any definition denoted with
reliability test results, product reliability, and the accelera- an asterisk (*) is a reprint of the term defined in JESD22-
tion factors in this document can be determined with the A104-B.
Engelmaier-Wild model (see IPC-D-279, Appendix A-3.1)
3.4.1 *Working Zone The volume in the chamber in
or some other suitable proven model.
which the temperature of the load is controlled within the
In the Engelmaier-Wild solder fatigue model a variable specified conditions.
fatigue ductility exponent defines the characteristic slope of
the curve which correlates fatigue life with the cyclic 3.4.2 Cyclic Temperature Range/Swing The difference
visco-plastic strain energy experienced by the solder. This between maximum and minimum temperatures incurred
exponent is empirically determined and is a function of during operational use or temperature cycling tests. See
time and temperature in contrast to the constant exponent Figure 3-1, Table 3-1 and Table 4-1.
used for the Coffin-Manson equation, which was developed
for non-creeping metals.

TEMPERATURE PROFILE
w/Tolerance

Ts (max) Nominal Ts (max)

Upper
Dwell Time
Temperature
∆T Cyclic Range

Ts

Lower
Dwell Time

Ts Nominal Ts (min.) Cycle Time

(min)
w/Tolerance

Time IPC-9701-3-1

Figure 3-1 Representative Temperature Profile for Thermal Cycle Test Conditions (Figure 3-1 based upon Figure 1,
Annex A of JESD22-A104-B)

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Table 3-1 Product Categories and Worst-Case Use Environments for Surface Mounted Electronics (For Reference Only)
4

IPC-9701A
Temperature, °C / °F(1) Worst-Case Use Environment
Product Category Tmin(2) Tmax(2) ∆T(3) tD(4) Typical years Approx. Accept.
(Typical Application) Storage Operation °C / °F °C / °F °C / °F hrs Cycles/year of Service Failure Risk, %
Consumer -40/85 0/55 0/32 60/140 35/63 12 365 1-3 1
Computers and Peripherals -40/85 0/55 0/32 60/140 20/36 2 1460 5 0.1
Telecomm -40/85 -40/85 -40/-40 85/185 35/63 12 365 7-20 0.01
Commercial Aircraft -40/85 -40/85 -55/-67 95/203 20/36 12 365 20 0.001
Industrial and Automotive - -55/150 -40/85 -55/-67 95/203 20/36 12 185 10-15 0.1
Passenger Compartment &40/72 12 100
&60/108 12 60
&80/144 12 20
Military -40/85 -40/85 -55/-67 95/203 40/72 12 100 10-20 0.1
(ground and shipboard) &60/108 12 265
Space -40/85 -40/85 3/5.4
to 100/180
leo -55/-67 95/203 1 8760 5-30 0.001
geo 12 365

Not for Resale

Military Aircraft -55/125 -40/85
a -55/-67 125/257 40/72 2 100 10-20 0.01
b 60/108 2 100
c 80/144 2 65
Maintenance
&20/36 1 120
Automotive -55/150 -40/125 -55/-67 125/257 60/108 1 1000 10-15 0.1
(under hood) &100/180 1 300
&140/252 2 40
& = in addition
1. All categories may be exposed to a process temperature range of 18°C to 260°C [64.4°F to 500°F].
2. Tmin and Tmax are the operational (test) minimum and maximum temperatures, respectively, and do not determine the maximum ∆T.
3. ∆T represents the maximum temperature swing, but does not include power dissipation effects; for power dissipation calculate ∆T; power dissipation can make pure temperature cycling accelerated testing
significantly inaccurate. It should be noted that the temperature range, ∆T, is not the difference between Tmin and Tmax ; ∆T is typically significantly less.
4. The dwell time, tD, is the time available for the creep of the solder joints during each temperature half-cycle.

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 February 2006 IPC-9701A

3.4.3 *Sample Temperature: Ts The temperature of the ear portion of the profile curve, which is generally the
samples during temperature cycling, as measured by ther- range between 10% and 90% of a specific test condition
mocouples, or equivalent temperature measurement appara- temperature range. Note: Ramp rate can be load dependent
tus, affixed to, or imbedded in, their bodies. The thermo- and should be verified for the load being tested.
couple or equivalent temperature measurement apparatus
used in the attachment method should ensure that the entire 3.4.14 Maximum Cyclic Strain Range The range of total
mass of the sample(s) is reaching the temperature extremes strain experienced during exposure to cyclically induced
and the dwell/soak requirements. thermal or mechanical deformations.

3.4.15 Maximum Cyclic Stress Range The range of

3.4.4 *Maximum Sample Temperature: Ts(max) The
total stress experienced during exposure to cyclically
maximum measured temperature experienced by the
induced thermal or mechanical deformations. For solder in
sample(s).
the temperature range where creep takes place, the stress
range and the strain range are independent of each other
3.4.5 Maximum Nominal Temperature: T(max) The
(this is in contrast to noncreeping metals for which the
maximum nominal temperature for a specific test condition
stress-strain curve defines unique correspondences between
is the required temperature Ts(max) of the sample; see
stress and strain) since there is a different stress-strain
Table 4-1.
curve for each temperature and strain-rate. The modulus
and yield strength are temperature- and strain-rate-
3.4.6 *Minimum Sample Temperature: Ts(min) The
dependent, and the maximum stress experienced by the
minimum measured temperature experienced by the
solder joints is strongly dependent on the compliancy of
sample(s).
the attached structures, e.g., compliant leads.
3.4.7 Minimum Nominal Temperature: T(min) The 3.4.16 Hysteresis Loop This loop diagrams the stress-
minimum nominal temperature for a specific test condition strain behavior of solder attachments obtained during a
is the required temperature Ts(min) of the sample; see loading cycle. The area of the hysteresis loop defines the
Table 4-1. visco-plastic strain energy per cycle, and is a measure of
the fatigue damage per cycle. The size of the hysteresis
3.4.8 Mean Cyclic Temperature, TSJ The mean of the loop depends on the strain range, stress range, the cyclic
maximum nominal temperature and the minimum nominal dwell time, and to a lesser extent on the mean cyclic tem-
temperature; see Equation 4, Appendix A. perature.

3.4.9 Nominal ∆T The difference between nominal 3.4.17 Design Service Life The required duration of
T(max) and nominal T(min) for a specific test condition; operational life of a piece of equipment that remains fully
see Table 3-1. functional while exposed to the expected environment.

3.4.10 Dwell/Soak Time, tD The total time the sample 3.4.18 Projected Service Life Service Life predicted by
temperature is within a specified range of each nominal a model using accelerated test results which relates the
T(max) and T(min) (see Table 4-1). The dwell time is of number of fatigue cycles to a given acceptable cumulative
particular importance for accelerated tests, since during failure probability.
accelerated testing the creep process is substantially incom-
3.4.19 Infant Mortality Failures Failures during environ-
plete. The dwell allows for a correction of the effect of the
mental stress screening (ESS), burn-in, initial functional
incomplete creep process relative to the product use tem-
testing, and/or early in service occur primarily as a result
perature cycles which are typically long enough to allow
of inadequate quality and/or manufacturing processes.
the creep process to be complete at every cycle dwell.
3.4.20 Random Steady-State Failures This is a period
3.4.11 Dwell/Soak Temperature The temperature that is of useful operation life during which failures occur seem-
above T(max) for the upper end of the cycle and is below ingly at random or at a low rate, weakly related to product
T(min) for the lower end of the cycle. See Table 4-1. complexity. For solder attachments, this period is not mea-
surable because it may not exist or have very low failure
3.4.12 Cycle Time Time for one complete temperature rates.
cycle. See Figure 3-1.
3.4.21 Wearout Failures Wearout is defined as the pro-
3.4.13 *Temperature Ramp Rate The rate of tempera- cess where damage accumulates over time and where the
ture increase or decrease per unit of time for the sample(s). occurrences of failures rise steadily as the product deterio-
The temperature ramp rate should be measured for the lin- rates due to fatigue, or another wear-out mechanism. It is
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the wear-out failures due to creep-fatigue of the solder The maximum temperature for thermal cycling should be
attachments which are the subject of this document. 25°C [45°F] below the glass transition temperature (Tg) of
the printed circuit board material.
3.5 Statistical Failure Distribution Concepts
It must be noted that temperature cycles that extend below
3.5.1 Statistical Failure Distribution Failures, in par- -20°C [-4°F] or above 110°C [230°F] or include both cold
ticular due to wear-out, do not occur all at once, but are and hot temperatures (for near-eutectic Sn-Pb solders) may
distributed over time. The Weibull statistical distribution is subject the solder attachment to more than one damage
the most suitable statistical distribution used for wear-out mechanism. These mechanisms tend to accelerate each
failures; however, occasionally the Log-Normal distribu- other and thus can lead to earlier failures; furthermore,
tion is used also. For the Weibull distribution two (2) defin- because of the confounding of multiple damage mecha-
ing parameters are required: (1) the Weibull slope (a mea- nisms, extrapolation of test results from such environments
sure of the degree of spread of the distribution), and (2) must be undertaken with a recognition of this fact.
some intercept value (typically N(63.2%)—the characteris-
3.6.3 Thermal Shock Thermal shock occurs when an
tic life of the Weibull distribution, but sometimes
assembly is exposed to rapid changes of temperature caus-
N(50%)—the mean fatigue life. On Weibull distribution
ing transient temperature gradients, warpages, and stresses
graph paper, using the two defining parameters, measured
within the part and/or assembly. The rate of temperature
data will plot as a straight line, frequently simplifying data
change for thermal shock is usually greater than 20°C
analysis.
[36°F]/minute.
3.5.2 Mean Fatigue Life, N(50%) The amount of time at
3.6.4 Power Cycling Power cycling may more accu-
which one-half of a given sample has failed.
rately replicate field use conditions than temperature cycle
testing for electronic devices that are frequently turned
3.5.3 Failure Free Life, N0 The amount of time (or num-
on/off.
ber of cycles) prior to the first failure (This parameter is
used in a 3-parameter (3-P) Weibull statistical distribution.) 3.7 Other Tests

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3.5.4 Cumulative Failure Percentage During testing, 3.7.1 Burn-In Test This test takes finished product and
the cumulative failure percentage of a sample i is calcu- routinely subjects it to normal, perhaps worst-case but still
lated by using F (i) = i/(n + 1) where i is the sample rank- realistic, operational environments. The burn-in test is not
ing. an accelerated reliability test.

3.5.5 Cumulative Failure Probability For design pur- 3.7.2 Environmental Stress Screening (ESS) This
poses the required reliability is typically given as a screening procedure employs environmentally generated
‘‘Cumulative Failure Probability’’ not to be exceeded in a stresses to cause overstressing of ‘‘weak’’ elements of an
given design life. assembly to the point of failure. It is intended to prevent
these latent defects from reaching field service and possi-
3.5.6 Acceptable Cumulative Failure Probability The bly causing field failures. The environments producing
maximum allowable percentage of defectives/failures at the these stresses may or may not be related to environmental
end of the service life. conditions experienced by the product during service. Once
having failed, the elements can be detected and either
3.6 Reliability Tests repaired, replaced, or discarded, and perhaps redesigned for
future product. ESS needs to be accomplished without sig-
3.6.1 Accelerated Reliability Test A test in which the nificant damage to the ‘‘normal’’ elements of the assembly.
damage mechanism(s) of concern for operational use is ESS is not an accelerated reliability test.
(are) accelerated to cause failures in less time than in ser-
vice. The test acceleration results from shorter cycle peri- 3.7.3 Highly Accelerated Stress Testing (HAST) This
ods and/or more severe loading conditions; however, the stress test is used to simulate corrosion related failure
introduction of extraneous damage mechanisms must be mechanisms under electrical bias while being subjected to
avoided. The service life can be estimated by application of an accelerated stress combination of temperature and
appropriate acceleration factors. humidity. HAST may be used in the context of components
and assemblies, but it is not an accelerated reliability test
3.6.2 Thermal Cycling Exposure of assemblies to cyclic for solder attachments.
temperature changes where the rate of temperature change
is slow enough to avoid thermal shock (typically less than 3.7.4 Mechanical Shock Mechanical shock is defined as
or equal to 20°C [36°F]/min). a rapid transfer of mechanical energy to a system that

6
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 February 2006 IPC-9701A

results in a significant change in stress, velocity, accelera- 4 PERFORMANCE TEST METHODS

tion, or displacement within a system. Standardized accelerated reliability test methods are pre-
ferred as data results can be correlated to form benchmark
3.7.5 Vibration Vibration in assemblies is defined as reliability bases. IPC-SM-785 provides a technical basis for
periodic or random motion in alternately opposite direc- designing and implementing accelerated reliability testing.
tions from the position of equilibrium. The application load The use of this document in conjunction with IPC-SM-785
typically is below the yield point (elastic) of materials. is highly recommended as this document provides an
understanding of the physics of SMT solder joint failure,
3.7.6 Process Qualification This is a special test or set that is, the various mechanisms which contribute to solder
of tests which validates a process used to manufacture joint fatigue. In addition to formulating failure mecha-
product that meets performance specifications. nisms, this document provides technical information based
upon empirical studies from which an accelerated test pro-
3.7.7 Process Verification A periodic evaluation of a gram can be derived. Appropriate caveats and disclaimers
process used to ensure process optimization or eliminate are given in IPC-SM-785.
process deviations. Since the fatigue life of SMT solder joints are far in excess
of the usual schedule spans for design and development of
3.8 Evaluation and Application Considerations Table electronic boxes, accelerated testing is a necessity for
3-1 shows common storage and operation environments as qualification purposes when equipment operational life is a
well as the worst-case use environmental conditions for the requirement. This document, IPC-9701, provides guidance
nine most common product categories. This table should be and methods for devising accelerated life tests for equip-
used for reference only. ment qualification purposes. Although accelerated life tests
are frequently agreed to between customer and suppliers,
3.9 Understanding of Solder Attachment Technology the use of this document, with minor modifications as
Solder is unique among engineering metals due to its tem- needed, will lead to standardization for life testing. Conse-
perature, time and stress dependent behavior for typical use quently, the test methods and requirements contained
conditions. For instance, eutectic tin-lead solder readily herein may not be technically rigorous. However, contin-
creeps and stress relaxes above 20°C [68°F], whereas ued usage and the accumulation of data will lead to a reli-
below -20°C [-4°F] solder has long-term load bearing able database.
capabilities similar to other metals. The higher the tempera-
ture above 20°C [68°F] and/or the higher the stress level, 4.1 General Requirements Table 4-1 lists both man-
the faster the solder will creep and stress relax. dated and preferred test parameters. Mandated parameters
An understanding of the reliability and failure mechanisms should be followed without any deviation. Complying with
for a given surface mount attachment technology is the first all mandated requirements insures acceptance of the tests
step toward designing and assuring product reliability. For and their results by the industry; deviation from a particu-
this, a generic database is required. Although failure lar mandated parameter may be acceptable to an individual
mechanisms based on monotonic overstressing can occur, customer but ultimately jeopardizes the acceptance of the
the most common reliability threat comes from stress- supplier’s results by the industry. For multiple parameters,
relaxation based fatigue damage. A desirable fatigue failure preferred reference test parameters are recommended to be
database is one that is based upon a combination of low used for an even wider-industry compatibility and accep-
acceleration and high acceleration tests. For near-eutectic tance. Preferred parameters should be followed unless the
Sn-Pb solders such databases exist, however they do not supplier can substantiate that their proposed deviation is
currently exist for other alloys, in particular Pb-free sol- expected to enhance board-level reliability of the specific
ders. package.

In this context, low acceleration tests produce mean-times- 4.2 Test Vehicles Proper design and assembly of the test
to-failure of the test vehicles that are about 10 to 20 times vehicles (TVs) are critical to assure that valid and appro-
shorter than actual life in field use. High acceleration tests priate data are obtained.
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are about 100 to 500 times shorter. The higher the test
acceleration, the less the test results are representative of
4.2.1 Component Description This document assumes a
performance at field conditions.
surface mount (SMT) component to be one that is attached
Thus, low acceleration tests should closely mimic expected onto a circuit board with a solder alloy using conventional
field conditions, whereas high acceleration test are often reflow technologies. Ball Grid Array (BGA), Small Outline
necessitated by the reality of the time and resources Package (SOP) and Chip Scale Package (CSP) are some
required for the low acceleration testing. typical component examples.

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 IPC-9701A February 2006

Table 4-1 Temperature Cycling Requirements, Mandated and Preferred Test Parameters Within Mandated Conditions
Test Condition Mandated Condition
Cycle (TC) Condition:
TC1 0°C ←→ +100°C (Preferred Reference)
TC2 -25°C ←→ +100°C
TC3 -40°C ←→ +125°C
TC4 -55°C ←→ +125°C
TC5 -55°C ←→ 100°
Test Duration Whichever condition occurs FIRST:
50% (Preferred 63.2%) cumulative failure
(Preferred Reference Test Duration)
or
Number of Thermal Cycle (NTC) Requirement:
NTC-A 200 cycles
NTC-B 500 cycles
NTC-C 1,000 cycles (Preferred for TC2, TC3,and TC4)
NTC-D 3,000 cycles
NTC-E 6,000 cycles (Preferred Reference TC1)
Low Temperature Dwell 10 minutes
Temperature Tolerance (preferred) +0/-10°C (+0/-5°C) [+0/-18°F (+0/-9°F)]
High Temperature Dwell 10 minutes
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Temperature Tolerance (preferred) +10/-0°C (+5/-0°C) [+18/-0°F(+9/-0°F)]

Temperature Ramp Rate ≤20°C [36°F]/minute
Full Production Sample Size 33 component samples
(32 test samples plus one for cross-section,
add additional 10 samples for rework, if applicable)
Printed Wiring (Circuit) Board (PWB/PCB) Thickness 2.35 mm [0.093 in]
Package/Die Condition Daisy-Chain Die/Package (see Table 4-2)
Test Monitoring Continuous Monitoring (see Table 4-4,
Preferred Reference-Event Detector)

This qualification and requirements standard will address 4.2.1.1 Daisy-Chain Die/Package The TV component
solder joint reliability and the thermomechanical package and die should be representative of the production
component/board interactions while other board level ther- component. This means:
mal cycling interactions, i.e., delaminations, via cracks,
dielectric cracks, etc., are more appropriately addressed in 1. The TV component layout, construction and materials
component qualification standards. are mandated to be representative of a typical produc-
tion component, including the die attach adhesive and
The default condition of this standard mandates the use of process, underfill and process, wire bond/flip chip, etc.
a daisy-chain die to assure that the reliability of solder
balls, package materials, and die-level interconnect are all 2. The die for the TV component is daisy-chained when
characterized during board-level temperature cycling. applicable (see Table 4-2). The test device must use
Exemptions to the daisy-chain die requirement are listed in package materials and dimensions representative of pro-
Table 4-2. Specific parameters on the exemption are given duction components, and must connect to the external
in Table 4-3. Mechanical die, when permitted, should rep- leads/balls/pads using the same die interconnects, trace
licate an actual die with regard to dimensions and die-level geometries, via constructions, layer counts, etc., as in
interconnect but are required to include daisy-chain pairs or the production component. To reduce further test
active silicon circuitry. expenses, the daisy-chain die should match the maxi-
mum die size anticipated for the component in produc-
Table 4-2 Daisy Chain Requirements
tion use.
Exemption Category Mandated Condition
Full Product Characterization Daisy-Chain Die For plastic BGA/CSP, the solder balls underneath the die
(Default) are often the first to fail in board-level temperature cycling;
Exemption Category A Daisy-Chain Package consequently, daisy-chain coverage of this region must be
(see Table 4-3) Substrate & Mechanical Die included, even if the solder balls are exclusively ground
(Preferred Daisy-Chain Die)
and/or power. For ceramic components, corner balls fail
Ceramic Package (Substrate Daisy-Chain Package
>1 mm [0.040 in] thick with Substrate (Preferred
early and should be considered critical. Daisy-chain cover-
an average modulus of Daisy-Chain) age for power/ground solder balls distributed within a
240-270 GPa) peripheral BGA/CSP solder ball matrix are not required;

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Table 4-3 Test Exemption Requirements –

A: Use of mechanical die rather than daisy-chain PQ 9701, previously qualified per IPC 9701
If [New] device does not meet requirements listed below for exempt A Category, then the default Full Product Characterization applies.
Description EXEMPT Exemption Category A
Package body size [NEW] ≤110% [PQ 9701] [NEW] ≤120% [PQ 9701]
Die* dimensions [NEW] ≤110% [PQ 9701] [NEW] ≤120% [PQ 9701]
Solder ball diameter, if applicable [NEW] ≥90% [PQ 9701] [NEW] ≥80% [PQ 9701]
Wetted solder pad diameter, if applicable [NEW] ≥90% [PQ 9701] [NEW] ≥80% [PQ 9701]
Solder ball pitch or lead pitch [NEW] ≥90% [PQ 9701] [NEW] ≥80% [PQ 9701]
Solder ball stand-off or lead stand-off [NEW] ≥90% [PQ 9701] [NEW] ≥80% [PQ 9701]
Substrate thickness [NEW] = [PQ 9701] ± 20% [NEW] = [PQ 9701] ± 40%
Stiffener and/or heat spreader dimensions, if applicable [NEW] = [PQ 9701] ± 20% [NEW] = [PQ 9701] ± 40%
Epoxy/encapsulant dimensions [NEW] = [PQ 9701] ± 20% [NEW] = [PQ 9701] ± 40%
Die attach* dimensions, if applicable [NEW] = [PQ 9701] ± 20% [NEW] = [PQ 9701] ± 40%
Underfill* material dimensions, if applicable [NEW] = [PQ 9701] ± 20% [NEW] = [PQ 9701] ± 40%
Organic material critical properties (modulus, CTE, ultimate strength, [NEW] = [PQ 9701] ± 20% [NEW] = [PQ 9701] ± 20%
etc.)
Organic material suppliers (substrate, die attach*, mold epoxy, [NEW] = [PQ 9701] [NEW] = [PQ 9701]
encapsulant, underfill*, etc.)
Lead material composition and lead base metallization [NEW] = [PQ 9701] [NEW] = [PQ 9701]
Stiffener and/or heat spreader materials, if applicable [NEW] = [PQ 9701] [NEW] = [PQ 9701]
Solder ball land pad type (SMD, NSMD, etc), if applicable [NEW] = [PQ 9701] [NEW] = [PQ 9701]
Ball array layouts (full matrix vs. depopulated), if applicable [NEW] = [PQ 9701] [NEW] = [PQ 9701]
Numerical/analytical modeling completed for [NEW] device ** Mandated Preferred
* Not applicable for ceramic substrates ≥1 mm thick with an average modulus in the range of 240 to 270 GPa and with no lid attached.
** Analytical techniques must be validated by comparison of predictions to experimentally obtained solder joint reliability data for [PQ9701] device. Critical
property data (modulus, CTE, ultimate strength, etc.) for organic materials must be experimentally obtained.
[NEW] = New device
[PQ 9701] = Device that test data complied with Full Product Characterization requirements of IPC-9701

however, dasiy-chain stitch patterns must provide some packages, 10 solder balls each. Perform shear by applying
level of coverage for all device rows and/or critical regions. a force against the edge of the BGA/CSP parallel to the
plane of the substrate. The height of shearing tool should
Designs in which a single continuous daisy chain is moni-
make a gap with the chip surface of 50 µm [0.002 in]
tored for each package will be considered acceptable. It is,
minimum. Shear test at nominal speed of 500 µm/sec
however, preferable that multiple nets be monitored inde-
[0.020 in/sec] is preferred. The failure mode for the
pendently on each part, and that these nets be designed to
sheared balls shall be either bulk solder failure or copper
provide additional information on the region(s) of first
pad lift-off, an intermetallic failure is unacceptable. Shear
failure.
testing at much higher speed is recommended to determine
An example for a BGA/CSP, using four - five nets per the effect of shear speed on shear strength and failure
package might include isolation of failures as follows: mechanisms. See JESD22-B117 BGA Ball Shear Test.
(a) The package corner solder attachments.
(b) The outer rows of solder attachments. 4.2.1.3 Component Documentation Requirements The
following covers all requirements for component documen-
(c) Solder attachments under or nearly under the die perim-
tation:
eter.
1. Package outline drawing or reference to JEDEC6 out-
(d) Central package solder attachments, if present.
line.
For Daisy-Chain Net, the known high failure risk regions 2. Internal die dimensions (LxWxH) and orientation (if
should be on separate daisy-chain nets than those of known die is not square).
low failure locations.
3. Package daisy-chain connection map and/or net list
4.2.1.2 Solder Ball Shear Test Perform solder ball (electronic files preferred).
shear test, if applicable. The minimum shear force is 4. Measured solder ball/lead coplanarity (seating plane
defined as the mean minus 3 sigma, for a minimum of three method or best fit place).

6. www.jedec.org
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5. Solder ball shear values or lead pull test, if applicable, 4.2.2.1 Test Board Design Requirements The follow-
and failure modes for parts from same production lot ing include all requirements necessary for test board
as tested devices. Pull test is optional. design:
6. Measured x and y CTE by micro-Moiré interferometry 1. For PWBs, preference is given to the 2.35 mm [0.093
data, preferred for area array packages, for parts from in] thick PWBs with a minimum of six copper layers;
same production lot as tested devices. Other tech- for thicker or thinner PWBs, the number of layers
niques such as TMA are also acceptable where appro- should be proportionally increased or decreased,
priate for the determination of effective CTEs. respectively.
7. Solder-wetted pad dimensions, if applicable. 2. For package body sizes larger than 40 mm [1.57 in],
8. Solder ball land pad type, if applicable (solder mask the use of 3.15 mm [0.125 in] thick PWB with a mini-
defined (SMD) with coverage of mask on pad, non- mum of eight copper layers is preferred.
solder mask defined (NSMD) with a gap between 3. The PWB TV is preferred to have the same material
mask and pad, or via-in-pad). and layup as the product PWB; however in all cases
9. Lead finish/pad metallization construction, including the measurement of the glass transition temperature,
thicknesses of all layers and composition of solder, if Tg, as well as the CTE in both x and y planar direc-
applicable. tions is mandated.
10. Illustration showing daisy-chain interconnection path, 4. Representative power/ground planes in even internal
if applicable, from die to lead. layers (total PWB layer count is even) is mandated to
11. Die-to-lead interconnection table (electronic file pre- have nominal 70% Cu coverage.
ferred). 5. Representative signal traces in odd internal layers
4.2.2 Printed Wiring (Circuit) Boards PWB/PCB lay-up, (total PWB layer count is even) is mandated to have
thickness, and pad design can affect solder attachment nominal 40% Cu coverage.
integrity. The nominal mandated reference PWB thickness 6. Daisy-chain nets are preferred to be in outer layers
shall be 2.35 mm [0.093 in] (see Table 4-1). Two PWB only.
thicknesses are preferred to be used for the first qualifica- 7. The trace routing is preferred to be isolated such that a
tion of a package family to aid analytical extrapolation of device can be cut away w/o compromising other
empirical test results for application. The additional PWB devices on the board. Additional reference traces
thickness may vary and can have thickness values lower should be placed by design close to pads to be used
and/or higher depending on the user application. only during solder paste height measurement by auto-
In addition to the PWB TV layer construction recom- matic visual systems such as a 3D laser. These traces
mended below, it is important to design with an even num- are needed since the visual system requires a reference
ber of layers, resulting in a symmetrical cross section. This to pad surface which is covered by solder paste.
symmetry also applies to signal layers. This is necessary 8. Although daisy-chain nets will typically not require
since copper and epoxy/glass have different coefficients of PWB TV vias, the PWB TV is mandated to contain
thermal expansion and the PWB would warp during pro- vias at a minimum of 50% of the land pad sites to
cessing if not symmetrical. approximate mechanical effect of vias on product
It is recommended that standard PWB design methodology PWBs.
be used to design the daisy-chain test boards. This should 9. OSP (Organic Solderability Preservative) surface finish
include defining the package(s) to be tested in a component is preferred. HASL (Hot Air Solder Levelling) is
library along with any connectors (if they are used), incor- optional.
porating the daisy-chain interconnectivity for all packages
10. NSMD (Non-Solder Mask Defined) is mandated if
used into the component definitions, and by creating an
applicable.
actual schematic for the test board. By doing this the test
board can be designed using the standard design flow 11. The PWB pad diameter for solder ball attachment is
methodology which is used for a product PWB. preferred to be 80% - 100% of the component solder-
wetted pad diameter.
This design flow typically includes both interactive tools
12. Multiple probe pads are required for each daisy chain
and design checks which insure that all nets are connected.
net to ease failure analysis.
Doing the above greatly increases the odds of a good first
time PWB TV design. Conversely, assuming that this is a 13. Nominal outer layer copper thickness is preferred to be
‘‘simple’’ test board and designing on a CAD system that 35 µm [137.8 µin].
does not check for the correct electrical connection of all 14. Minimum outer layer trace width is preferred to be 150
parts greatly increases the odds of failure. µm [590.6 µin].
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15. Minimum of 5 mm [0.2 in] clearance, plus routing 4.2.3 Board Assembly For many applications, SMT
space for failed package removal, if applicable, devices are assembled onto circuit boards using not only
between package body and adjacent packages, connec- mass-reflow conveyor furnaces, but also using hot gas
tors or board edge is required. rework stations. Consequently, it is preferred that daisy-
16. For solder mask registration, no overlap on surface chain devices are assembled onto the test boards using both
mount pads is allowed. No solder mask allowed on reflow methods. The term rework applies to the reflow
NSMD pads. operation using rework equipment and not to the re-use of
any devices. The devices for rework shall be virgin, iden-
17. For board warpage, it is required that the PWB tical to the mass-reflow assembled devices.
warpage is within the values defined by industry stan-
dards such as IPC-2221, IPC-6012 and IPC-A-600. Moisture absorption of the daisy-chain components prior to
These standards refer to PWB warpage as ‘‘bow and either the mass reflow or rework assembly process could
twist.’’ result in delamination at various package interfaces. Sev-
eral studies have also demonstrated that a multiplicity of
18. Components anticipated for use in mirror-sided (dual-
board assembly parameters affect not only the yield, but the
sided) board assemblies are mandated to be tested in a
reliability of solder attachments. Consequently, it is critical
mirror-sided board configuration.
that the documentation accompanying solder attachment
19. Silkscreen nomenclature or Cu etch, including but not reliability test results include the test board assembly docu-
limited to, legends which clearly label all components mentation listed below.
on the test board and all test points, and location of pin
1 for correct package on board assemly, is mandated An adhesively or mechanically attached heatsink can affect
for ease in assembly, ATC and FA. solder attachment reliability and may need to be evaluated
in application-specific testing, separate from this standard.

4.2.2.2 Test Board, Daisy-Chain Design The combina- 4.2.3.1 Board Assembly Requirements Board Assem-
tion of daisy-chain links on the component and those on bly Location Process parameters must be optimized prior to
assembly. Optimization process parameter examples
the PWB TV should result in a completed daisy-chain net
include solder volume, paste registration, printing speed,
after assembly. It is preferred that the daisy-chain trace-
squeegee pressure, stencil snap off, thermal profile, etc.
links be placed on the top PWB layer, wherever possible.
This is to avoid missinterpretation of daisy-chain failures Component Bake-Out Prior to Board Assembly Production
due to via failure. It is highly recommended that acceler- storage/bake-out procedures, if available, should be used.
ated testing be performed on bare PWB prior to assembly
If a qualified moisture resistance level or bake-out specifi-
to assure quality and to minimize the likelihood of via fail- cation is not finalized for the device, then a default bake-
ure during board-level testing. out of 24 hours at 125°C [257°F] is required.
It is mandated that component/PWB daisy-chains be moni- Board Assembly Bake-Out Prior to Rework Processing
tored continuously. However, it is preferred that multiple Production storage/bake-out procedures, if available,
manual probe pads be located within each daisy-chain net should be used.
--`,,```,,,,````-`-`,,`,,`,`,,`---

to ease fault isolation. The use of multiple jumper locations

If a qualified moisture resistance level or bake-out specifi-
within each daisy-chain net can enable continued testing of
cation is not finalized for the PWB, then a default board
the device for additional failure locations.
bake-out of 24 hours at 105°C [221°F] is required.
Assembly Inspection X-Ray of all solder attachments shall
4.2.2.3 Test Board Documentation Requirements The
be performed after assembly to identify solder attachment
following cover all requirements for documentation of test
defects. Defects to be identified include: solder bridge, sol-
boards:
der open, missing solder contacts, large number of voids,
1. PWB Lay-Up. solder ball misalignment and lack of fillets. Assemblies
2. Dielectric material. with gross defects must not be included in reliability evalu-
3. Internal trace, plane and via geometries, preferred. ation. Manufacturing processes optimization is recom-
mended to be repeated if multiple gross defects are
4. External geometries.
detected.
5. Plating finish.
All assemblies must be tested for electrical continuity. Any
6. Measured x/y-CTE (coefficient of thermal expansion),
open, short, or abnormality in initial daisy-chain resistance
TMA or Moiré interferometry, preferred.
is not acceptable. Samples with any open, short, and/or
7. Measured glass transition temperature, Tg. abnormality in initial resistance should not be monitored in
8. Test board orientation in thermal chamber. ATC.

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4.2.3.2 Test Board Assembly Documentation The fol- 4.3.2.2 *Test Procedure Sample(s) shall be placed in a
lowing represent the requirements for proper documenta- position with respect to the air stream such that there is
tion of the test board assembly: substantially no obstruction to the flow of air across and
1. Reflow temperature characterization including pre-heat around each sample(s). When special mounting is required,
temperature, ramp rate, critical peak temperatures (sol- it shall be specified. The sample shall then be subjected to
der, package surface, board, etc.), duration above solder the specified temperature cycling test condition for the
liquidus temperature and cooling rate. Include reflow specified number of cycles. Completion of the total number
atmosphere and thermocouple locations and attachment of cycles specified for the test may be interrupted for test
configurations. chamber loading or unloading of device lots, manual veri-
fication of interruptions or as the result of power or equip-
2. Solder composition and solder paste metal percentage,
ment failure. However, the number of interruptions shall
particle mesh size and flux type.
be minimized. If the thermocouple is affixed to the sample
3. Nominal solder paste volume. body, the amount of glue or tape used shall be minimized
4. Nominal solder attachment standoff. to insure proper temperature measurements. The thermo-
5. Nominal ball diameter or fillet shape, preferably by couple, or equivalent temperature measurement apparatus,
diagonal cross-section and/or x-ray laminography. attachment method used should ensure that the entire mass
of the sample(s) reaches the temperature extremes and the
6. Number of rework operations completed (default = one)
dwell/soak requirements.
at each test board rework site.
When testing interconnections for solder joint fatigue, it is
4.3 Accelerated Temperature Test Methods important to avoid transient thermal gradients in the
samples on test. Samples with large thermal mass and low
4.3.1 Preconditioning by Isothermal Aging Select non- heat transfer efficiency require ramp rates slow enough to
commercial customers prefer that test vehicles, following compensate for the thermal mass. The temperature of the
board assembly, should be subjected to an accelerated ther- sample should be within a few degrees of the chamber
mal aging (e.g., 24 hours at 100°C [212°F] {(-0/+5°C), ambient temperature during the temperature ramps. For
(-0/+9°F)}) in air to simulate a reasonable use period and samples of large thermal mass, use of a single zone cham-
to accelerate such possible processes as solder grain ber may be required to achieve the mandated ramp rate.
growth, intermetallic compound growth, and oxidation.
The following conditions are mandated or preferred as
Storing the test vehicles after this artificial aging for some
described below:
additional time at room temperature before commencing
with the fatigue testing serves to further stabilize the solder a) Preferred single zone chamber with air in which
structure. assembled boards are vertically oriented and are paral-
lel to air flow are preferred.
4.3.2 Temperature Cycling Note: Paragraphs denoted b) Board temperature measurements preferred to be made
with an asterisk (*) are reprints of text taken from JESD22- at six boards at different chamber locations, two within
A104-B. the center area of the chamber and four toward the
perimeter.
4.3.2.1 *Temperature Chambers The chamber(s) used c) Dwell time at each end of the temperature limit, heat up
shall be capable of providing and controlling the specified and cool down rates (ramp rates) as listed in Table 4-1.
temperatures and cycle timing in the working zone(s), Use the average of thermocouples on boards for the
when the chamber is loaded with a maximum load. Direct ramp rates calculation. Ramp rate should be measured
heat conduction to sample(s) shall be minimized. The between the maximum low temperature soak limit, and
capability of each chamber achieving the sample tempera- the minimum high temperature soak limit.
ture requirements shall be verified across each chamber by
4.3.3 Test Monitoring
one or both of the following methods:
(a) Periodic calibration using instrumented parts and a 4.3.3.1 Temperature Monitoring The temperature moni-
maximum load, and continual monitoring during each toring requirements are given in Table 4-4.
test of such fixed tool thermocouple temperature mea- 4.3.3.2 Electrical Daisy-Chain Monitoring The electri-
surement(s) as adequate to ensure run-to-run repeatabil- cal daisy-chain monitoring requirements are given in Table
ity. 4-4. Continuous electrical monitoring mandated to be per-
(b) Continual monitoring during each test of an instru- formed by an event detector and/or data logger, though the
mented part or parts placed at worst-case temperature event detector technique is the preferred reference test.
locations (for example, this may be the corners and Manual read points are not an acceptable alternative to
middle of the load). continuous monitoring.
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Table 4-4 Test Monitoring Requirements

Test Parameter Mandated Condition
Temperature (Chamber Characterization) Component temperature to be monitored and recorded at each board location in
chamber during initial chamber set-up. Characterization study should be performed
using representative sample loads, test board configurations and fixturing.
Temperature (Chamber Test Operation) Continuous component temperature monitoring of at least two devices, total, on two
test boards (chamber center and perimeter), as well as chamber ambient.
Electrical (High and Low Temperatures) Continuous intermittent event monitoring (preferred reference)

OR

Continuous electrical resistance monitoring (maximum scan interval of all chains =

one minute). Manual monitoring is not allowed.
Failure Definition Event detector: 1000 Ω, 10 events (maximum), 1 micro-second duration (maximum),
report first verified as time-to-failure

AND/OR

Data logger/Voltmeter: 20% nominal resistance increase (maximum), five readings/

scans (maximum)

Solder joint fractures almost always electrically manifest 5 QUALIFICATION REQUIREMENTS

themselves as very short-duration opens or high-resistance
connections. The primary advantage in an event detector is 5.1 Thermal Cycling Ranges The thermal cycling
the ability to capture these intermittent high-resistance requirements are given in Table 4-1. The thermal cycling
events, which typically precede a measurable resistance requirement for any product should be determined by the
increase, shortly after the full fracture of a solder joint user or customer to meet specific environmental opera-
occurs. The most significant disadvantages of an event tional conditions of the product. Preferred reference should
detector are false failure indications due to minor electrical be given to temperature cycle condition TC1 (0°C [32°F]
noise in the test apparatus, cabling and/or connectors. A to 100°C [212°F]) and test duration NTC-E (6,000 cycles)
data logger detects and records resistance changes. Using a for acceptance of test results by a wider industry sector.
data logger to scan interval durations of less than one
minute is mandated. Regardless of the continuous monitor- The thermal cycling requirements are given in Table 4-1.
ing method, manual verification is required to reduce the
likelihood of false failures due to associated cabling, con- Four Test Condition temperature cycling ranges and their
nectors, PWB TV or test apparatus problems. allowable temperature tolerances are defined in Table 4-1.
Except for the tolerances, Test Conditions TC1, TC3, and
Manual monitoring at thermal cycling intervals are not an TC4 are the same as test conditions J, G, and B in JEDEC
acceptable alternative to continuous monitoring. Not only 22 Method A 104 Revision A, respectively.
does manual monitoring ignore initial failures at high/low

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temperatures, but the accuracy of the failure durations are *CAUTION: Care should be taken when selecting Test
dependent on the manual sampling frequency. Further, this Conditions, since: 1) the T(max) requirement for a specific
method disturbs the tests, is uncertain finding failures when Test Condition may exceed the glass transition temperature
they occur, and is very time consuming. region (Tg minus 25°C [45°F]) of the PWB which would
cause a significant change in the physical properties of the
4.3.3.3 Failure Definition Failure is defined for the event
PWB and induce a nonlinear change in the loading condi-
detector as the first interruption for a period of one micro-
tions, 2) the T(max) requirement for a specific Test Condi-
second or less and increase in daisy chain resistance to
tion may exceed the glass transition temperature of some
1,000 Ω or more, and affirmation of the failure by nine or
component materials which may induce failure mecha-
more additional events within 10% of the cycles to initial
nisms not normally seen during design application condi-
failure. Large numbers of interruptions are required to be
tions in the field, and 3) CTE differences over the test con-
monitored in order to assure that failures are due to inter-
dition temperature range can produce premature failure of
connections. Interruption events associated with noninter-
plated-through holes in the test board, thus limiting electri-
connect failure such as apparatus/software malfunctions
cal readout capability for the parts being tested.
shall be documented.
For the data loggers, failure is defined as a maximum of Additional disadvantages of the Test Conditions TC3 and
20% nominal resistance increase within a maximum of five TC4 are:
consecutive reading scans. 1) Reduced compatability with high aspect ratio vias on
The failure definitions are given in Table 4-4. test boards.

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2) Reduced correlation of modeled and measured material 6.1 Failure Analysis Procedures Common failure analy-
characteristics over the wider temperature range. sis methods include optical and scanning electron micros-
3) Reduced accuracy of extrapolated lifetimes given the copy (SEM), X-ray and coupled scanning acoustic micros-
relatively benign actual-use temperature ranges of most copy (CSAM), cross section (transverse and parallel), and
electronic applications. dye-and-pry (pressurized dye exposure of assembled unit
followed by mechanical package removal). After nonde-
5.2 Thermal Cycling Test Durations The thermal structive characterization of failures, it is preferable to per-
cycling test duration requirements for any product should form both cross-sectioning and dye-and-pry evaluation.
be determined by the user or customer to meet specific
environmental operational conditions of the product. The For tests stopped at the end of an NTC level with ZERO
thermal cycling test duration requirements are given in failure, the supplier must perform failure analysis (three
Table 4-1. Preference should be given to temperature cycle randomly selected devices, minimum, per board test type)
condition TC1 (0 to 100°C [32°F to 212°F]) and test dura- to insure that failures were not missed due to errors in
tion NTC-E (6,000 cycles). Testing to 63% failures is daisy-chain design or test hardware.
always performed to characterize the failure distribution.
6.2 Data and Failure Analysis Documentation Require-
*CAUTION: Care should be taken when extrapolating ments The following documentation requirements are
accelerated test results for the product life-cycle in opera- mandated:
tional use. The short dwell/soak times at the temperature 1. Detailed description of all experimental apparatus,
extremes results in incomplete creep process. Thus, even including thermal chamber and data acquisition systems.
though the applied strain and stress ranges may be larger
2. Temperature vs. time plots for both boards and chamber
for accelerated test than during operational use, the cyclic
(chamber set-up characterization data).
hysteresis loops for test could be smaller. The test accelera-
tion is primarily one of shorter mean-time-to-failure and 3. Resistance vs. time plots for data logger samples.
not necessarily one of less cycles-to-failure. 4. Tabular data for number of cycles to failure for all fail-
ures, electronic file(s) preferred.
When 50% (preferred 63.2%) cumulative failure of
samples occur prior to defined NTC levels, then the test 5. 2-Parameter Weibull plots for all failures, preferred.
duration is defined by the number-of-cycles to the failure 6. Failure analysis samples and identification of failure
of the last failed samples. modes (dye-and-pry, CSAM, cross-section, X-ray or
whatever characterization technique is appropriate) and
5.3 Number of Samples A total of 33 components is
root cause identification of three samples, minimum, per
mandated for Default Product Characterization (see Table
test board type and major failure mode.
4-1). Of these, 32 are to be tested, and one sample is to be
cross-sectioned after assembly. Use of a minimum of 10 7. For tests stopped at NTC level with ZERO test failures,
additional virgin samples for rework assembly and its failure analysis documentation of three randomly
effects on reliability is strongly recommended for Full selected devices, minimum, per test board type.
Default Characterization. 8. Time-zero diagonal cross-section of single, representa-
tive package/board assembly.
For Category A Exemption (see Table 4-3), additional
samples for rework test are not required. 7 QUALITY ASSURANCE
5.4 Test Exemption Requirements The conditions that
have to be met to obtain a test exception are listed in Table 7.1 Responsibility for Inspection Unless otherwise
4-3 under Exempt column. No testing is required when the specified in the contract, the supplier is responsible for the
[New] device meets, with history of full Default Protection performance of all inspection requirements to assure qual-
characterization per IPC-9701, meets the Exempt require- ity conformance to inspection requirements specified in this
ments specified in this column. document. The user reserves the right to perform any of the
inspections set forth in the specification where such inspec-
6 FAILURE ANALYSIS tions are deemed necessary to assure supplies and services
The obvious goal of failure analysis is the ability to detect conform to prescribed requirements.
the location, mode, and mechanism for the observed elec-
trical failure. In many cases, it is not readily obvious if the 7.2 Quality Conformance Inspection
failure is within the test cable/connector, test board, solder
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attachment or internal package interconnect. Thoughtful 7.2.1 As Assembled Inspection Inspection for solder
design of the test board, daisy-chain die and overall inter- joint gross defects shall be performed by nondestructive
connect scheme can help to reduce the effort of failure iso- X-ray technique on assemblies as specified in 4.2.3.1. The
lation. nondestructive inspection along with the cross-sectioning

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sample inspection specified in 5.3 shall be used to deter- 7.2.2 Thermal Cycling Inspection Inspection shall be
mine the presence of assembly gross defects. If the gross performed on at least three samples of thermal profiles
defects reflect a non-optimized assembly process, then new generated by thermocouples at three thermal cycling inter-
assemblies shall be fabricated after inspection of compo- vals, start, middle, and completion; to assure they meet
nents and PWBs to assure conformance to their general the thermal cycling condition requirements specified in
requirements specified in 4.2.2 and 4.2.3 and further Section 5.
assembly process optimization. Key inspection parameters
are: 7.2.3 Failure Analysis Inspection Failure analysis shall
1. Component Inspection of component coplanarity to be performed as specified in section 6.1. For the test
meet JEDEC requirements. Review recommended com- stopped at the end of an NTC level with ZERO failure,
ponent bake out and assure compliance. cross-sectional and dye-and-pry samples shall be used for
mapping to assure that zero failure condition is met.
2. PWB Inspection of PWB warpage to meet IPC
requirements. Visual inspection of solder mask misreg-
istration and documentation of mask coverage on pad.
Mask coverage is not allowed.
3. Assembly Inspection of solder paste type and expira-
tion, squeegee blade, stencil, solder paste consistency on
PWB, and package placement. Solder paste is required
to cover all pads. Inspect reflow profile and assure to
meet manufacturing practice.

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APPENDIX A

A.1 ACCELERATION FACTORS A-3.1. It needs to be noted, that the temperature cycling
Analytical and computational models have not been fully ranges for test conditions TC3, and TC4 violate the stated
established to replace empirical solder joint reliability caveats for the underlying model; these caveats are a con-
evaluation. The solder joint reliability modeling to estimate sequence of the time-, temperature-, and stress-dependent
acceleration factors can be simple to complex depending material behavior of solder.
on experience and resources available. Nonetheless, com- In the Engelmaier-Wild model the fatigue ductility expo-
ponent end-users increasingly leverage both empirical and nent, m, given below accounts for the incomplete creep/
computational solder joint reliability studies to estimate stress relaxation process within solder joints during accel-
actual field-use lifetimes. It is recommended that the sup- erated testing. It accounts for the faster creep rates at
pliers responsible for the design and material selection of higher temperatures (TSJ, in °C) and the more complete
package provide mechanical models and material property creep for longer cyclic dwell times (tD=half-cycle dwell
tables for the empirically tested device. time in minutes).
There are two acceleration factors that need to be consid-
ered: AF(cycles), which relates the cyclic fatigue life of
solder joints obtained in a test to the life of a product in a
1
m
= 0.442 + 6x10-4 • TSJ – 1.74x10-2 • !n 1 +
(
360 minutes
tD )
given use environment; and AF(MTTF), which relates the (Eq. 3)
time to failure of solder joints obtained in a test to the life
of a product in a given use environment. The acceleration The mean cyclic solder joint temperature, TSJ, is given in
factor in terms of cycles to failure is the equation below.

Nf(product) 1[
TSJ = T(max,comp.) + T(max,sub.)
AF(cycles) = 4
Nf(test)
+ T(min,comp.) + T(min,sub.)]
(Eq. 1)
(Eq. 4)
where Nf(product) is the mean fatigue life, Nf (50%), of the
product in service and Nf(test) is the mean fatigue life, Nf In Table A-1, values for m are given for the four (4) test
(50%), of the test vehicles simulating the product in test- levels and some typical product temperature cycles.
ing. The acceleration factor in terms of time to failure is
For the different test conditions the values of m are differ-
f(test) ent because TSJ is different for each of the test levels; for
AF(MTTF) = AF(cycles) x

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f(product) the typical product cycles the values of m are the same
(Eq. 2) because in all cases TSJ = 30°C [54°F] and tD = 660 min-
utes.
where f(test) is the test cycle frequency and f(product) is
the cyclic frequency in service. In Table A-2, values for the mean fatigue lives, Nf (50%),
for a given component with fixed design parameters are
A.2 AN EXAMPLE OF ACCELERATION FACTOR CALCU- given for the four (4) test levels and the four (4) typical
LATION product cycles given in Table A-1, based on the solder
The following is one example of such calculation provided attachment fatigue model in IPC-D-279, Appendix A. Also
to compare the effects of key variables and should be used given are the values of AF(N) and the acceleration factors
as reference only. Similar acceleration factor calculations in terms of mean time to failure.
resulting from other models will be included as they
It should be noted, that the values of Nf and AF are all for
become available.
identical components on identical PCBs and the differences
The acceleration factors given below are based on the in life are solely the result of the differences in test and
Engelmaier-Wild model given in IPC-D-279, Appendix product service conditions.

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Table A-1 Values for Exponent ’’m’’ for the Four Test Condition
Levels and for Four Representative Product Use Conditions
Test Condition Typical Product Cycles
Test ∆T T(min) T(max) m ∆T T(min) T(max) m
100°C 0°C +100°C 20°C +20°C +40°C
TC 1 2.444 2.210
[180°F] [32°F] [212°F] [36°F] [68°F] [104°F]
125°C -25°C +100°C 60°C 0°C +60°C
TC 2 2.490 2.210
[225°F] [-13°F] [212°F] [108°F] [32°F] [140°F]
165°C -40°C +125°C 100°C -20°C +80°C
TC 3 2.471 2.210
[297°F] [-40°F] [257°F] [180°F] [-4°F] [176°F]
180°C -55°C +125°C 140°C -40°C +100°C
TC 4 2.499 2.210
[324°F] [-67°F] [257°F] [252°F] [-40°F] [212°F]

Table A-2 Mean Fatigue Lives for a Given Component Assembly

for the Four Test Condition Levels and for Four Representative
Product Use Conditions, and Their Respective Acceleration Factors
Test Condition Typical Product Cycles
Nf(50%) Nf(50%)
Test ∆T Nf(1%) ∆T Nf(1%) AF(N) AF(MTTF)
100°C 17,100 20°C 221,000
TC1 12.9 310.2
[180°F] 5,910 [36°F] 76,700
125°C 11,900 60°C 19,500
TC2 1.63 39.2
[225°F] 4,140 [108°F] 6,770
165°C 5,570 100°C 6,300
TC3 1.13 27.2
[297°F] 1,930 [180°F] 2,190
180°C 4,980 140°C 3,000
TC4 0.60 14.4
[324°F] 1,730 [252°F] 1,040

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APPENDIX B
Guidelines for Thermal Cycle
Requirements for Pb-Free Solder Joints

B.1 PURPOSE The models can be categorized as analytical [B4, B6, B7],
The following guidelines provide additional recommenda- one-dimensional strain-energy based [B2] or finite-element
tions to the indicated sections of IPC-9701 for testing strain-energy based models [B1, B3, B5, B8, B9, B10].
Pb-free solder joints. Recommendations for changes in the Because of the empirical correlation of the models to gen-
thermal cycle profile given here are based on current indus- erally unrelated failure datasets (including different types
try understanding and test results as of the publication of of packages, board assemblies, thermal conditions and fail-
this document. Data of the impact of various thermal cycle ure criteria), end users should assess for themselves the
profiles on the results of accelerated testing in comparison most appropriate models for a particular design and use
to eutectic tin-lead solder continue to be gathered by indus- conditions of interest. When fully validated models become
try. available, they will be included in an updated version of
this appendix.
Currently, there is only limited data and insight in deter-
mining acceleration factors and acceleration models for B.3.3 Recommendations to Table 4-1, Accelerated
Pb-free solders [B1-B14]. The results of the test method, in Thermal Cycle Profile For Tin-Silver-Copper (SAC)
conjunction with an accelerated test factor different for alloys the thermal profile defined in Table 4-1 remains the
each Pb-free solder, may in the future provide the ability to same except for dwells. Dwells at hot and cold temperature
estimate product reliability. extremes can be carried out at the following two conditions
depending on the reliability approach and user need:
B.2 APPLICABLE DOCUMENTS FOR Pb-FREE SOLDER
ALLOYS a) Condition D10 (10 minute dwell) – This condition
requires 10 minute dwells at the hot/cold temperature
IPC/JEDEC-J-STD-020 Moisture/Reflow Sensitivity Clas- extremes. This is perhaps the most efficient accelerated
sification for Nonhermetic Solid State Surface Mount thermal cycle profile as it induces the most strain
Device energy per unit of time (considering the entire cycle) or
per unit dwell time. Cycles-to-failure data generated
B.3 GUIDELINES FOR Pb-FREE SOLDER JOINTS under this condition should generally be used to make
The following sections provide additional recommenda- ‘‘stand-alone’’ life assessments for Pb-free solder joints,
tions to existing IPC-9701 section requirements when uti- and not to make comparisons between the life of
lizing a Pb-free soldering process. Pb-free and Sn-Pb joints. Only when damage accumu-
lation is understood through accepted models can test
B.3.1 Recommendations to 2.2, Joint Industry Standard results be used to determine the relative performance of
The most recent IPC/JEDEC J-STD-020 specification Pb-free and Sn-Pb joints under product service condi-
should be used for the Sn-Ag-Cu (SAC) system. This tions.
specification, in conjunction with component manufacturer
b) Condition D30+ (30 minutes or higher dwell) – This
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recommendations for moisture and bake out prior to solder

condition requires dwells of 30 minutes and higher (60
reflow, should be considered to ensure that test vehicles are
minutes) at the hot/cold temperature extremes in order
not damaged by the manufacturing process.
to experimentally induce creep damage that may be
B.3.2 Recommendations to 3.3.3, Solder Creep-Fatigue
somewhat comparable to lead-based solder. Modeling
Model There is no comprehensive model, available at the in conjunction with experimental data at different dwell
time of publication for this appendix, for Pb-free solder times may be required to better define such a compari-
creep-fatigue similar to that provided in Appendix A; how- son.
ever, there are currently a number of models for SAC For bismuth-tin (Bi-Sn) based solder alloys (e.g., 57Bi-
alloys, but none for tin-bismuth (Sn-Bi) solder alloys. 42Sn-1Ag), the 0 - 100°C temperature cycle should be
Examples of such models for thermal cycling reliability are required, unless components plated with Sn-Pb solder are
given in references [B1-B10]. Note that most of these mod- used. In this case, a -25 to +75°C temperature cycle is rec-
els are undergoing further validation by model developers ommended. Cycle profiles other than these should not be
and end users. considered acceptable for this class of Pb-free solders.

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B.3.4 Recommendations to 4.2.2.1, PWB/PCB Surface B.4 INFORMATION UPDATE SPECIFIC TO Pb-FREE SOL-
Finish, Item 9 OSP or immersion silver (IAg) surface fin- DER ALLOYS
ish which is a Pb-free material should be used for testing
of Pb-free solder joints. Sn-Pb HASL finish on the PWB B.4.1 Other Specification Revisions for Pb-Free This
should not be allowed for testing of Pb-free components specification refers to many other standards associated with
and Pb-free solders. Other surface finishes may be used for the manufacture of the test vehicle, from components and
manufacturer’s internal data comparison only. laminates to 2nd-level assembly and rework processes.
Some of these standards are currently being modified by
B.3.5 Recommendations to 5.4, Test Exemption industry to account for the changes in manufacturing con-
Requirements Note that two additional requirements ditions required by the new Pb-free alloys. Modifications
have been added to Table 4-3: may be required to account for the higher 2nd-level manu-
(1) Thermal cycle testing of solder joints should be facturing process temperatures required for Sn-Ag-Cu or
required when the component terminal plating or sol- other alloys, and the impact that this has on all the materi-
der ball alloy is changed: als involved. The applicable modified document for Pb-free
alloys should be used when they are available and the build
Exemption process should be fully documented. Examples include the
Description EXEMPT Category A
IPC-S-816, SMT Process Guideline and Checklist, the IPC-
Solder ball alloy, [NEW] = [NEW] =
termination plating [PQ 9701] [PQ 9701] 7711/21, Rework and Repair Guide, etc.

(2) Thermal cycle testing of solder joints should be B.4.2 Solder Failure Mechanism Failure mechanisms
required when the solder paste alloy used for 2nd-level defined in 3.6.2 may not be comparable with Pb-free
assembly is changed: alloys. Solder failure mechanisms may change at extremely
hot and cold temperatures and if so, need to be validated.
Exemption
Description EXEMPT Category A In addition, the background information provided in 3.9 is
Solder paste [NEW] = [NEW] = valid for eutectic Sn-Pb solder alloy, as specifically men-
materials [PQ 9701] [PQ 9701] tioned in the first paragraph.
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References Pacific Microelectronics Symposium, SMTA, Janu-

B1. Che, F. X., Pang, J. H. L., Xiong, B. S., Xu, L., Low, ary 25-27, 2005, Kauai, Hawaio, pp. 161-169.
T. H., ‘‘Lead free solder joint reliability characteriza-
B8. Schubert, A., Dudek, R., Auerswald, E., Gollhardt,
tion for PBGA, PQFP and TSSOP assemblies,’’ Pro-
A., Michel, B. and Reichl, H., ‘‘Fatigue life models
ceedings, 55th Electronic Components and Technol-
for SnAgCu and SnPb solder joints evaluated by
ogy Conference, Orlando, FL, May 31 - June 3,
experiments and simulation,’’ Proceedings (CD-
2005, pp. 916-921.
ROM), IEEE 53rd Electronic Components and Tech-
B2. Clech, J.P., EPSI Inc., ‘‘Acceleration Factors and nology Conference, New-Orleans, LA, May 27-30,
Thermal Cycling Test Efficiency for Lead-Free 2003.
Sn-Ag-Cu Assemblies,’’ to appear in Proceedings,
SMTA International Conference, Chicago, IL, Sep- B9. Syed, A., ‘‘Accumulated creep strain energy and
tember 25-29, 2005. energy density based thermal fatigue life prediction
models for SnAgCu solder joints,’’ Proceedings, 54th
B3. Guédon, Alexandrine, PhD Thesis on Lead-Free Sol-
Electronic Components and Technology Conference,
der Joint Modelling: ‘‘Contribution á l’exploitation
Las Vegas, NV, June 1-4, 2004, pp. 737-746.
d’un système de caractérisation thermomécanique
pour la conception optimisée d’assemblage sans B10. Zhang, Q., Dasgupta, A. and Haswell, P., ‘‘Viscoplas-
plomb,’’ University of Bordeaux, ENSEIRB, IXL tic constitutive properties and energy-partitioning
Lab (http://www.ixl.fr) 2005. model of lead-free Sn3.9Ag0.6Cu solder alloy,’’ Pro-
B4. Lall, P., Singh, N., Strickland, M., Blanche, J. and ceedings (CD-ROM), IEEE 53rd Electronic Compo-
Suhling, J., ‘‘Decision-support models for thermo- nents and Technology Conference, New-Orleans, LA,
mechanical reliability of lead free flip-chip electron- May 27-30, 2003.
ics in extreme environments,’’ Proceedings, 55th B11. Bartelo, J., Cain, S. R., Caletka, D., Darbha, K., Gos-
Electronic Components and Technology Conference, selin, T., Henderson, D. W., King, D., Knadle, K.,
Orlando, FL, May 31 - June 3, 2005, pp. 127-136. Sarkhel, A., Thiel, G. and Woychik, C., ‘‘Thermo-
B5. Ng, H. S., Tee, T. Y., Goh, K. Y., Luan, J-E., Reini- mechanical fatigue behavior of selected lead-free sol-
kainen, T., Hussa, E. and Kujala, A., ‘‘Absolute and ders,’’ Proceedings, IPC SMEMA Council APEX
relative fatigue life prediction methodology for vir- 2001, Paper # LF2-2.
tual qualification and design enhancement of lead-
B12. Clech, J.P., ‘‘An obstacle-controlled creep model for
free BGA,’’ Proceedings, 55th Electronic Compo-
SnPb and Sn-based lead-free solders,’’ Proceedings,
nents and Technology Conference, Orlando, FL, May
SMTA International (SMTAI) Conference, Chicago,
31 - June 3, 2005, pp. 1282-1291.
IL, Sept. 26-30, 2004, pp. 776-802.
B6. Pan, N., Henshall, G. A., Billaut, F., Dai, S., Strum,
M. J., Benedetto, E. and Rayner, J., Hewlett-Packard B13. Bath, J., et el, ‘‘Reliability Evaluation of Lead-free
Company. ‘‘An Acceleration Model for Sn-Ag-Cu Sn-Ag-Cu PBGA 676 Components Using Tin-Lead
Solder Joint Reliability Under Various Thermal Cycle and Lead-free Sn-Ag-Cu Solder Paste,’’ Proceedings,
Conditions,’’ to appear in Proceedings, SMTA Inter- SMTA International (SMTAI) Conference, Chicago,
national Conference, Chicago, IL, September 25-29, IL, Sept. 25-29, 2005, pp. 891-901
2005. B14. Ghaffarian, R., ‘‘Effect of Area Array Package Types
B7. Salmela, O., Andersson, K., Särkkä, J. and Tammen- on Assembly Reliability and Comments on IPC-
maa, M., ‘‘Reliability analysis of some ceramic lead- 9701’’ Proceedings, IPC SMEMA Council APEX,
free solder attachments,’’ 2005 Proceedings, Pan Feb 2006

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20
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 ANSI/IPC-T-50 Terms and Definitions for
ASSOCIATION CONNECTING
Interconnecting and Packaging Electronic Circuits
ELECTRONICS INDUSTRIES ®
Definition Submission/Approval Sheet
The purpose of this form is to keep SUBMITTOR INFORMATION:
current with terms routinely used in Name:
the industry and their definitions.
Individuals or companies are Company:
invited to comment. Please
City:
complete this form and return to:
IPC State/Zip:
3000 Lakeside Drive, Suite 309S Telephone:
Bannockburn, IL 60015-1219
Fax: 847 615.7105 Date:

❑ This is a NEW term and definition being submitted.

❑ This is an ADDITION to an existing term and definition(s).
❑ This is a CHANGE to an existing definition.

Term Definition

If space not adequate, use reverse side or attach additional sheet(s).

Artwork: ❑ Not Applicable ❑ Required ❑ To be supplied

❑ Included: Electronic File Name:
Document(s) to which this term applies:

Committees affected by this term:

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Office Use
IPC Office Committee 2-30
Date Received: Date of Initial Review:
Comments Collated: Comment Resolution:
Returned for Action: Committee Action: ❑ Accepted ❑ Rejected
Revision Inclusion: ❑ Accept Modify

IEC Classification
Classification Code • Serial Number
Terms and Definition Committee Final Approval Authorization:
Committee 2-30 has approved the above term for release in the next revision.
Name: Committee: IPC 2-30 Date:
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 This Page Intentionally Left Blank

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 Technical Questions
The IPC staff will research your technical question and attempt to find an appropriate specification
interpretation or technical response. Please send your technical query to the technical department via:
tel: 847-615-7100 fax: 847-615-7105
www.ipc.org e-mail: answers@ipc.org

IPC World Wide Web Page www.ipc.org

Our home page provides access to information about upcoming events, publications and videos, membership, and industry
activities and services. Visit soon and often.

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IPC Technical Forums
IPC technical forums are opportunities to network on the Internet. It’s the best way to get the help you need today! Over
2,500 people are already taking advantage of the excellent peer networking available through e-mail forums provided by IPC.
Members use them to get timely, relevant answers to their technical questions. Contact KeachSasamori@ipc.org for details.
Here are a few of the forums offered.

TechNet@ipc.org
TechNet forum is for discussion of issues related to printed circuit board design, assembly, manufacturing, comments or

BENEFITS OF IPC MEMBERSHIP

questions on IPC specifications, or other technical inquiries. IPC also uses TechNet to announce meetings, important technical
issues, surveys, etc.

ComplianceNet@ipc.org
ComplianceNet forum covers environmental, safety and related regulations or issues.

DesignersCouncil@ipc.org
Designers Council forum covers information on upcoming IPC Designers Council activities as well as information, comments,
and feedback on current designer issues, local chapter meetings, new chapters forming, job opportunities and certification. In
addition, IPC can set up a mailing list for your individual Chapter so that your chapter can share information about upcoming
meetings, events and issues related specifically to your chapter.

Trainingnews@ipc.org
This is an announcement forum where subscribers can receive notice of new IPC Training Products.

leadfree.ipc.org
This forum acts as a peer interaction resource for staying on top of lead elimination activities worldwide and within IPC.

IPC_New_Releases@ipc.org
This is an announcement forum where subscribers can receive notice of new IPC publications, updates and standards.

ADMINISTERING YOUR SUBSCRIPTION STATUS:

All commands (such as subscribe and signoff) must be sent to listserv@ipc.org. Please DO NOT send any command to the
mail list address, (i.e.<mail list> @ipc.org), as it would be distributed to all the subscribers.
Example for subscribing: Example for signing off:
To: LISTSERV@IPC.ORG To: LISTSERV@IPC.ORG
Subject: Subject:
Message: subscribe TechNet Joseph H. Smith Message: signoff DesignerCouncil
Please note you must send messages to the mail list address ONLY from the e-mail address to which you want to apply
changes. In other words, if you want to sign off the mail list, you must send the signoff command from the address that you
want removed from the mail list. Many participants find it helpful to signoff a list when travelling or on vacation and to
resubscribe when back in the office.
How to post to a forum:
To send a message to all the people currently subscribed to the list, just send to <mail list>@ipc.org. Please note, use the mail
list address that you want to reach in place of the <mail list> string in the above instructions.
Example:
To: TechNet@IPC.ORG
Subject: <your subject>
Message: <your message>
The associated e-mail message text will be distributed to everyone on the list, including the sender. Further information on
how to access previous messages sent to the forums will be provided upon subscribing.
For more information, contact Keach Sasamori
tel: 847-597-2815 fax: 847-615-5615
e-mail: sasako@ipc.org www.ipc.org/emailforums

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 Education and Training
IPC conducts local educational workshops and national conferences to help you better understand conventional and
emerging technologies. Members receive discounts on registration fees. Visit www.ipc.org to see what programs are
coming to your area.

IPC Certification Programs

IPC provides world-class training and certification programs based on several widely-used IPC standards, including
IPC-A-600, IPC-A-610, IPC/WHMA-A-620, J-STD-001 and IPC-7711A/7721A Rework and Repair. IPC-sponsored
certification gives your company a competitive advantage and your workforce valuable recognition.
For more information on these programs:
tel: 847-597-2814 fax: 847-615-7105
e-mail: certification@ipc.org www.ipc.org/certification

Designer Certification (C.I.D.)/Advanced Designer Certification (C.I.D.+)

Contact:
tel: 847-597-2827 fax: 847-615-5627
BENEFITS OF IPC MEMBERSHIP

e-mail: christipoulsen@ipc.org http://dc.ipc.org

EMS Program Manager Certification

Contact:
tel: 847-597-2884 fax: 847-615-5684
e-mail: susanfilz@ipc.org www.ipc.org/certification

IPC Video Tapes and CD-ROMs

IPC video tapes and CD-ROMs can increase your industry know-how and on the job effectiveness. Members receive
discounts on purchases.
For more information on IPC Video/CD Training, contact Mark Pritchard
tel: 505/758-7937 ext. 202 fax: 505/758-7938
e-mail: markp@ipcvideo.org http://training.ipc.org

IPC Printed Circuits Expo, APEX and the Designers Summit

This yearly event is the largest electronics interconnection event in North America. With technical
paper presentations, educational courses, standards development meetings networking opportunities
and designers certification, there’s something for everyone in the industry. The premier technical
conference draws experts from around the globe. 500 exhibitors and 6,000 attendees typically
participate each year. You’ll see the latest in technologies, products and services and hear about the trends that affect us
all. Go to www.GoIPCShows.org or contact shows@ipc.org for more information.

Exhibitor information:
Mary Mac Kinnon Alicia Balonek
Director, Show Sales Director, Trade Show Operations
847-597-2886 847-597-2898
MaryMacKinnon@ip c.org AliciaBalonek@ipc.org

How to Get Involved

The first step is to join IPC. An application for membership can be found in the back of this publication. Once you
become a member, the opportunities to enhance your competitiveness are vast. Join a technical committee and learn
from our industry’s best while you help develop the standards for our industry. Participate in market research programs
which forecast the future of our industry. Participate in Capitol Hill Day and lobby your Congressmen and Senators for
better industry support. Pick from a wide variety of educational opportunities: workshops, tutorials, and conferences.
More up-to-date details on IPC opportunities can be found on our web page: www.ipc.org.
For information on how to get involved, contact:
Jeanette Ferdman, Membership Director
tel: 847-597-2809 fax: 847-597-7105
e-mail: JeanetteFerdman@ipc.org www.ipc.org
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 Application for IPC Site Membership ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

Thank you for your decision to join IPC, Association Connecting Electronics Industries. IPC membership is site specific, which
means that benefits of IPC membership are extended only to employees at the site that is designated on this application.
To help IPC serve your member site in the most effective manner possible, please tell us what work is being done at your
site by choosing the most appropriate member category. (Check one box only.)

❏ INDEPENDENT PRINTED CIRCUIT BOARD MANUFACTURER

This facility manufactures, and sells to other companies, printed wiring boards (PWB’s) or other electronic interconnection
products on the merchant market.
What products do you make for sale?
❏ One- and two-sided rigid, multilayer printed boards ❏ Flexible printed boards ❏ Other interconnections
Site General Manager________________________________________________________________________________ _____
Name Title

❏ EMSI COMPANY - Independent Electronics Assembly

This facility assembles printed wiring boards, on a contract basis, and may offer other electronic interconnection products for sale.
Site General Manager____________________________________________________________________________________
Name Title

❏ OEM - Original Equipment Manufacturer

This facility purchases and/or manufactures printed wiring boards or other interconnection products for use in a final product,
which we manufacture and sell.
What is your company’s primary product line?
______________________________________________________________________________________________________

Site General Manager _________________________________________________________

___________________________
Name Title

❏ INDUSTRY SUPPLIER
This facility supplies raw materials, machinery, equipment, or services used in the manufacture or assembly of electronic
interconnection products.
What products or services does your company supply? (50 word limit, please)
The information that you provide here will appear in the next edition of the IPC Membership Directory.

Our company supplies:

❏ GOVERNMENT AGENCY/ACADEMIC TECHNICAL LIAISON

This government agency or accredited university, college or technical training school is directly concerned with design,
research and utilization of electronic interconnection devices. (Must be a non-profit or not-for-profit organization.)

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Please proceed to page 2 to complete the membership application. 1
Copyright Association Connecting Electronics Industries
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 Application for IPC Site Membership ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

Site Information: (Please print or type)

Company Name

Street Address

City State Zip/Postal Code Country

Main Switchboard Phone No Main Fax No.

Company E-Mail Address Website URL

Name of Primary Contact for all IPC matters Title Mail Stop

Phone No. Fax No E-Mail

Name of Senior Management Contact: Title: Mail Stop

Phone No Fax No E-Mail

Please attach business card of primary contact here.

Please designate your site’s Technical Representatives:

For PWB/PWA design-related information and activities:

Contact Name Title Phone Fax E-mail

For PCB fabrication-related information and activities:

Contact Name Title Phone Fax E-mail

For Electronics Assembly-related information and activities:

Contact Name Title Phone Fax E-mail

Please designate your site’s Management Representatives:

For PWB/PWA design-related information and activities:

Contact Name Title Phone Fax E-mail

For PCB fabrication-related information and activities:

Contact Name Title Phone Fax E-mail

For Electronics Assembly-related information and activities:

Contact Name Title Phone Fax E-mail

2 Please proceed to page 3 to complete the membership application.

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 Application for IPC Site Membership ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

MEMBERSHIP DUES SCHEDULE

Please check one: TMRC MEMBERSHIP
❏ $1,000.00 – Annual dues for Primary Site Membership ❏ Please send information on participation in the
Twelve months of IPC membership begins from the Technology Market Research Council (TMRC) program.
time the application and payment are received at the Only current IPC member sites are eligible to participate
IPC office. in this calendar year program, which is available for an

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❏ $800.00 – Annual dues for Additional Facility additional fee.
Membership ❏ Yes, sign up our site now:
An additional membership for a site within an organi- $950.00 - Primary TMRC member site
zation where there already is a current Primary Site $400.00 - Additional facility TMRC member. Another
IPC membership. site within our organization is already a
❏ $600.00** – Annual dues for an independent PCB/PWA TMRC program participant.
fabricator or independent EMSI provider with annual
sales of less than $1,000,000.00. USD Name of Primary Contact for all TMRC matters:
** Please provide proof of annual sales.
❏ $250.00 – Annual dues for Government Agency or
Academic Technical Liaison Membership. Must be
Phone Fax
not-for-profit organization.
E-Mail

PAYMENT INFORMATION
Enclosed is our check/money order for $________________________
Mail application with check or money order to:
IPC
3491 Eagle Way
Chicago, IL 60678-1349
Fax or mail application with credit card payment to:
IPC
*3000 Lakeside Drive, Suite 309S
Bannockburn, IL. 60015-1249
Tel: 847-615-7100
Fax: 847-615-7105
* Overnight deliveries to this address only
Please bill my credit card (circle one) for $_______________________
❏ MasterCard ❏ American Express ❏ Visa ❏ Diners Club

Account No Expiration Date

Name of Card Holder

Authorized Signature

Phone Number

QUESTIONS ?
Call the IPC Member Services Department in Bannockburn, Illinois,
at 847-597-2809 or 847-597-2872, or fax us at 847-615-7105.
E-mail: JeanetteFerdman@ipc.org SusanStorck@ipc.org

Please proceed to page 4 to complete the membership application.

Tech doc
3
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 Application for IPC Site Membership ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

INFORMATION DISTRIBUTION
IPC has significant member benefits available to a wide range of individuals within your organization. To ensure that your facility
takes advantage of these benefits, please provide the name of the individual responsible for each of the functional areas listed
below. If one person has multiple responsibilities, please list that person’s name as many times as necessary.
Chief Executive:

Name Title/Mail Stop Phone Fax E-mail

Sales/Marketing:

Name Title/Mail Stop Phone Fax E-mail

Finance (CFO)

Name Title/Mail Stop Phone Fax E-mail

Human Resources

Name Title/Mail Stop Phone Fax E-mail

Environmental/Safety

Name Title/Mail Stop Phone Fax E-mail

Design/Artwork

Name Title/Mail Stop Phone Fax E-mail

Product Assurance

Name Title/Mail Stop Phone Fax E-mail

Manufacturing
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Name Title/Mail Stop Phone Fax E-mail

Training

Name Title/Mail Stop Phone Fax E-mail

Purchasing

Name Title/Mail Stop Phone Fax E-mail

IPC REVIEW SUBSCRIPTION LIST

One of the many benefits of IPC membership is a subscription to the IPC Review, our monthly magazine. Please list below
the names of individuals who would benefit from receiving our magazine, which provides information about the industry,
IPC news, and other items of interest. A subscription for the IPC Primary Contact person is entered automatically.

Name Title/Mail Stop

Name Title/Mail Stop

Name Title/Mail Stop

Name Title/Mail Stop

Name Title/Mail Stop

Name Title/Mail Stop

4
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 ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®

Standard Improvement Form IPC-9701A

The purpose of this form is to provide the Individuals or companies are invited to If you can provide input, please complete
Technical Committee of IPC with input submit comments to IPC. All comments this form and return to:
from the industry regarding usage of will be collected and dispersed to the IPC
the subject standard. appropriate committee(s). 3000 Lakeside Drive, Suite 309S
Bannockburn, IL 60015-1219
Fax 847 615.7105
E-mail: answers@ipc.org

1. I recommend changes to the following:

Requirement, paragraph number
Test Method number , paragraph number

The referenced paragraph number has proven to be:

Unclear Too Rigid In Error
Other

2. Recommendations for correction:

3. Other suggestions for document improvement:

Submitted by:

Name Telephone

Company E-mail

Address

City/State/Zip Date

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 --`,,```,,,,````-`-`,,`,,`,`,,`---

ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES ®
ISBN #1-580987-79-6 3000 Lakeside Drive, Suite 309S, Bannockburn, IL 60015-1219
Tel. 847.615.7100 Fax 847.615.7105
www.ipc.org

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