20ECE474 – ARM and PIC

Programming
Viva - Voce

ARM Programming

1) Differentiate CISC and RISC architectures.

2. What is Pipelines ?
The processing of instructions is broken down into smaller units that can be executed in
parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum
throughput. Instructions can be decoded in one pipeline stage. There is no need for an
instruction to be executed by a miniprogram called microcode as on CISC processors.
3. What is Registers?
RISC machines have a large general-purpose register set. Any register can contain either
data or an address. Registers act as the fast local memory store for all data processing
operations. In contrast, CISC processors have dedicated registers for specific purposes.
4. Explain Load-store architecture.
The processor operates on data held in registers. Separate load and store instructions
transfer data between the register bank and external memory. Memory accesses are costly, so
separating memory accesses from data processing provides an advantage because you can use
data items held in the register bank multiple times without needing multiple memory accesses.
In contrast, with a CISC design the data processing operations can act on memory directly.
5. Explain Variable cycle execution for certain instructions.
Not every ARM instruction executes in a single cycle. For example, load-store-multiple
instructions vary in the number of execution cycles depending upon the number of registers
being transferred. The transfer can occur on sequential memory addresses, which increases
performance since sequential memory accesses are often faster than random accesses. Code
density is also improved since multiple register transfers are common operations at the start
and end of functions.

6. Explain Inline barrel shifter leading to more complex instructions.

The inline barrel shifter is a hardware component that pre-processes one of the input
registers before it is used by an instruction. This expands the capability of many
instructions to improve core performance and code density. We explain this feature in more
detail in Chapters 2, 3, and 4.
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7. What is Thumb 16-bit instruction set ?
ARM enhanced the processor core by adding a second 16- bit instruction set called
Thumb that permits the ARM core to execute either 16- or 32-bit instructions. The 16-bit
instructions improve code density by about 30% over 32-bit fixed- length instructions.

8. What is Conditional execution?

An instruction is only executed when a specific condition has been satisfied. This
feature improves performance and code density by reducing branch instructions.

9. What is Peripherals ?
Theperipherals provide all the input-output capability external to the chip and are
responsible for the uniqueness of the embedded device.
10. What is a bus?
A Bus is used to communicate between different parts of the device.

11. Explain the AMBA bus protocol.

The Advanced Microcontroller Bus Architecture (AMBA) was introduced in 1996 and has been
widely adopted as the on-chip bus architecture used for ARM processors. The first AMBA
buses introduced were the ARM System Bus (ASB) and the ARM Peripheral Bus (APB). Later
ARM introduced another bus design, called the ARM High Performance Bus (AHB).
12. Explain Different Types of Memory.
 Read-only memory (ROM) is the least flexible of all memory types because it
contains an image that is permanently set at production time and cannot be
reprogrammed.
 Dynamic random access memory(DRAM)is the most commonly used RAM for
devices. It has the lowest cost per megabyte compared with other types of RAM.
 Static random access memory (SRAM) is faster than the more traditional DRAM, but
requires more silicon area. SRAM is static—the RAM does not require refreshing.
 Synchronous dynamic random access memory (SDRAM) is one of many
subcategories of DRAM. It can run at much higher clock speeds than conventional
memory. SDRAM synchronizes itself with the processor bus because it is clocked

13. What are memory controller and Interrupt controller?

Memory Controllers
Memory controllers connect different types of memory to the processor bus. On power-up a
memory controller is configured in hardware to allow certain memory devices to be active.
These memory devices allow the initialization code to be executed. Some memory devices
must be set up by software; for example, when using DRAM, you first have to set up the
memory timings and refresh rate before it can be accessed.
Interrupt Controllers
When a peripheral or device requires attention, it raises an interrupt to the processor. An
interrupt controller provides a programmable governing policy that allows software to
determine which peripheral or device can interrupt the processor at any specific time by
setting the appropriate bits in the interrupt controller registers.
There are two types of interrupt controller available for the ARM processor: the standard
interrupt controller and the vector interrupt controller (VIC).
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14. With a neat diagram explain the different general purpose registers of ARM
processors.

 General-purpose registers hold either data or an address. They are identified with the letter r
prefixed to the register number. For example, register 4 is given the label r4. The active
registers available in user mode—a protected mode normally used when executing
applications. The processor can operate in seven different modes. All the registers shown are
32 bits in size.

 There are up to 18 active registers: 16 data registers and 2 processor status registers. The data
registers are visible to the programmer as r0 to r15.

 The ARM processor has three registers assigned to a particular task or special function: r13,
r14, and r15. They are frequently given different labels to differentiate them from the other
registers.

 Special-purpose registers:

 Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack
in the current processor mode.
 Register r14 is called the link register (lr) and is where the core puts the return
address whenever it calls a subroutine.
 Register r15 is the program counter (pc) and contains the address of the next instruction
to be fetched by the processor.

Depending upon the context, registers r13 and r14 can also be used as general-purpose
registers, which can be particularly useful since these registers are banked during a processor
mode change.

15. Explain current program status register (CPSR) with neat diagram.
The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated
32-bit register and resides in the register file. Figure shows the basic layout of a generic
program status register. Note that the shaded parts are reserved for future expansion.

The cpsr is divided into four fields, each 8 bits wide: flags, status, extension, and control. In
current designs the extension and status fields are reserved for future use. The control field
contains the processor mode, state, and interrupt mask bits. The flags field contains the
condition flags.

16. What is Processor Modes ?

The processor mode determines which registers are active and the access rights to the cpsr
register itself. Each processor mode is either privileged or non-privileged: A privileged mode
allows full read-write access to the cpsr. Conversely, a non-privileged mode only allows read
access to the control field in the cpsr but still allows read-write access to the condition flags.
There are seven processor modes in total: six privileged modes (abort, fast interrupt request,
interrupt request, supervisor, system, and undefined) and one non-privileged mode (user).

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17. Which are the different conditional flags of ARM processor.

Condition flags are updated by comparisons and the result of ALU operations that specify the
S instruction suffix. For example, if SUBS subtract instruction results in a register value of
zero, then the Z flag in the cpsr is set. This particular subtract instruction specifically updates
the cpsr.

18. Explain ARM pipeline with 3,5,6 stages.

A pipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline
speeds up execution by fetching the next instruction while other instructions are being
decoded and executed.

• Fetch loads an instruction from memory.

• Decode identifies the instruction to be executed.
• Execute processes the instruction and writes the result back to a register.

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19. What are interrupts or exceptions?

When an exception or interrupt occurs, the processor sets the pc to a specific memory
address. The address is within a special address range called the vector table. The entries in
the vector table are instructions that branch to specific routines designed to handle a
particular exception or interrupt.

The memory map address 0x00000000 is reserved for the vector table, a set of 32-bit words.
On some processors the vector table can be optionally located at a higher address in memory
(starting at the offset 0xffff0000).

20. Reset Vector: Reset vector is the location of the first instruction executed by the processor
when power is applied. This instruction branches to the initialization code.

21. Undefined instruction vector is used when the processor cannot decode an instruction.

22. Software interrupt vector is called when you execute a SWI instruction. The SWI
instruction is frequently used as the mechanism to invoke an operating system routine.

23. Prefetch abort vector occurs when the processor attempts to fetch an instruction from an
address without the correct access permissions. The actual abort occurs in the decode stage.
24. Data abort vector is similar to a prefetch abort but is raised when an instruction attempts to
access data memory without the correct access permissions.

25. Interrupt request vector is used by external hardware to interrupt the normal
execution flow of the processor. It can only be raised if IRQs are not masked in the cpsr.
26. Fast interrupt request vector is similar to the interrupt request but is reserved for
hardware requiring faster response times. It can only be raised if FIQs are not masked in the
cpsr.

27 Explain A brief Comparison of different ARM families:

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27. Write the difference between Von Neumann and Harvard:

Parameters Von Neumann Harward

Memory Data and program(code) are stored in Data and Program (Code) are stored in
same memory different memory )
Memory Type It has only RAM for Data & Code It has RAM for Data and ROM for
Code.
Buses Common bus for Address and Separate Bus Address and Data / Code
Data/Code
Data / Code Data or Code in one cycle Data and Code in one cycle
Transfer
Control Signals Less More
Space It needs less Space It needs more space
Cost Less Costly

28. Write the difference between Assembly Language and C Language

S.No Assembly Language C- Language

1 Unstructured Language (No Formal Structure) Structured Language ( Well Define Structure )
2. Differs with respect to processors and Controllers Core Idea remain same with respect to processor and
Controllers
3 Low Level Interface High Level Interface. It can use Assembly as well.
4. Architecture Specific – Based on Instruction Set General Purpose

5. Assembler converts it into Machine Codes. Compiler converts into Machine Codes

6. Program length is small Program Length is longer than Assembly.

7. Program Execution is Faster Program Execution is Slower

8. Delvelopment of Program is bit Complex Development of program is relatively easier.

9. Less then 10% of programmers use Assembly. More thean 90% of programmers use C.

10. Less lexible More Flexible

11. Slow Development Fast Development

12. Performance based Programming User Friendly Programming.

29. What is Little Endian and Big Endian

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30. What is Assembler Directives ?

Assembler Directives not a instruction. It is a Pseudo Codes. It is given
directives to assembler Language Program. Ex: AREA: The AREA directive tells
the assembler to define a new section of memory.

31. What is Pre-index and Post-index mode ?

-pre-index modes which apply the offset before accessing the memory.
-post-index modes which apply the offset after accessing the memory.

32. What are the different types of addressing modes in ARM7 ?

Addressing Mode: The various formats of specifying the operands in
instructions are called addressing modes.
1. Immediate Addressing mode: Data (only 1 byte) specified in
instruction.
Ex: Mov R5, #0x20 ; 20H will copied to R5
ADD R0,R1,#0x20 ; R0 <-- R1+20H
2. Register Addressing Mode: data is given by registers only. All logical
and Arithmetic instructions are based on this mode only with ARM.
Ex: Mov R5,R1 ; R1 data copied into R5
3. Direct Addressing Mode: Address of operand is given in this
instruction. This address will be 1 bits offset from PC given by
assembler.
Ex: LDR R5, Variable ; R5 <-- [Variable]
4. Indirect Addressing Mode: Address of operand is given by register.
Ex: LDR R5, [R1] ; R5 <- - [R1]
5. Register Relative Indirect Addressing Mode: Here Address of the
memory operand is given by a register(base address) + Numeric Value
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(offset). Programming
Ex: LDR R0, [R1, #0x04] ; R0<- - data from memory pointed by
(R1+4). Here R1 remains unchanged.
LDR R0, [R1, #0x04]! ; First R1<- - R1+4, then R0 <- - data
from memory pointed by [R1].
-This is called PRE-INDEX addressing.
LDR R0, [R1], #0x04 ; First R0<- - [R1], then R1 <- - R1+4,
-This is called Post-INDEX addressing.
pre-index modes which apply the offset before accessing the memory.
post-index modes which apply the offset after accessing the memory.

6. Base Indexed Indirect Addressing Mode:

- Here address of the memory operand is given by a sum of two
registers.
- Where first register act as base second register act as index
register.
Ex: LDR R0,[R1,R2] ; R0 <- - data from memory pointed by
(R1+R2). Here R1 remain unchanged.
7. Base with Scaled Index Indirect Addressing Mode: Here address of the
memory operand is given by a sum of two registers, where first register
act as base and second register scaled index by shift left.
Ex: LDR R0, [R1,R2,LSL #2] ; R0<- - data from memory pointed
by [R1+R2 shifted left by 2 bits]. Here R1 remains unchanged.
33. What is Branch Instruction ?
A branch Instruction changes the normal flow of execution of a main
program or is used to all a subroutine.
B – Branch
BL – Branch with Link
BX – Branch Exchange
BLX – Branch exchange with Link

34. Comparison of Cortex-A, Cortex-B and Cortex-M

Parameters Cortex A Cortex B Cortex M

Performance Highest Very Good Medium
Response Very Good Best Medium

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Programming
Time
Power 80 microWatt / MHZ 120 microWatt / 8 microWatt /
Consumption MHZ MHZ
Processor Application Based RTOS based Embedded System
based
Pipeline Long Pipeline Medium Pipeline Short Pipeline
Clock High High Less relatively
Memory Cache memory with Cache memory + Cache Memory
more size Tightly Coupled with less size
memory
ISA ARM ARM Thumb
FPU Yes Yes Optional
Application Computer, Router, etc., Robert, Harddisk, Headphone,
(High performance etc smart watch etc.,
device)

PIC Programming

35. What is PIC Controller ?

 In 1989 microchip technology corporation introduced an 8-bit micro-controller
Called PIC Microcontroller which stands for Peripheral Interface Controller.
 This micro-controller had small amount of data RAM , a few hundred bytes of on-
chip ROM for the program ,one timer, and a few pins for I/O ports ,all on a
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single chip . Programming
 Some PIC Microcontroller families are 10xxx, 12xxx, 14xxx, 16xxx, 17xxx and
18xxx.
 They are all 8 bit processor means CPU can work on only 8 bit data at a time and
data larger than 8 bit are broken into 8-bit pieces to be processed by the CPU.

36. What is Flash memory (program memory) ?

Code memory or read-only memory (ROM), is where
the program's instructions are stored (nonvolatile storage technology).

37. What is SRAM (data memory) ?

This is RAM memory type, which contains a special registers like SFR (Special
Faction Register) and GPR (General Purpose Register).

38. What is EEPROM memory (programmable at run-time) ?

EEPROM (Electrically Erasable Programmable Read-Only Memory) is user-
modifiable read-only memory (ROM) that can be erased and reprogrammed.

39. What is Sleep mode (power savings) ?

In Sleep mode, the normal operation of a PIC microcontroller is suspended and
the clock oscillator is switched off. The power consumption is lowest in this state.

40. What is Watchdog timer ?

A watchdog timer is a simple countdown timer which is used to reset a
microprocessor after a specific interval of time.

41. Write the Feature of PIC16F877.

 It has a smaller 35 instructions set.
 It can operate up to 20MHz frequency.
 The operating voltage is between 4.2 volts to 5.5 volts. If you provide it
voltage more than 5.5 volts, it may get damaged permanently.
 It is available as 40 PIN IC.
 8K x 14 words of Flash Program Memory,
 Data Memory RAM of 368 x 8 bytes,
 EEPROM Data Memory of 256 x 8 bytes (EEPROM retention is 40 years).
 Low-power, high-speed Flash/EEPROM technology.
 It uses Low-power consumption.
 Power saving Sleep mode.
 Watchdog Timer.

42.. Explain Different types of Memory in PIC controller.

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Program Memory: Programming
• Program memory contains the programs that are written by the user. The
program counter (PC) executes these stored commands one by one.
• Usually PIC16F877 devices have a 13 bit wide program counter that is capable
of addressing 8K×14 bit program memory space.
• we write a new program to the controller, we must delete the old one at that
time.
• The special function registers are also memory registers which is used for
special dedicated functions.
• These registers are used by the CPU and peripheral modules for controlling the
desired operation of the device.
• These registers are normally implemented as in the form of static RAM
memory.
Data Memory Organization
• The data memory is partitioned into multiple banks which contain the General
Purpose Registers and the Special Function Registers.
• Bits RP1 (Status) and RP0 (Status) are the bank select bits.

• Each bank extends up to 7Fh (128 bytes).

• The lower locations of each bank are reserved for the Special Function
Registers.
• Above the Special Function Registers are General Purpose Registers,
implemented as static RAM.
• All implemented banks contain Special Function Registers.
• Some frequently used Special Function Registers from one bank may be
mirrored in another bank for code reduction and quicker access.

42. What is Parallel I/O Port.

 Unlike parallel communication, where several bits are send at one time.
 Most of the PIC16cx/7x family controllers have 33 I/O lines and five I/O
ports They are PORT A, PORT B, PORT C , PORT D and PORT E.
 PORT A: Port A is a 6-bit wide bi-directional port. Its data direction
register is TRISA setting TRISA bit to 1 will make the corresponding
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PORT A Pin an input. Clearing a TRIS
Programming a bit will make the corresponding
pin as an output.
 PORT B: Port B is an 8-bit wide, bi-directional port. Four of the PORT
B pins RB7 – RB4 have an interrupt-on- change feature. Only the pins
configured as inputs can cause this interrupt to occur.
 PORT C: Port C is an 8-bit wide, bidirectional port. Bits of the TRISC
Register determine the function of its pins. Similar to other ports, a logic
one 1 in the TRISC Register configures the appropriate port pin as an
input.
 PORT D: Port D is an 8-bit wide bi-directional port. In addition to I/O
port, Port D also works as 8-bit parallel slave port or microprocessor port,
when control bit PSPMODE (TRISE:4) is set.
 PORT E: It is a 3-bit bi-directional port. Port E bits are multiplexed with
analog inputs of ADC and they serve as control signals (RD , WR, CS)
for parallel slave port mode of operation.
43. What is Serial I/O Port ?
 Serial Communication is a process of transmitting data bit by bit.
 USART is a two wire communication system in which the data flow
serially.
 USART is also a full-duplex communication, means you can send and
receive data at the same time which can be used to communicate with
peripheral devices, such as CRT terminals and personal computers.
 it can be configured as a half-duplex synchronous system that can
communicate with peripheral devices, such as Analog-to-Digital (A/D) or
Digital-to-Analog (D/A) integrated circuits, serial EPROM’s, and so on.
 Usually PIC 16F877 consists of USART module which can be controlled
by,
-Transmit status and control register(TXSTA)
-RCSTA – Receive Status and Control Register

44. What is Interrupt ?

• Even they disrupts the normal execution and cause the executing the special
instructions.

44. Write the difference between Polling and Interrupt.

• Polling:
-PIC continuously monitor the status of each device
-Each device get the attention of the CPU as the same level of priority.
• Interrupt:
-Devices get the attention of the CPU only when it needs a service.
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-Can service many devices with different level
Programming of priorities.

45. What is ISR ?

 When an interrupt is invoked the microcontroller runs the ISR.
 Interrupt Vector Table (IVR) holds the address of ISRs
- Power-on-Reset = 0000H
- High Priority Interrupt = 0008H
- Low Priority Interrupt = 0018H
-
46. Explain Flag Bit, Enable bit and Priority bit.

 Flag bit: To indicate that an interrupt event occurred

 -Enable bit: that allows program execution to branch to the interrupt vector
address when the flag bit is set.
 - Priority bit: to select high priority or low priority

47. Write the different categories in PIC Instruction Set.

The Instruction set of PIC is divided into 3- basic categories, they are
(a) Byte oriented Instructions
(b) Bit oriented Instructions
(c) Literal and Control Instructions.

48. Write the classification of Instructions Set in PIC.

All the instructions of the PIC microcontroller are classified into nearly 9 groups.
They are, Arithmetical, Logical, Increment/Decrement, Data Transfer, Clear,
Rotation, Unconditional, Conditional and Miscellaneous Instructions.

49. What is Working Register ?

Working Register is used by many instructions as the source of an operand. It
also serves as the destination for the result of instruction execution and it is
similar to accumulator in other mcs and mps.

50. What is Status Register ?

This is an 8-bit register which denotes the status of ALU after any arithmetic
operation and also RESET status and the bank select bits for the data memory.
51. What is FSR – (File Select Register) ?
It is the pointer used for indirect addressing. In the indirect addressing mode the
8-bit register file address is first written into FSR. It is a special purpose register
that serves as an address pointer to any address through out the entire register file.
52. What is INDF – (Indirect File) ?
It is not a physical register addressing but this INDF will cause indirect
addressing. Any instruction using the INDF register actually access the register
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pointed to by theFSR.
Programming
53. What is PROGRAM COUNTER ?
- PIC PIC16F877A has a 13 bit program counter in which PCL is the lower 8-bits
of the PC and PCLATH is the write buffer for the upper 5 bits of the PC.
-PCLATH (program counter Latch can be read or from or written to without
affecting the Program Counter(PC).The upper 3 bits of PCLATH remain zero.It is
only when PCL is written to that PCLATH is automatically written into the PC at
the same time.
54. What is CCP ?
 The CCP module(s) can operate in one of three modes 16-bit capture, 16-bit
compare, or up to 10-bit Pulse Width Modulation (PWM)
 Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL
register pair. The capture event can be programmed for either the falling edge,
rising edge, fourth rising edge, or sixteenth rising edge of the CCPx pin.
 Compare mode compares the TMR1H:TMR1L register pair to the
CCPRxH:CCPRxL register pair. When a match occurs, an interrupt can be
generated and the output pin CCPx can be forced to a given state (High or
Low) and Timer1 can be reset. This depends on control bits
CCPxM3:CCPxM0.
55. Explain Timer/Counter.
 As the name suggests these are used to measure the time or generate the
accurate time delay.
 The microcontroller can also generate/measure the required time delays by
running loops, but the timer/counter relieves the CPU from that redundant and
repetitive task, allowing it to allocate maximum processing time for other
tasks.
 Timer is nothing but a simple binary counter that can be configured to count
clock pulses(Internal/External).
 Once it reaches the Max value, it will roll back to zero setting up an
OverFlow flag and generates the interrupt if enabled.

56. Write Various PIC Timer Mode.

Control Count Min Max
Timer Size
Register Register Delay Delay

TIMER0 8-bit OPTION_REG TMR0 0.2usec 13.107ms

TMR1H,
TIMER1 16-bit T1CON 0.2usec 104.857ms
TMR1L

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TIMER2 8-bit T2CON TMR2 0.2usec 819usec

57. Explain Timer-0.

 The TMR0 module is an 8-bit timer/counter with the following features:
 8-bit timer/counter
 Readable and writable
 8-bit software programmable prescaler
 Internal or external clock select
 Interrupt on overflow from FFh to 00h
 Edge select for external clock
58. Explain Timer-1
 16-bit timer/counter with two 8-Bit register TMR1H/TMR1L
 Readable and writable
 software programmable prescaler upto 1:8
 Internal or external clock select
 Interrupt on overflow from FFFFh to 00h
 Edge select for external clock
59. Explain Timer-2
 8-bit timer/counter
 Readable and writable
 Software programmable prescaler/PostScaler upto 1:16
 Interrupt on overflow from FFh to 00h
60. Use of RS232 in PIC.
 This article shows how to do a simple communication via a RS232 interface
with a PIC microcontroller. RS232 is a standard for a serial communication
interface which allows to send and receive data via at least three wires. With
the RS232 interface it is possible to setup a connection between a
microcontroller and a PC (via PC's COM port) or between two
microcontrollers.

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