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3.SAP-2 Computer Architecture

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Mohsin Islam Rifat
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59 views61 pages

3.SAP-2 Computer Architecture

Uploaded by

Mohsin Islam Rifat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Simple As Possible

Computer (SAP-2)
Reference: Malvino . Brown C h a p t e r 11

Dr. Fakir Sharif Hossain


Associate Prof., EEE,
AUST
Block Diagram

@Hossain
Comparison between SAP1 & SAP2 Computer
Architecture
SAP1 SAP2

Input block 1 2

Output block 1 2

RAM/Memory Size=16×8 Size=64K×8 [first 2k for ROM, rest


Address->4 64k for RAM]
bit Data-> 8 Address->16
bit Opcode- bit Data-> 8
>4 bit bit Opcode-
>8 bit
Registers 2 (A, B) 4 (A, B, C, Temp)

Flags No Yes

Instructions 4 42

@Hossain
Types of instruction

i. Data Transfer instruction { use for changing the location of data }

ii. Data manipulation Instruction { perform arithmetic, Logical, shift


operation}

iii. Programmed control instruction { provide decision making capability}

@Hossain
Data Transfer Instruction

Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

@Hossain
Data Manipulation Instruction

Logical and bit manipulation


Arithmetic Instruction
Name Mnemonic Name Mnemonic Shift Instruction
Increment INC Clear CLR Name Mnemonic
Decrement DEC Complement COM Logical shift Right SHR
Addition ADD And AND Logical shift left SHL
Subtraction SUB OR OR Rotate right
Multiplication MUL XOR XOR Rotate left ROR
Division DIV XNOR XNOR
Negative NEG ROL

@Hossain
Program control Instruction

Name Mnemonic
Jump Jump
Call CALL
skip SKP

@Hossain
SAP2
Instructions
(42)

@Hossain
Mnemonics and Op-code

Mnemonics Op code Mnemonics Op code


ADD B 80H HLT 76H
ADD C 81H IN byte DBH
ANA B A0H INR A 3CH
ANA C A1H INR B 04H
ANI byte E6H INR C 0CH
CALL address CDH JM address FAH
CMA 2FH JMP address C3H
DRC A 3DH JNZ address C2H
DCR B 05H JZ address CAH
DCR C 0DH LDA address 3AH

@Hossain
Mnemonics and Op-code
Mnemonics Op code Mnemonics Op code
MOV A,B 78H ORA C B1H
MOV A , C 79H ORI byte F6H
MOV B,A 47H OUT byte D3H
MOV B,C 41H RAL 17H
MOV C , A 4FH RAR 1FH
MOV C,B 48H RET C9H
MVI A,byte 3EH STA address 32H
MVI B,byte 06H SUB B 90H
MVI C,byte 0EH SUB C 91H
NOP 00H XRA B A8H
ORA B B0H XRA C A9HH

@Hossain
Memory-Reference
Instructions

@Hossain
LDA

@Hossain
ST
A

@Hossain
MVI

@Hossain
MVI

@Hossain
Problem

@Hossain
Solution Machine Code

Assembly Code

@Hossain
Register
Instructions

@Hossain
MOV

@Hossain
MOV

@Hossain
ADD and SUB

@Hossain
ADD and SUB

@Hossain
INR and DCR

@Hossain
INR and DCR

@Hossain
Problem

@Hossain
Solution Machine Code
Assembly Code

@Hossain
Logic Instructions

@Hossain
CMA

If,
A= 25H or

00100101
Then,
after executing CMA
A=11011010

@Hossain
ANA and
ORA

@Hossain
ANA and
ORA

@Hossain
ANI

@Hossain
ORI

@Hossain
XRI

@Hossain
JUMP and CALL
Instructions

@Hossain
JMP

@Hossain
JMP

@Hossain
JM, JZ, JNZ

@Hossain
@Hossain
@Hossain
CALL and
RET
 C ALL 5000H : Call
the subroutine
starting from 5000H
 RET : return, Have to
return to the address
next to the address
where CALL 5000H
was stored
 CALL is
unconditional

@Hossain
CALL and
RET
 When CALL is
executed, the content
of PC is
automatically saved
in memory locations
FFFEH and FFFFH
 Infinite Loop?

@Hossain
Problem

@Hossain
Solution

@Hossain
Assembly version

@Hossain
Problem

@Hossain
Solution

@Hossain
Problem

@Hossain
Solution

@Hossain
Other
Instructions

@Hossain
NOP

HL
T
@Hossain
IN

@Hossain
OUT

@Hossain
RAR and RAL

@Hossain
Problem

@Hossain
Solution

@Hossain
Calculation of
Execution Time of
a Program

@Hossain
Problem

@Hossain
Solution
Total Time:

@Hossain
Problem

@Hossain
Solution
Inner

Loop

Tota
l
Time

@Hossain
Discussion

@Hossain

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