Digital Design: A System Approach, 2012
Book Organization
(Textbook : Caltech, MIT, Stanford)
1
다룰 내용
Chap. 1, 2
Chap. 3, 4, 6, 7, 8, 9
보조자료 1, Chap.14, 15, 16, 18, 19
보조자료 2, 3, 4, Chap.12
Chap. 20
Chap. 28, 29
3
PART I Introduction
Chap 1 The digital abstraction
Chap 2 The practice of digital system design
4
Chap 1 The Digital Abstraction
1.1 Digital signals
1.2 Digital signal tolerate noise
1.3 Digital signals represent complex data
1.3.1 Representing the day of year
1.3.2 Representing subtractive colors
1.4 Digital logic functions
1.5 Verilog description of digital circuits and systems
1.6 Digital logic in system
5
Chap 2 The Practice of Digital System Design
2.1 The design process
2.1.1 Specification
2.1.2 Concept of development and feasibility
2.1.3 Partitioning and detailed design
2.1.4 Verification
2.2 Digital systems are built from chips and boards
2.3 Computer-aided design tools
2.4 Moore's law and digital system evolution
6
PART II Combinational Logic
Chap 3 Boolean Algebra
Chap 4 CMOS Logic Circuits
Chap 5 Delay and Power of CMOS Circuits
Chap 6 Combinational Logic Design
Chap 7 Verilog Description of Combinational Logic
Chap 8 Combinational Building Blocks
Chap 9 Combinational Examples
7
Chap 3 Boolean Algebra
3.1 Axioms
3.2 Properties
3.3 Dual functions
3.4 Normal forms
3.5 From equations to gates
3.6 Boolean expressions in Verilog
8
Chap 4 CMOS Logic Circuits
4.1 Switch logic
4.2 Switch model of MOS transistors
4.3 CMOS gate circuits
4.3.1 Basic CMOS gate circuit
4.3.2 Inverter, NANDs, and NORs
4.3.3 Complex gates
4.3.4 Tri-state circuits
4.3.5 Circuits to avoid
9
Chap 6 Combinational Logic Design
6.1 Combinational logic
6.2 Closure
6.3 Truth table, min-terms, and normal form
6.4 Implicants and cubes
6.5 Karnaugh maps
6.6 Covering a function
6.7 From a cover to gates
6.8 Incompletely specified functions
6.9 Product-of-sum implementation
6.10 Hazards
10
Chap 7 Verilog Description of Combinational Logic
7.1 The prime number circuit in Verilog
7.1.1 A Verilog module
7.1.2 The case statement
7.1.3 The casex statement
7.1.4 The assign statement
7.1.5 Structural description
7.1.6 The decimal prime number function
7.2 A testbench for the prime number circuit
7.3 Example: a seven-segment decoder
11
Chap 8 Combinational Building Blocks
8.1 Multi-bit notation
8.2 Decoders
8.3 Multiplexers
8.4 Encoders
8.5 Arbiters and priority encoders
8.6 Comparators
8.7 Shifters
8.8 Read-only memories
8.9 Read-write memories
8.10 Programmable logic arrays
8.11 Data sheets
8.12 Intellectual property
12
Chap 9 Combinational Examples
9.1 Multiple-of-3 circuit
9.2 Tomorrow circuit
9.3 Priority arbiter
9.4 Tic-tac-toe
13
PART IV Synchronous Sequential Logic
보조자료1: Flip-flops
Chap 14 Sequential Logic
Chap 15 Timing Constraints
Chap 16 Datapath Sequential Logic
Chap 17 Factoring Finite-State Machine
Chap 18 Microcode
Chap 19 Sequential Examples
14
Chap 14 Sequential Logic
14.1 Sequential circuits
14.2 Synchronous sequential circuits
14.3 Traffic-light controller
14.4 State assignment
14.5 Implementation of finite-state machine
14.6 Verilog implementation of finite-state machines
15
Chap 15 Timing Constraints
15.1 Propagation and contamination delay
15.2 The D flip-flop
15.3 Setup- and hold-time constraints
15.4 The effect of clock skew
15.5 Timing examples
15.6 Timing and logic synthesis
16
Chap 16 Datapath Sequential Logic
16.1 Counters
16.1.1 A simple counter
16.1.2 Up/down/load counter
16.1.3 A timer
16.2 Shift registers
16.2.1 A simple shift register
16.2.2 Left/right/load (LRL) shift register
16.2.3 Universal shifter/counter
16.3 Control and data partitioning
16.3.1 Example: vending machine FSM
16.3.2 Example: combinational lock
17
Chap 19 Sequential Examples
19.1 Divide-by-3 counter
19.2 SOS detector
19.3 Tic-tac-toe game
19.4 Huffman encoder/decoder
19.4.1 Huffman encoder
19.4.2 Huffman decoder
18
PART III Arithmetic Circuits
보조자료 2: Number systems
보조자료 3: 연산 회로 – FA 기반
보조자료 4: 연산 회로 – P&G 기반
Chap 10 Arithmetic Circuits
Chap 11 Fixed and Floating-point Numbers
Chap 12 Fast Arithmetic Circuits
Chap 13 Arithmetic Examples
19
Chap 12 Fast Arithmetic Circuits
12.1 Carry look-ahead
12.2 Booth recoding
12.3 Wallace trees
12.4 Synthesis notes
20
PART V Practical Design
Chap 20 Verification and Test
21
Chap 20 Verification and Test
20.1 Design verification
20.1.1 Verification coverage
20.1.2 Types of tests
20.1.3 Static timing analysis
20.1.4 Formal verification
20.1.5 Bug tracking
20.2 Test
20.2.1 Fault models
20.2.2 Combinational testing
20.2.3 Testing redundant logic
20.2.4 Scan
20.2.5 Built-in-self-test (BIST)
20.2.6 Characterization
22
PART VII Asynchronous Logic
26 Asynchronous Sequential Circuits
27 Flip-flops
28 Metastability and Synchronization Failure
29 Synchronizer Design
23
Chap 28 Metastability and Synchronization Failure
28.1 Synchronization failure
28.2 Metastability
28.3 Probability of entering and leaving an illegal state
28.4 Demonstration of metastability
24
Chap 29 Synchronizer Design
29.1 Where are synchronizer used?
29.2 Brute-force synchronizer
29.3 The problem with multi-bit signals
29.4 FIFO synchronizer
25
