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CH 7

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20 views14 pages

CH 7

Uploaded by

sifbdd
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Logic Circuit

(디지털 논리회로)
Interview
Lecture 7: Multi-Level Gate Circuits NAND and NOR Gates

SungHoon Lim
Department of Electrical Engineering
Jeonbuk National University
Minimum Forms

Multi-Level Gate Circuits (다단 게이트 회로)


✓ Number of levels of gates: Maximum number of gates cascaded in
series between a circuit input and the output
✓ Z is composed with four levels, six gates, and 13 gate inputs

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Minimum Forms

Multi-Level Gate Circuits (다단 게이트 회로)


✓ Example:
→ Consider solutions with two levels of gates and three levels of gates
→ Try to minimize the number of gates and the total number of gate inputs
→ Assume that all variables and their complements are available as inputs

Simplify f by using Karnaugh map

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Minimum Forms

Multi-Level Gate Circuits (다단 게이트 회로)


✓ Example:
• 2 levels
• 5 gates
• 16 gate inputs
• AND-OR gate circuit
Factoring (인수분해) OR gate at the output

• 3 levels
• 5 gates
• 12 gate inputs
• OR-AND-OR gate circuit

• Transform to OR-AND circuit


• (Place AND gate at the end) → Every factor needs to be multiplied (product-of-sums – 곱의 형태로)
• Obtain f’ in sum-of-products (합의 형태) then f will be in form of product-of-sums (곱의 형태)

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Minimum Forms

Multi-Level Gate Circuits (다단 게이트 회로)


✓ Example:

• 2 levels
• 5 gates
• 14 gate Inputs
• OR-AND circuit
Use (X + Y)(X + Z) = X + YZ

• 3 levels
• 7 gates
• 16 gate Inputs
• AND-OR-AND circuit

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Minimum Forms

Multi-Level Gate Circuits (다단 게이트 회로)


✓ Best two-level solution had an AND gate at the output
✓ Best three-level solution had an OR gate at the output

AND gate at the output OR gate at the output

• 3 levels
• 2 levels • 5 gates
• 5 gates • 12 gate Inputs
• 14 gate Inputs

✓ In general, to be sure of obtaining a minimum solution, one must find


both the circuit with the AND-gate output and the one with the OR-
gate output

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Minimum Forms

NAND and NOR Gates


✓ NAND gate (AND-NOT gate) definition:
✓ Output of the n-input NAND gate:

Three-input NAND gate NAND gate equivalent n-input NAND gate

✓ NOR gate (OR-NOT gate) definition:


✓ Output of the n-input NAND gate:

Three-input NOR gate NOR gate equivalent n-input NOR gate

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Minimum Forms

Design of Two-Level NAND and NOR-Gate Circuits


✓ AND-OR form
NAND-NAND form
OR-NAND form
NOR-OR form

We can obtain minimum product of Example using f’


sums from a Karnaugh map

NOR-NOR form
AND-NOR form
NAND-AND form

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Minimum Forms

Design of Two-Level NAND and NOR-Gate Circuits

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Minimum Forms

Designing a Minimum Two-Level NAND-NAND Circuit


1. Find a minimum sum-of-products expression for F
2. Draw the corresponding two-level AND-OR circuit
3. Replace all gates with NAND gates leaving the gate interconnections
unchanged. If the output gate has any single literals as inputs,
complement these literals
✓ Example:
Apply DeMorgan’s law

Designing a Minimum Two-Level NOR-NOR Circuit


1. Find a minimum product-of-sums expression for F
2. Draw the corresponding two-level OR-AND circuit
3. Replace all gates with NOR gates ~~

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Minimum Forms

Design of Multi-Level NAND Circuits


1. Simplify the switching function to be realized.
2-1. Design a multi-level circuit. The output gate must be OR gate.
2-2. AND gate outputs cannot be used as AND-gate inputs & OR-gate
outputs cannot be used as OR-gate inputs.
3. Replace all gates with NAND gates. Leave the inputs to levels 2, 4, 6, . . .
unchanged. Invert any literals which appear as inputs to levels 1, 3, 5, . . .
✓ Example:

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Minimum Forms

Circuit Conversion Using Alternative Gate Symbols


✓ NOT gate (inverter):
✓ AND, OR, NAND, and NOR gates

✓ NAND Gate Circuit Conversion

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Minimum Forms

Designing a Minimum two-level NAND-NAND circuit


1-1. Convert all AND gates to NAND gates by adding an inversion bubble
at the output.
1-2. Convert all OR gates to NAND gates by adding inversion bubbles at
the inputs.
2. Whenever an inverted output drives an inverted input, the two
inversions cancel
3. Insert an inverter to cancel the bubbles for inversion output and input
✓ Example:
AND-OR circuit

Bubble cancels

NAND transform

Add an inverter Add an inverter

Completed form

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Minimum Forms

Design of Two-Level, Multiple-Output Circuits


✓ Use of some gates in common between two or more functions
sometimes leads to a more economical realization

- CD = ACD+A’CD
- AB is repeated

Seven gates and 18 gate inputs


Nine gates and 21 gate inputs

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