21ECC211L – DEVICES AND DIGITAL IC

LABORATORY MANUAL

SEMESTER - III

SRM Institute of Science &

Technology
RAMAPURAM CAMPUS

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

2021 REGULATION

Name: .........................................................................

Register No.: ...............................................................

Class / Sec: ..................................................................

 21ECC211L – DEVICES AND DIGITAL IC LAB

LIST OF EXPERIMENTS

S.NO TITLE OF THE EXPERIMENT

DEVICES LAB

1 CHARACTERISTICS OF PN JUNCTION DIODE

2 CHARACTERISTICS OF ZENER DIODE

3 CHARACTERISTICS OF BJT (CE CONFIGURATION)

4 SINGLE PHASE HALF WAVE RECTIFIER

5 SINGLE PHASE FULL WAVE RECTIFIER

6 CLIPPERS

DIGITAL IC LAB

7 STUDY OF LOGIC GATES

8 DESIGN OF ADDER AND SUBTRACTOR

9 DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER

10 DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

11 STUDY OF FLIP FLOPS

12 DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS

UP/DOWN COUNTER
 INDEX
EXP. NO DATE NAME OF THE EXPERIMENT PAGE MARKS SIGNATURE
NO
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Experiment No. 1
CHARACTERISTICS OF PN JUNCTION DIODE
Date :

Aim
To study the characteristics of PN Junction diode under forward and reverse bias
conditions.

Apparatus Required Components Required

S.No. Name Range Qty S.No. Name Range Qty

1 R.P.S (0-30)V 1 1 Diode IN4001 1

(0–30)mA 1 2 Resistor 1k 1

2 Ammeter Bread
(0-500)µA 1 3 - 1
Board
(0–1)V 1 connecting
3 Voltmeter 4 - Req
(0-10)V 1 Wires

Theory
A PN junction diode is a two terminal semiconducting device. It conducts only in
one direction (only on forward biasing).
Forward Bias
On forward biasing, initially no current flows due to barrier potential. As the applied
potential exceeds the barrier potential the charge carriers gain sufficient energy to cross
the potential barrier and hence enter the other region. The holes, which are majority
carriers in the P-region, become minority carriers on entering the N-regions, and electrons
which are the majority carriers in the N-region, become minority carriers on entering the
P-region. This injection of minority carriers results in the current flow, opposite to the
direction of electron movement.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Reverse Bias
On reverse biasing, the majority charge carriers are attracted towards the terminals
due to the applied potential resulting in the widening of the depletion region. Since the
charge carriers are pushed towards the terminals no current flows in the device due to
majority charge carriers. There will be some current in the device due to the thermally
generated minority carriers. The generation of such carriers is independent of the applied
potential and hence the current is constant for all increasing reverse potential. This current
is referred to as Reverse Saturation Current (IO) and it increases with temperature. When
the applied reverse voltage is increased beyond the certain limit, it results in breakdown.
During breakdown, the diode current increases tremendously.

Procedure
Forward Bias
1. Connect the circuit as per the diagram.
2. Vary the applied voltage V in steps of 0.1V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I

Observations
1. Find the d.c (static) resistance = V/I.
V2  V1
2. Find the a.c (dynamic) resistance r = V / I (r = V/I) = .
I 2  I1
3. Find the forward voltage drop [Hint: it is equal to 0.7 for Si and 0.3 for Ge]

Reverse Bias
1. Connect the circuit as per the diagram.
2. Vary the applied voltage V in steps of 1.0V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
5. Find the dynamic resistance r = V / I.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Formula for Reverse Saturation Current (IO):

I  I 0 (eV /VT 1)

where I is forward (or reverse) diode current, I0 is reverse saturation current, V is external
voltage (+ve for forward bias & -ve for reverser bias),  is constant number (1 for Silicon
and 2 for Germanium), VT is the volt-equivalent of temperature (T/11600) and T is
temperature in Kelvin.
Circuit Diagram
Forward Bias

Specification for 1N4001: Silicon Diode

Peak Inverse Voltage: 50V
Idc = 1A.
Maximum forward voltage drop at 1 Amp is 1.1 volts
Maximum reverse current at 50 volts is 5A
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Tabular Column

Forward Bias Reverse Bias

S.No. Voltage Current S.No. Voltage Current

(In Volts) (In mA) (In Volts) (In A)

Result
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Experiment No. 2 CHARACTERISTICS OF ZENER DIODE

Date :

Aim
To find the forward and reverse bias characteristics of a given Zener diode.

Apparatus Required Components Required

S.No. Name Range Qty S.No. Name Range Qty
Zener
1 R.P.S (0-30)V 1s 1 FZ5.1 1
diode
2 Resistor 1K 1
2 Ammeter (0–30)mA 2 Bread
3 - 1
Board
(0–10)V 1
3 Voltmeter 4 Wires - Req
(0–1)V 1

Theory
A properly doped crystal diode, which has a sharp breakdown voltage, is known as Zener
diode.
Forward Bias
On forward biasing, initially no current flows due to barrier potential. As the
applied potential increases, it exceeds the barrier potential at one value and the charge
carriers gain sufficient energy to cross the potential barrier and enter the other region. The
holes, which are majority carriers in p-region, become minority carriers on entering the N-
regions and electrons, which are the majority carriers in the N-regions become minority
carriers on entering the P-region. This injection of minority carriers results current,
opposite to the direction of electron movement.
Reverse Bias
When the reverse bias is applied, due to majority carriers small amount of current
(i.e.,) reverse saturation current flows across the junction. As the reverse bias is increased
to breakdown voltage, sudden rise in current takes place due to Zener effect.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Zener Effect
Normally, PN junction of Zener Diode is heavily doped. Due to heavy doping the
depletion layer will be narrow. When the reverse bias is increased the potential across the
depletion layer is more. This exerts a force on the electrons in the outermost shell.
Because of this force the electrons are pulled away from the parent nuclei and become free
electrons. This ionization, which occurs due to electrostatic force of attraction, is known
as Zener effect. It results in large number of free carriers, which in turn increases the
reverse saturation current.

Procedure
Forward Bias
1. Connect the circuit as per the circuit diagram.
2. Vary the power supply in such a way that the readings are taken in steps of 0.1V in
the voltmeter till the needle of power supply shows 30V.
3. Note down the corresponding ammeter readings.
4. Plot the graph between V & I.
5. Find the dynamic resistance r = V / I.
Reverse Bias
1. Connect the circuit as per the diagram.
2. Vary the power supply in such a way that the readings are taken in steps of 0.1V in
the voltmeter till the needle of power supply shows 30V.
3. Note down the corresponding Ammeter readings I.
4. Plot a graph between V & I
5. Find the dynamic resistance r = V / I.
6. Find the reverse voltage Vr at Iz=20 mA.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Circuit Diagram
Forward Bias
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Tabular Column
Forward Bias Reverse Bias

S.No. Voltage Current S.No. Voltage Current

(In Volts) (In mA) (In Volts) (In mA)

Result
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Experiment No. 3 CHARACTERISTICS OF BJT (CE CONFIGURATION)

Date :

Aim
To plot the transistor (BJT) characteristics of CE configuration.

Apparatus Required Components Required

S.No. Name Range Qty S.No. Name Range Qty
1 R.P.S (0-30)V 2 1 Transistor BC 107 1
(0–30) mA
1 Resistor 10 K 1
MC
2 Ammeter 2
(0–250) µA
1 Resistor 1 K 1
MC
(0–30)V Bread
1 3 1
MC Board
3 Voltmeter
(0–1)V
1 4 Wires
MC

Theory

A BJT is a three terminal two – junction semiconductor device in which the

conduction is due to both the charge carrier. Hence it is a bipolar device. BJT is classified
into two types – NPN & PNP. A NPN transistor consists of two N types in between which
a layer of P is sandwiched. The transistor consists of three terminal emitter, collector and
base. The emitter layer is the source of the charge carriers and it is heavily doped with a
moderate cross sectional area. The collector collects the charge carries and hence
moderate doping and large cross sectional area. The base region acts a path for the
movement of the charge carriers. In order to reduce the recombination of holes and
electrons the base region is lightly doped and is of hollow cross sectional area. Normally
the transistor operates with the EB (emitter-base) junction forward biased.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Procedure

Input Characteristics

1. Connect the circuit as per the circuit diagram.

2. Set VCE, vary VBE in regular interval of steps and note down the corresponding IB
reading. Repeat the above procedure for different values of VCE.
3. Plot the graph: VBE Vs IB for a constant VCE.
Output Characteristics

1. Connect the circuit as per the circuit diagram.

2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC
reading. Repeat the above procedure for different values of IB.
3. Plot the graph: VCE Vs IC for a constant IB.

Pin Diagram

Specification: BC107/50V/0.1A,0.3W,300 MH

Circuit Diagram
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Model Graph

Input Characteristics Output Characteristics

µA
mA

IC
IB
VCE = 0V
VCE = 5V
IB=60A

IB=40A

IB=20A

0
VBE(V) 0
VCE(V)

Tabular Column
Input Characteristics

VCE = 0 V VCE = 2V
VBE(V) IB(μA) VBE(V) IB(μA)
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Output Characteristics
IB=20A IB=40A

Result
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Experiment No. 4 SINGLE PHASE HALF WAVE RECTIFIER

Date :
Aim
To construct a half wave rectifier using diode and to draw its performance characteristics.
Apparatus Required Components Required
S. S.
Name Range Qty Name Range Qty
No. No.
1 Transformer 230/(6-0-6)V 1 Diode IN4007
1 1

2 Resistor 1K  1
2 R.P.S (0-30)V 2 Bread
3 - 1
Board
4 Capacitor 100µf 1
5 CRO - 1

Formulae

Without Filter
(i) Vrms = Vm / 2
(ii) Vdc = Vm / 𝜋
2
 Vrms 
(iii) Ripple Factor =   1
 Vdc 

(iv) Efficiency = (Vdc / Vrms)2 x 100

With Filter
2 2
(i) Vrrms = Vrms  Vdc

(ii) Vrms = Vrpp / (3 x 2), where Vrpp is peak to peak value of ripple voltage
(iii) Vdc = Vm – 0.5*V rpp
(iv) Ripple Factor = Vrms / Vdc
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Procedure
Without Filter
1. Give the connections as per the circuit diagram.
2. A 230 V, 50 Hz AC input given to primary side of the transformer where phase
end of the secondary is connected to anode terminal of the diode.
3. Observe the output across the 1 K ohm load with use of CRO.
4. Plot its performance graph.

With Filter
1. Connections made as per the circuit diagram.
2. A 230 V, 50 Hz AC input given to primary side of the transformer where phase
end of the secondary is connected to anode terminal of the diode.
3. Connect the Capacitor across the 1 K Ohm load
4. Observe the output across the 1 K Ohm load with use of CRO.
5. Plot its performance graph.
Circuit Diagram

Tabular Column
Without Filter
Vm (V) Vrms (V) Vdc (V) Ripple factor Efficiency

With Filter
Vrpp (V) Vrms (V) Vdc (V) Ripple factor
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Model Graph

Vin
(Volts)

t (ms)

Vo
(Volts) Without Filter

t (ms)
Vo
(Volts) With Filter

t (ms)

Result
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Experiment No. 5 SINGLE PHASE FULL WAVE RECTIFIER

Date :

Aim
To construct a single phase full-wave rectifier using diode and draw its
performance characteristics.

Apparatus Required Components Required

S. S.
Name Range Qty Name Range Qty
No. No.
1 Transformer 230/(6-0-6)V 1 Diode IN4007
1 2

2 Resistor 1K  1
Bread
3 - 1
2 R.P.S (0-30)V 2 Board
4 Capacitor 100µf 1
1Hz-
5 CRO 1
20MHz
Connecting
6 - Req
wires

Formulae
Without Filter
(i) Vrms = Vm / 2
(ii) Vdc = 2Vm / 𝜋
2
 Vrms 
(iii) Ripple Factor =   1
 Vdc 

(iv) Efficiency = (Vdc / Vrms)2 x 100

With Filter
(i) Vrms = Vrpp /(2* 3)
(ii) Vdc = Vm – V rpp
(iv) Ripple Factor = Vrms’/ Vdc
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Procedure
Without Filter
1. Give the connections as per the circuit diagram.
2. A 230 V, 50 Hz AC input given to primary side of the transformer where the
phases end of the secondary is connected to anode terminal of the diode.
3. Observe the output across the 1 K ohm load with use of CRO.
4. Plot its performance graph.

With Filter
1. Give the connections as per the circuit diagram.
2. A 230 V, 50 Hz AC input given to primary side of the transformer where the
phases end of the secondary is connected to anode terminal of the diode.
3. Connect the Capacitor across the load.
4. Observe the output across the 1 K ohm load with use of CRO.
5. Plot its performance graph.

Circuit Diagram

Tabular Column
Without Filter
Vm Vrms Vdc Ripple factor Efficiency
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

With Filter
Vrms Vrpp Vdc Ripple factor

Model Graph

Vin
(Volts)

t (ms)

Vo
(Volts) Without Filter

t (ms)
Vo
(Volts) With Filter

t (ms)

Result:
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Experiment No. 6 CLIPPERS

Date :

Aim
To study the clipping circuits for different reference voltages and to verify the
responses.

Apparatus Required Components Required

S.No. Name Range Qty S.No. Name Range Qty
1 CRO 1Hz-20MHz 1
2 RPS (0–30) V 1
1 Resistor 10KΩ 1
Bread
3 - 1
Board
Connecting
4 - Req
Wires
2 Diode IN4007 1
Function
5 1Hz-1MHz 1
Generator

Theory
The non-linear semiconductor diode in combination with resistor can function as
clipper circuit. Energy storage circuit components are not required in the basic process of
clipping. These circuits will select part of an arbitrary waveform which lies above or below
some particular reference voltage level and that selected part of the waveform is used for
transmission. So they are referred as voltage limiters, current limiters, amplitude selectors or
slicers. There are three different types of clipping circuits.
1) Positive Clipping circuit.
2) Negative Clipping.
3) Positive and Negative Clipping (slicer).
In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negative
portion of sinusoidal signal is obtained in the output of reference voltage is added, instead of
complete positive cycle that portion of the positive cycle which is above the reference
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

voltage value is clipped. In negative clipping circuit instead of positive portion of sinusoidal
signal, negative portion is clipped. In slicer both positive and negative portions of the
sinusoidal signal are clipped.

Procedure

1. Connect the circuit as shown in the circuit diagram.

2. Connect the function generator at the input terminals and CRO at the output terminals of
the circuit.
3. Apply a sine wave signal of frequency 1 KHz, Amplitude greater than the reference
voltage at the input and observe the output waveforms of the circuits.
Circuit Diagram

Positive Clipper
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Negative Clipper

Tabulation:
Positive Clipper Negative Clipper

Unbiased Clipper
Vref = 0V Vref = 0V
Output voltage Time Period Output voltage Time Period
(V) (ms) (V) (ms)

Biased Clipper
Vref = 2V Vref = 2V
Output voltage Time Period Output voltage Time Period
(V) (ms) (V) (ms)
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

Result :
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

EXPT N O : STUDY OF LOGIC GATES

DATE :

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates.
Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs is
low.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

OR GATE:

The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low
and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The
output is low when one or both inputs are high.

X- OR GATE:

The output is high when any one of the inputs is high. The output is low when both the inputs
are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

21ECC211L – DEVICES AND DIGITAL IC LABORATORY
2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

NOR GATE:

RESULT:
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

EXPT NO. : DESIGN OF ADDER AND SUBTRACTOR

DATE :

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’
and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND
gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of
three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot
do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR
Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two
input and two outputs. The outputs are difference and borrow. The difference can be applied using X-
OR Gate, borrow output can be implemented using an AND Gate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together gives a
full subtractor. The first half subtractor will be C and A
B. The output will be difference output of full subtractor. The expression AB assembles the borrow
output of the half subtractor and the second term is the inverted difference output of first X-OR.
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

K-Map for CARRY:

CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY
K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

LOGIC DIAGRAM:
FULL SUBTRACTOR
 21ECC211L – DEVICES AND DIGITAL IC LABORATORY

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + ABC

 Borrow = A’B + BC + A’C

PROCEEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates and
study of IC 74150 and IC 74154.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line. The selection of a particular input line is

controlled by a set of selection lines. Normally there are 2 n input line and n selection lines whose bit
combination determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes information from
one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also
known as a data distributor. Decoder can also be used as demultiplexer.

2018-19/ODD/III/ECE/15EC203J/DS/LM Page. 41
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data
select lines enable only one gate at a time and the data on the data input line will pass through the
selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2
1 1 D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0
0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:
To design and implement encoder and decoder using logic gates and study of IC
7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2 n
input lines and n output lines. In encoder the output lines generates the binary code corresponding to
the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output
that generate the corresponding binary code. In encoder it is assumed that only one input has a value
of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs
are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input into
coded output where input and output codes are different. The input code generally has fewer bits than
the output code. Each input code word produces a different output code word i.e there is one to one
mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded

information is present as n input producing 2n possible outputs. 2n output values are from 0 through

out 2n – 1.

PIN DIAGRAM FOR IC 7445: BCD

TO DECIMAL DECODER:
PIN DIAGRAM FOR IC 74147:
LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1
LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1
0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0
PROCEDURE:
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:
 EXPT NO. :
DATE :
STUDY OF FLIPFLOPS
AIM:

To construct and study the operations of the following circuits: (i) RS and Clocked RS Flip-Flop (ii) D Flip-Flop
(iii) JK and Master-Slave JK Flip-Flop (iv) T Flip-Flop

THEORY:

In many instances it is desirable to have the next output depending on the current output. A simple example is a
counter, where the next number to be output is determined by the current number stored. Circuits that remember
their current output or state are often called sequential logic circuits. Clearly, sequential logic requires the ability to
store the current state. In other words, memory is required by sequential logic circuits, which can be created with
boolean gates. If you arrange the gates correctly, they will remember an input value. This simple concept is the
basis of RAM (random access memory) in computers, and also makes it possible to create a wide variety of other
useful circuits.
The memory elements in these circuits are called flip-flops. A flip-flop circuit has two outputs, one for the normal
value and one for the complement value of the stored bit. Binary information can enter a flip-flop in a variety of
ways and gives rise to different types of flip-flops.

CIRCUIT DIAGRAM:

SR Flip Flop:
 EXPT NO. :

Characteristic Table:

Present Next
Inputs
State State
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 x
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 x
JK Flip-Flop:

JK Flip-Flop has two inputs J(set) and K(reset). A JK Flip-Flop can be obtained from the clocked SR Flip-Flop by
augmenting two AND gates.

Characteristic Table:

Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
 EXPT NO. :

D Flip Flop:

To eliminate the undesirable condition of the indeterminate state in the RS Flip-Flop. D Flip-Flop is used. The D
(delay) Flip-Flop has one input called delay input and clock pulse input.

Characteristic Table:

Qn D Qn+1

0 0 0
0 1 1
1 0 0
1 1 1

T Flip-Flop:
The T (Toggle) Flip-Flop is a modification of the JK Flip-Flop. It is obtained from JK Flip-Flop by connecting both
inputs J and K together, i.e., single input.The Flip-Flop complements its output when the clock pulse occurs while input T=
1.
EXPT NO. :

Chacteristic Table:

Qn T Qn+1

0 0 0
0 1 1
1 0 1
1 1 0

RESULT:
EXPT NO. :

DATE :

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bidirectional counter. Usually up/down operation of the counter is controlled by
up/down signal. When this signal is high counter goes through up sequence and when up/down signal
is low counter follows reverse sequence.
K MAP

STATE DIAGRAM:
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:
 Input Present State Next State A B C
Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT: