7 segment
module seg7decoder (input [3:0] data, output reg [6:0] segments);
parameter BLANK = 7'b000_0000;
parameter ZERO = 7'b111_1110;
parameter ONE = 7'b011_0000;
parameter TWO = 7'b110_1101;
parameter THREE = 7'b111_1001;
parameter FOUR = 7'b011_0011;
parameter FIVE = 7'b101_1011;
parameter SIX = 7'b101_1111;
parameter SEVEN = 7'b111_0000;
parameter EIGHT = 7'b111_1111;
parameter NINE = 7'b111_1011;
always @(*) begin
case(data)
4'b0000: segments = ZERO;
4'b0001: segments = ONE;
4'b0010: segments = TWO;
4'b0011: segments = THREE;
4'b0100: segments = FOUR;
4'b0101: segments = FIVE;
4'b0110: segments = SIX;
4'b0111: segments = SEVEN;
4'b1000: segments = EIGHT;
4'b1001: segments = NINE;
default: segments = BLANK;
endcase
end
endmodule
testbench:-
module seg7decoder_tb;
reg [3:0] data; // BCD input
wire [6:0] segments; // 7-segment display output
// Instantiate the Unit Under Test (UUT)
seg7decoder uut (
.data(data),
.segments(segments)
);
initial begin
$monitor("BCD Input = %b, 7-Segment Output = %b", data, segments);
// Test all BCD values from 0 to 9
data = 4'b0000; #20;
data = 4'b0001; #20;
data = 4'b0010; #20;
data = 4'b0011; #20;
data = 4'b0100; #20;
data = 4'b0101; #20;
data = 4'b0110; #20;
data = 4'b0111; #20;
data = 4'b1000; #20;
data = 4'b1001; #20;
// Test default case (invalid input)
data = 4'b1010; #20;
data = 4'b1111; #20;
$finish;
end
endmodule
XDC:-
##Switches
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { data[0] }];
#IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { data[1] }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { data[2] }];
#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { data[3] }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]
##7 segment display
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { segments[0] }];
#IO_L4P_T0_35 Sch=seg[0] (segment a)
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { segments[1] }];
#IO_L19P_T0_35 Sch=seg[1] (segment b)
set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { segments[2] }];
#IO_L18P_T1_35 Sch=seg[2] (segment c)
set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { segments[3] }];
#IO_L19P_T1_35 Sch=seg[3] (segment d)
set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { segments[4] }];
#IO_L16P_T2_35 Sch=seg[4] (segment e)
set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { segments[5] }];
#IO_L16N_T1_35 Sch=seg[5] (segment f)
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { segments[6] }];
#IO_L14N_T2_35 Sch=seg[6] (segment g)
