Manual

【Instruction】
Chapter 1 PLC Ladder Diagram and the Coding Rules of Mnemonic

In this chapter, we would like to introduce you the basic principles of ladder diagram, in addition, the coding rules of
mnemonic will be introduced as well, it's essential for the user who use FP-07C as a programming tool. If you are familiar
with PLC Ladder Diagram and mnemonic coding rules, you may skip this chapter.
1.1 The Operation Principle of Ladder Diagram
Ladder Diagram is a type of graphic language for automatic control systems it had been used for a long period since World
War II. Until today, it is the oldest and most popular language for automatic control systems. Originally there are only few
basic elements available such as A-contact (Normally ON), B contact (Normally OFF), output Coil, Timers and Counters.
Not until the appearance of microprocessor based PLC, more elements for Ladder Diagram, such as differential contact,
retentive coil (refer to page 1-6) and other instructions that a conventional system cannot provide, became available.
The basic operation principle for both conventional and PLC Ladder Diagram is the same. The main difference between the
two systems is that the appearance of the symbols for conventional Ladder Diagram are more closer to the real devices,
while for PLC system, symbols are simplified for computer display. There are two types of logic system available for Ladder
Diagram logic, namely combination logic and sequential logic. Detailed explanations for these two logics are discussed
below.
1.1.1 Combination Logic
Combination logic of the Ladder Diagram is a circuit that combines one or more input elements in series or parallel and then
send the results to the output elements, such as Coils, Timers/Counters, and other application instructions.
Actual wiring diagram

AC110V
AC110V
X0
X0 Y0
Y0
Circuit 1
NO(A)
NC(A)
X1 Y1
X1 Y1
Circuit 2
NC(B)
NC(B)
X2 X4
X4 Y2
Y2
X2
Circuit 3
NC NO
NC NO
X3
X3
NO
NO
1-1
Conventional Ladder Diagram PLC Ladder Diagram
X0 Y0 X0 Y0
circuit 1 circuit 1
X1 Y1 X1 Y1
circuit 2 circuit 2
X2 X4 X2 X4 Y2
Y2
circuit 3 circuit 3
X3
X3
The above example illustrated the combination logic using the actual wiring diagram, conventional Ladder Diagram, and
PLC Ladder Diagram. Circuit 1 uses a NO (Normally Open) switch that is also called "A" switch or contact. Under normal
condition (switch is not pressed), the switch contact is at OFF state and the light is off. If the switch is pressed, the contact
status turns ON and the light is on. In contrast, circuit 2 uses a NC (Normally Close) switch that is also called "B" switch or
contact. Under normal condition, the switch contact is at ON state and the light is on. If the switch is pressed, the contact
status turns OFF and the light also turns off.
Circuit 3 contains more than one input element. Output Y2 light will turn on under the condition when X2 is closed or X3
switches to ON, and X4 must switch ON too.
1.1.2 Sequential Logic
The sequential logic is a circuit with feedback control; that is, the output of the circuit will be feedback as an input to the
same circuit. The output result remains in the same state even if the input condition changes to the original position. This
process can be best explained by the ON/OFF circuit of a latched motor driver as shown in below.
Actual wiring diagram
AC110V
AC110V
~
Relay
Relay
STARTswitch
START switch STOP switch
STOP switch
Y3
X5
X5 X6
X6
NO
NO NC
NC Contact
Contact22
Contact 11
Contact
Motor
Motor
1-2
Conventional Ladder Diagram PLC Ladder Diagram
X5 X6 Y3 X5 X6 Y3
Y3 Y3
When we first connect this circuit to the power source, X6 switch is ON but X5 switch is OFF, therefore the relay Y3 is OFF.
The relay output contacts 1and 2 are OFF because they belong to A contact (ON when relay is ON). Motor does not run. If
we press down the switch X5, the relay turns ON as well as contacts 1and 2 are ON and the Motor starts. Once the relay
turns ON, if we release the X5 switch (turns OFF), relay can retain its state with the feedback support from contact 1 and it
is called Latch Circuit. The following table shows the switching process of the example we have discussed above.
X5 switch X6 switch
Motor（Relay）status
(NO) (NC)
c Released Released OFF

↓
d Pressed Released ON
↓
e Released Released ON
↓
f Released Pressed OFF
↓
g Released Released OFF
From the above table we can see that under different stages of sequence, the results can be different even the input
statuses are the same. For example, let’s take a look at stage c and stage e , X5 and X6 switches are both released, but
the Motor is ON (running) at stage e and is OFF (stopped) at stage c . This sequential control with the feedback of the
output to the input is a unique characteristic of Ladder Diagram circuit. Sometimes we call the Ladder Diagram a "Sequential
Control Circuit" and the PLC a "Sequencer”. In this section, we only use the A/B contacts and output coils as the example.
For more details on sequential instructions please refer to chapter 5 - "Introduction to Sequential Instructions."
1.2 Differences Between Conventional and PLC Ladder Diagram
Although the basic operation principle for both conventional and PLC Ladder Diagram are the same, but in reality, PLC uses
the CPU to emulate the conventional Ladder Diagram operations; that is, PLC uses scanning method to monitor the
statuses of input elements and output coils, then uses the Ladder Diagram program to emulate the results which are the
same as the results produced by the conventional Ladder Diagram logic operations. There is only one CPU, so the PLC has
to sequentially examine and execute the program from its first step to the last step, then returns to the first step again and
repeats the operation (cyclic execution). The duration of a single cycle of this operation is called the scan time. The scan
time varies with the program size. If the scan time is too long, then input and output delay will occur. Longer delay time may
cause big problems in controlling fast response systems. At this time, PLCs with short scan time are required. Therefore,
scan time is an important specification for PLCs. Due to the advance in microcomputer and ASIC technologies nowadays
the scan speed has been enhanced a great deal. A typical FBE-PLC takes approximately 0.33 ms for IK steps of contact.
The following diagram illustrates the scanning process of a PLC Ladder Diagram.
1-3
Input processing (Reading the
status of all external input terminals)
X0 X1 Y0
First
step
Y0
Cyclic execution
PLC sequentially executes
M100 X3 X10 Y1
the stored program and
gets new output results
(has not sent to external
terminals yet)
X100 M505 Y126
Last step
Output processing (Output the resulting

signals to external output terminals)
Besides the time scan difference mentioned above, the other difference between the conventional and PLC Ladder
Diagram is “Reverse flow” characteristic. As shown in the diagram below, if X0, X1, X4 and X6 are ON, and the remaining
elements are OFF. In a conventional Ladder Diagram circuit, a reverse flow route for output Y0 can be defined by the
dashed line and Y0 will be ON. While for PLC, Y0 is OFF because the PLC Ladder Diagram scans from left to right, if X3 is
off then CPU believes node “a” is OFF, although X4 and node “b” are all ON, since the PLC scan reaches X3 first. In other
words, the PLC ladder can only allow left to right signal flow while conventional ladder can flow bi-directional.
Reverse flow of conventional Ladder diagram
X0
X0 X1
X1 X2
X2 Y0
X3
X3 X4
X4 X5
X5
aa b
X6
1-4
1.3 Ladder Diagram Structure and Terminology
Sample Ladder Diagram
Element
Element Node
Node Parallel block
Parallel block Serial block
Serial block
Origin line
Origin line
X0
X0 X1 X2 X3 X4
X4 X5
X5 X6
X6 Y0
Y0
X7 X10
X10 X9 Y2
Y2
/
Branch
Branch
Network 1
Network
X10
X10 X11
X11
Y4
Y4
X12 Y4
Network 2
Network
M1
M1 X14 X20
X20 Y5
Y5
/
Y0
Y0 M6
M6
Network
Network 33
X16
X16
(Remark：The maximum size of FBs-PLC network is 16 rows×22 columns)
As shown above, the Ladder Diagram can be divided into many small cells. There are total 88 cells (8 rows X 11 columns)
for this example Ladder Diagram. One cell can accommodate one element. A completed Ladder Diagram can be formed by
connecting all the cells together according to the specific requirements. The terminologies related to Ladder Diagram are
illustrated below.
c Contact
Contact is an element with open or short status. One kind of contact is called "Input contact"(reference number prefix with X)
and its status reference from the external signals (the input signal comes from the input terminal block). Another one is
called "Relay contact" and its status reflects the status of relay coil (please refer to d). The relation between the reference
number and the contact status depends on the contact type. The contact elements provided by FB series PLC include: A
contact, B contact, up/down differential (TU/TD) contacts and Open/Short contacts. Please refer to f for more details.
d Relay
Same as the conventional relay, it consists of a Coil and a Contact as shown in the diagram below.
Y0 A
Y0 B
Relay coil COIL Relay contacts

Y0 TU
Y0
Y0 TD
1-5
We must energize the coil of relay first (using OUT instruction) in order to turn on the relay. After the coil is energized, its
contact status will be ON too. As shown in the example above, if Y0 turns ON, then the relay contact A is ON and contact B
is OFF, TU contact only turns ON for one scan duration and TD contact is OFF. If Y0 turns OFF, then the relay contact A is
ON and contact B is ON, TU contact is OFF and TD contact only turns ON for one scan duration (Please refer to chapter 5
“Introduction to Sequential Instructions” for operations of A,B,TU and TD contacts).
There are four types of FB-PLC relays, namely Y△△△（output relay）, M△△△△（internal relay）, S△△△（step relay）
and TR△△（temporary relay）. The statuses of output relays will be sent to the output terminal block.
e Origin-line: The starting line at the left side of the Ladder Diagram.
f Element: Element is the basic unit of a Ladder Diagram. An element consists of two parts as shown in the diagram below.
One is the element symbol which is called “OP Code” and another is the reference number part which is called
“Operand”.
Operand
X100 Y15
OP Code
Element type Symbol Mnemonic instructions Remark
A Contact □△△△△
（Normally OPEN） (ORG、LD、AND、OR) □△△△△ □ can be X、Y、M、S、
T、C（please refer to
B Contact □△△△△ (ORG、LD、AND、OR) NOT
section 3.2）
（Normally CLOSE） □△△△△
□△△△△ (ORG、LD、AND、OR) TU
Up Differential Contact
□△△△△
□ can be X、Y、M、S
□△△△△ (ORG、LD、AND、OR) TD
Down Differential Contact
□△△△△
Open Circuit Contact (ORG、LD、AND、OR) OPEN
Short Circuit Contact (ORG、LD、AND、OR) SHORT
□△△△△
Output Coil OUT □△△△△
□ can be Y、M、S
□△△△△
Inverse Output Coil OUT NOT □△△△△
Y△△△
Latching Output Coil OUT L Y△△△
L
Remark：please refer to section 3.2 for the ranges of X、Y、M、S、T and C contacts. Please refer to section 5.2 for the
characteristics of X、Y、M、S、T and C contacts.
There are three special sequential instructions, namely OUT TRn, LD TRn and FOn, which were not displayed on the
Ladder Diagram. Please refer to section 1.6 “Using the Temporary Relay” and section 5.1.4 “Function Output FO”.
1-6
g Node: The connection point between two or more elements（please refer to section 5.3）
h Block: a circuit consists of two or more elements.

There are two basic types of blocks:
• Serial block：Two or more elements are connected in series to form a single row circuit.
Example:
• Parallel block: Parallel block is a type of a parallel closed circuit formed by connecting elements or serial blocks in
parallel.
Example:
Remark: Complicated block can be formed by the combination of the single element, serial blocks and parallel
blocks. When design a Ladder Diagram with mnemonic entry, it is necessary to break down the circuits into
element, serial, and parallel blocks. Please refer to section 1.5.
i Branch: In any network, branch is obtained if the right side of a vertical line is connected with two or more rows of circuits.
Example:
Branch
Merge line is defined as another vertical line at the right side of a branch line that merges the branch circuits into a
closed circuit (forming a parallel block). This vertical line is called “Merge line”.
Branch line Merge line
If both the right and the left sides of the vertical line are connected with two or more rows of circuits, then it is both a
branch line and a merge line as shown in the example below.
Example:
Parallel block 1 Parallel block 2
Block 1 merge line Block 2 branch line
1-7
j Network: Network is a circuit representing a specified function. It consists of the elements, branches, and blocks.
Network is the basic unit in the Ladder Diagram which is capable of executing the completed functions, and the
program of Ladder Diagram is formed by connecting networks together. The beginning of the network is the
origin line. If two circuits are connected by a vertical line, then they belong to the same network. If there is no
vertical line between the two circuits, then they belong to two different networks. Figure 1, shows three (1～3)
networks.
1.4 The Coding Rules of Mnemonic (Users of WinProladder can skip this section)
It’s very easy to program FB-PLC with WinProladder software package, just key-in the ladder symbols as they appear on
your CRT screen directly to form a ladder diagram program. But for the users who are using FPC-07 to program FB-PLC
they have to translate ladder diagram into mnemonic instructions by themselves. Since FPC-07 only can input program with
mnemonic instruction, this section till section 1.6 will furnish you with the coding rules to translate ladder diagrams into
mnemonic instructions.
z The program editing directions are from left to right and from top to bottom. Therefore the beginning point of the network
must be at the upper left corner of the network. Except the function instruction without the input control, the first instruction
of a network must begin with the ORG and only one ORG instruction is permissible per network. Please refer to section
6.1.1 for further explanations.
Example: X0 X1 X5 ORG X 0
AND X 1
X2 X4 LD X 2
X3
Ö OR
AND
X
X
3
4
ORLD
AND X 5
z Using LD instruction for connecting vertical lines (origin line or branch line) except at the beginning of the network.
Example 1: M0 ORG M 0
X0 X1 Ö LD
AND
X
X
0
1
ORLD
Example 2: AND Y 0
Y0 M0 M1 LD M 0
X0 X1 Ö AND
LD
M
X
1
0
AND X 1
ORLD
Remark 1: Using the AND instruction directly if only one row of elements is serially connected to the branch line.
Example: Y0
AND X 0
Ö ORLD
X0 AND Y 0
1-8
Remark 2: Also using the AND instruction directly if an OUT TR instruction has been used at a branch line to store
the node statuses.
Example: AND M 0
M0 X0 Y1 OUT TR 0
OUT TR0 Y0 Ö AND

OUT
X
Y
0
1
LD TR0 LD TR 0
AND Y 0
z Using AND instruction for serial connection of a single element.
Example: X0 X1
Ö ORG
AND
X
X
0
1
z Using OR instruction for parallel connection of a single element.
Example: X0 X2 ORG X 0
X1 Ö OR
AND
X
X
1
2
Example: X0 X1 X3 ORG X 0
AND X 1
X2 Ö OR X 2
AND X 3
z If the parallel element is a serial block, ORLD instruction must be used.
Example: X2 X3
ORG X 2
LD X 0
X0 X1 Ö AND
ORLD
X 1
AND X 3
Remark：If more than two blocks are to be connected in parallel, they should be connected in a top to bottom
sequence. For example, block 1 and block 2 should be connected first, then connect block 3 to it and so
on.
Example: LD X 0
AND M 0
X0 M0
LD X 1
X1 M1 AND M 1
X2 M2 Ö ORLD
LD X 2
AND M 2
X3 M3
ORLD
LD X 3
AND M 3
1-9
z ANDLD instruction is used to connect parallel blocks in series.
Example: ORG X 1
OR X 2
X1 X3 X4 X7
LD X 3
AND X 4
X2 X5 X6
Ö LD
AND
X
X
5
6
ORLD
Must use ANDLD instruction
ANDLD
AND X 7
z The ANDLD instruction must be used if the element or serial block is in front of the parallel block. If the parallel block is in
front of the element or serial block, AND instruction can be used to connect all parts together.
Example: ANDLD instruction ORG X 0

is not necessary AND X 1
Serial Block
X0 X1 X2 X4 LD X 2
X3 Ö OR
ANDLD
X 3
AND X 4
Must use ANDLD instruction
Remark: If there are more than two blocks are to be connected serially, they should be connected in a top to bottom
sequence. For example, block 1 and 2 should be connected first, then connect block 3 to it and so on.
Example: ORG X 0
LD X 1
OR X 2
X0 X1 X3 X4
ANDLD
X2 X5 X6 LD X 3
X7
Ö AND
LD
X
X
4
5
AND X 6
ORLD
OR X 7
ANDLD
z The output coil instruction （OUT）can only be located at end of the network (the right end) and no other elements can be
connected to it afterwards. The output coil can not connect to the origin line directly. If you want to connect the output coil
to the origin line, connect it serially with a short circuit contact.
ORG SHORT
Y0
Ö OUT Y 0
1 - 10
1.5 The De-Composition of a Network (Users of WinProladder can skip this section)
The key process of de-composition of a network is to separate the circuits that appear between two vertical lines into
independent elements and serial blocks, then coding those elements and serial blocks according to the mnemonic coding
rules and then connect them (with ANDLD or ORLD instruction) from left to right and top to bottom to form a parallel or a
serial-parallel blocks, and finally to form a complete network.
Sample diagram:
13 ANDLD( 9 12 )
9 AND( 7 8 )
7 ANDLD( 3 6 )
3 ORLD( 1 2 ) 6 ORLD( 4 5 ) 12 OR( 10 11 )
1 X0 X1 4 X4 X5 8 X8 10 X9 X10 14 Y0
2 X2 X3 5 X6 X7 11 X11
ORG X0
AND X1 Serial blockc
e
LD X2
AND X3 Serial blockd
ORLD Forming the parallel i

block e
LD X4
AND X5 Serial blockf
h
LD X6 k
AND X7 Serial blockg
ORLD Forming the parallel

block h
○
13 Y0
ANDLD Forming the serial
block i
AND X8 Serial blockiAND element j
LD X9
AND X10 Serial block ○
10
○
12
OR X11 OR element ○
11
ANDLD Forming the serial block ○

13
OUT Y0 Send the ○

13 result to Y0
1 - 11
1.6 Using Temporary Relays (Users of WinProladder can skip this section)
The network de-composition method for mnemonic coding demonstrated in section 1.5 does not apply to the branched
circuit or branched block. In order to input the program using the method shown in section 1.5, It must first to store the
statuses of branched nodes in temporary relays. The program design should avoid having branched circuit or branched
block as much as possible. Please refer the next section “Program Simplification Techniques”. Two situations that must use
the TR are described at below.
z Branched circuit: Merge line does not exist at the right side of the branch line or there is a merge line at the right side of the
branch line but they are not in the same row.
Example： * indicates setting of TR relay
Without merge line
Although this branch has merge lines

but they are not in the same row, so this
is also a branched circuit
z Branched block：The horizontal parallel blocks with a branch in one of the blocks.
Example： Merge line
Branch line
Remark 1: The OUT TR instruction must be programmed at the top of the branched point. LD TRn instruction is used
at the starting point of the circuits after second rows of the branch line for regaining the branch line status
before you can connect any element to the circuits. AND instruction must be used to connect the first
element after OUT TRn or LD TRn instruction. LD instruction is not allowed in this case.
Remark 2: A network can have up to 40 TR points and the TR number can not be used repeatedly in the same
network. It is recommended to use the numbers 1,2,3… with sequence. The TR number must be the
same in the same branch line. For example, if a branch line uses OUT TR0, then starting from row 2, LD
TR0 must be used for connection.
Remark 3: If the branch line of a branched circuit or a branched block is the origin line, then ORG or LD instructions
can be used directly and TR contact is not necessary.
Remark 4: If any one of the branched circuit rows is not connected to the output coil (there are serially connected
elements in between), and other circuits also exist after the second row, a TR instruction must be used at
the branch points.
1 - 12
Example: AND X 0
OUT TR0 OUT TR 0
X0 X1 Y0
AND X 1
OUT Y 0
X2 Y1
Ö LD TR 0 ←─ Begins from row 2
LD TR0 AND X 2
Y2
OUT Y 1
LD TR 0 ←─ Begins from row 3
OUT Y 2
Example: ORG X 1
OUT TR1 AND X 2
X1 X2 X5 X6 Y0 LD X 3
OUT TR 0
block 1 block 2 Ö AND X 4
X3 X4 X7 X8 ORLD
OUT TR 1
OUT TR0 LD TR1 AND X 5 Uses AND Instruction
←─ after TR instruction
X9 block 3 AND X 6
LD TR0
LD TR 1 Uses LD TR instruction
←─ to return to TR branch
AND X 7 line
LD TR 0
AND X 9 Uses AND instruction
←─ after TR instruction
ORLD
AND X 8
ORLD
OUT Y 0
z The above sample diagram shows a typical example of connecting two parallel blocks in series. Block 3 is formed when
the element X9 is introduced into the network and the two parallel blocks become the branched blocks.
z TR instruction is not necessary because the（*）point is the origin line.
z If have already used TR relay to connect two blocks serially, then ANDLD instruction is not necessary.
1.7 Program Simplification Techniques
z If a single element is connected in parallel to a serial block, The ORLD instruction can be omitted if the serial block is
connected on top of this single element.
X0 X1 X2
X1 X2
Ö X0
LD X 0 LD X 1
LD X 1 AND X 2
AND X 2 OR X 0
ORLD
1 - 13
z When a single element or a serial block is connected in parallel with a parallel block, ANDLD instruction can be omitted if
put the parallel block in front.
X0 X1 X2 X3 X4 X0 X1
X3 X4
Ö X2
ORG X 0 ORG X 3
AND X 1 AND X 4
LD X 2 OR X 2
LD X 3 AND X 0
AND X 4 AND X 1
ORLD
ANDLD
z If the branch node of a branch circuit is directly connected to the output coil, this coil could be located on top of the branch
line (first row) to reduce the code.
X0 Y0 Y1
Y1 Ö X0 Y0
OUT TR 0 OUT Y 1
AND X 0 AND X 0
OUT Y 0 OUT Y 0
LD TR 0
OUT Y 1
z The diagram shown below indicates the TR relay and the ORLD instruction can be omitted.
X0 Y0 X1 X2 Y0
X1 X2 X0
Ö
X3 Y1 X1 X3 Y1
OUT TR0
ORG X 0 ORG X 1
LD X 1 AND X 2
OUT TR 0 OR X 0
AND X 2 OUT Y 0
ORLD ORG X 1
OUT Y 0 AND X 3
LD TR 0 OUT Y 1
AND X 3
OUT Y 1
1 - 14
z Conversion of the bridge circuit
X1 X2 Y0
X0 Y0
X0
X1 X2 Y1
Ö X0 X2 Y1
This network structure is not X1

allowed in PLC program
ORG X 1
AND X 2
OR X 0
OUT Y 0
ORG X 0
AND X 2
OR X 1
OUT Y 1
1 - 15
MEMO
Chapter 2 FBs-PLC Memory Allocation
2.1 FBS-PLC Memory Allocation
Remark:
SRAM FBS-PACK 1. When the Read Only Register (ROR)
X0 X0
X(256)
X255 X255
has been configured by the user, the
Y0 Y0
Y(256) contents of R5000～R8071 (depends
Y255 Y255
T(256)
T0 T0
on the quantity of configuration) will
T255 T255
C(256)
C0 C0 be loaded from the ROR's during
DISCRETE Save status
STATUS
TR(40)
C255
Load status
C255
each time of power up or changing
AREA S0 S0
(4096)
S(1000)
from STOP to RUN mode.
S999 S999 The user can access the ROR through
M0 M0
the corresponding R5000～R8071.

M(2002) Write operation of function
instructions are prohibited in this
M2001 M2001
T(256)
T0 T0
ROR area of corresponding R5000～
T255 T255
C0 C0 R8071. The others of R5000～R8071
C(256)
C255 C255
R0 R0 that have not been configured for
ROR, they can work as general
R(3840)
purpose registers.
R3839 R3839
2. There is a dedicated area of program
D0 D0
REGISTER
AREA
Save Register memory to store the contents of
(20040W) D(4096)
Load Register Read Only Register.
D4095 D4095
IR , OR R3840 R3840 ROR can be configured up to 3072

SR(328)
R or ROR
R4167 R4167
words in maximum.
R5000 R5000
(3072)
F0 F0
F(8192)
F8191 F8191
LADDER LADDER
PROGRAM PROGRAM
(20KW) (20KW)
Save Program
LADDER
LABEL LABEL
PROGRAM (1KW) Load Program (1KW)
AREA
(32KW)
ROR ROR
(3KW) (3KW)
DOC DOC
(8KW) (8KW)
Memory Buffer in PLC PP/Winproladder
2-1
2.2 Digital and Register Allocations
〝 *〞 is default, user configurable
Typee Symbol Item Range Remarks
X Digital Input (DI) X0～X255 (256) Mapping to external digital I/O
Y Digital Output (DO) Y0～Y255 (256)
TR Temporary Relay TR0～TR39 (40) For branched points
Digital 《 Bit Status 》
M0～M799 (800)*
Non-Retentive M0～M1399 configurable as
Internal M1400～M1911 (512)
Non-retentive or Retentive, M1400～
M Relays
M800～M1399 (600)* M1911 are fixed to Non-retentive
Retentive
Special Relay M1912～M2001 (90)
Step Non-Retentive S0～S499 (500)* S20～ S499 configurable as Retentive

S
Relays Retentive S500～S999 (500)* S500～S999 configurable as Non-retentive
T Timer contact status T0～T255 (256)

C Counter contact status C0～C255 (256)
0.01STime Base T0～ T49 (50)*

CV of
The quantity of
TMR Timer 0.1S Time Base T50～T199 (150)*
each time base can be configured
Register T200～T255 (56)*
1S Time Base
Retentive C0～C139 (140)*
16-bit
Configurable as Non-retentive
CV of
Counter Non-Retentivee C140～C199 (60)* Configurable as Retentive
CTR
Register Retentive C200～C239 (40)*
32-bit
Configurable as Non-retentive
Non-Retentive C240～C255 (16) Configurable as Retentive
DR R0～R2999 (3000)* R0～R3839 configurable as

Data Retentive
or D0～D3999 (4000) Non-retentive or Retentive,
Registers
HR R3000～R3839 (840)* D0～D3999 are fixed to Retentive
Non-Retentive
Register 《 Word Data 》
IR Input Registers R3840～R3903 (64) Map to external AI Register input
OR Output Registers R3904～R3967 (64) Map to external AO /Register output
R3968～ R4167 (200)

System Special Registers
D4000～ D4095 (96)
High-Spped Timer Register R4152～R4154 (3)

Special Register
HSC Hardware (4sets) DR4096～ DR4110

Registers Software(4sets) DR4112～DR4126
Minute Second R4129 R4128
Calendar Day Hour R4131 R4130

Registers Year Month R4133 R4132
Week R4134
As general purpose registers if ROR not
DR Data Registers R5000～R8071(3072)*
been configured.
or
Configurable as ROR for recipe like
ROR Read Only Registers R5000～R8071(0)*
application
FR File Registers F0～F8191(8192) Need dedicated instruction to access
XR Index Registers V,Z (2)、 P0～ P9 (10)
2-2
Remark: During power up or changing operation mode from STOP→RUN, all contents in non-retentive relays or
registers will be cleared to 0; the retentive relays or registers will remain the same state as before.
2.3 Special Relay Details
Relay No. Function Description
1. Stop, Prohibited Control

M1912 Emergency Stop control y If ON, PLC will be stopped (but not enter STOP mode) and all
outputs OFF.
This bit will be cleared when power up or changing operation
mode from STOP→RUN.
M1913 Disable external outputs control y All external outputs are turn off but the
status of Y0～Y255 inside the PLC will not be affected.
M2001 Disable/Enable status retentive control yIf M2001 is 0 or enabled, the Disable/Enable status of all
contacts will be reset to enable during power up or changing
operation mode from STOP→RUN.
yIf M2001 is disabled and force ON, the Disable/Enable status &
ON/OFF state of all contacts will remain as before during power
up or changing operation mode from STOP→RUN.
While testing, it may disable and force ON M2001 to keep the
ON/OFF state of disabled contacts, but don’t forget to enable
the M2001 after testing.
2. CLEAR Control
M1914 Clear Non-Retentive Relays y Cleared When at 1
M1915 Clear Retentive Relays y Cleared When at 1
M1916 Clear Non-Retentive Registers y Cleared When at 1
M1917 Clear Retentive Registers y Cleared When at 1
M1918 Master Control (MC) Selection y If 0, the pulse activated functions within the master control loop
will only be executed once at first 0→1 of master control loop.
If 1, the pulse activated functions within the master control loop
will be executed every time while changing 0→1 of master
control loop.
M1919 Function output control yIf 0, the functional outputs of some function instructions will
memory the output state, even these instructions not been
executed.
If 1, the functional output of some function instructions without
the memory ability.
※ M1918/M1919 can be set to 0 or 1 at will around the whole program to meet the control requirements.
2-3
3. Pulse Signals
◤M1920 0.01S Clock pulse "1" T(M1920)=0.01S
◤M1921 0.1S Clock pulse "0" T(M1921)=0.1S
c T
◤M1922 1S Clock pulse c T(M1922)=1S
◤M1923 60S Clock pulse T is the pulse period T(M1923)=60S
◤M1924 Initial pulse (first scan) d "RUN"
"STOP"
◤M1925 Scan clock pulses e

t
d M1924 t is the scan time
◤M1926 Reserved
t t t t
e M1925
y 0：CTS True (ON)

◤M1927 CTS input status of communication
y 1：CTS False (OFF)
port 1
y When communication port 1 is used to connect with the printer
or modem, it can use this signal and a timer to detect whether
the printer or the modem is ready.
4. Error Messages
◤M1928 Reserved
◤M1929 Reserved
◤M1930 No expansion unit or exceed the limit y 1: Indicating no expansion unit or exceed the limit on number of
on number of I/O points I/O points
◤M1931 Immediate I/O not in the main unit y 1: Indicating that Immediate I/O not in the main unit range and
range the main unit cannot RUN
◤M1932 Unused
◤M1933 System stack error y 1: Indicating that system stack error
◤M1934
│ Reserved
◤M1935
5.Port3～Port4 Controls（MC/MN）
M1936 Port 3 busy indicator y 0：Port 3 Busy
y 1：Port 3 Ready
M1937 Port 3 finished indicator y 1：Port 3 finished all communication transactions
y 1：Port 4 Ready
2-4
6. HSC0/HSC1 Controls (MC/MN)

M1940 HSC0 software Mask y 1: Mask
M1941 HSC0 software Clear y 1: Clear
M1942 HSC0 software Direction y 0: Count-up, 1: Count-down
M1943 Reserved
M1944 Reserved
M1945 Reserved
M1947 HSC1software Clear y 1: Clear
M1949 Reserved
M1950 Reserved
M1951 Reserved
7. RTC Controls
M1952 RTC setting
M1953 ±30 second Adjustment
◤M1954 RTC installation checking
◤M1955 Set value error
8. Communication/Timing/Counting Controls
M1956 Selection of Message Fame Interval y 0：Use system default value as Message Fame Interval Detection
Detection Time Time for Modbus RTU communication protocol
y 1：Use the high byte value of R4148 as Message Fame Interval
Detection Time for Modbus RTU protocol
M1957 The CV value control after the timer y 0: The CV value will continue timing until the upper limit is met
"Time Up" after “Time Up”
y 1: The CV value will stop at the PV value after “Time Up” (User
may control M1957 within the program to control the individual
timer )
M1958 Communication port 2 High Speed y 0: Set Port 2 to Normal Speed Link
Link mode selection y 1: Set Port 2 to High Speed CPU Link
※M1958 is only effective at slave station
M1959 Modem dialing signal selection y 0: Dialing by TONE when Port 1 connecting with Modem.
y 1: Dialing by PULSE when Port 1 connecting wit
Modem.
y 1：Port 1 Ready
y 1：Port 2 Ready
M1964 Modem dialing control y If Port 1 is connected with Modem,
when signal 0→1 will dial the phone number;
when signal 1→0 will hang-up the phone.
2-5
M1965 Dialing success flag y 1: Indicating that dialing is successful (when Port 1 is connected
with Modem).
M1966 Dialing fail flag y 1: Indicating that dialing has failed (when Port 1 is connected
with Modem).
M1967 Port 2 High Speed Link working y 0: Continuous cycle.
mode selection y 1: One cycle only. It will stop when the last communication
transaction is completed (only effective at the master
station).
M1968 Step program status y 1: Indicating that there are more than 16 active steps in the step
program at the same time.
M1969 Indirect addressing illegal write flag y 1: Indicating that a function with index addressing attempts to
write cross over the boundary of different type of data.
M1970 Port 0 status y 1: Port 0 has received and transmitted a message
M1971 Port 1 status y 1: Port1 has received and transmitted a message
M1972 Port 2 status y 1: Port2 has received and transmitted a message
M1973 The CV value control after counting y 0: Indicating that the CV value will continue counting up to the
“Count-Up” upper limit after “Time-Up”.
y 1: Indicating that the CV value will stop at the PV value after
“Count-Up”（User may control M1973 within the program to
control the individual counter）
M1974 RAMP function (FUN95) slope y 0: Time control for ramping
control y 1: Equivalent slope control for ramping
M1975 CAM function (FUN112) selection y 1: For the circular applications where the electric CAM switch
(FUN112) can support the wrap around situation like the
angle from 359° cross to 0°
9. HSC2～HSC7 Controls
M1984 HSC5 software MASK y 1: Mask
M1990 Reserved
2-6
10. PSO0～PSO3 Controls
M1991 Selection of stopping the pulse output y 0：Immediately stop while stopping pulse output
(FUN140) y 1：Slow down stop while stopping pulse output
M1992 PSO0 Busy indicator y 0：PSO0 Busy
y 1：PSO0 Ready
y 1：PSO1 Ready

y 1：PSO2 Ready
y 1：PSO3 Ready
M1996 PSO0 Finished indicator y 1：PSO0 finished the last step of motion
M2000 Selection of Multi-Axis y 1: Synchronized Multi-Axis
synchronization for High Speed Pulse
Ouput (FUN140)
2-7
2.4 Special Registers Details
Register No. Function Description
Input Registers For Analog or Numeric inputs

R3840
CH0 : R3840
│
│ │
R3903
CH63 : R3903
Output Registers For Analog or Numeric outputs
R3904
CH0 : R3904
│
│ │
R3967
CH63 : R3967
Raw Temperature Registers For temperature measurement
R3968
TP0 : R3968
│
│ │
R3999
TP31 : R3999
R4000 Reserved
R4001 Reserved
R4002 Reserved
R4003 Reserved
R4004 Reserved
R4005 High Byte：Period of PWM For PID temperature control
=0, 2 seconds
=1, 4 seconds
=2, 8 seconds
=3, 1 second
=4, 16 seconds
≥5, 32 seconds
Low Byte：Period of PID calculation
=0, 2 seconds
=1, 4 seconds
=2, 8 seconds
=3, 1 second
=4, 16 seconds
≥5, 32 seconds
R4006 Threshold value of output ratio for For PID temperature control
heating/cooling loop abnormal detecting (Unit
in %)
R4007 Threshold value of continuous time for For PID temperature control
heating/cooling loop abnormal detecting (Unit
in second)
R4008 Maximum temperature for heating loop For PID temperature control
abnormal detecting
R4009 Reserved
2-8
R4010
Each bit represents 1 sensor,
│ Installed temperature sensor flag
if bit value = 1 means installed.
R4011
R4012
Each bit represents 1 temperature point, if bit value =
│ PID Temperature control flag
1 means enable control.
R4013
R4014 Reserved
R4015 Averaging of temperature value
=0, no average on temperature
=1, average by two readings
=2, average by four readings
=3, average by eight readings
=4, average by sixteen readings
R4016 Reserved
R4017 Reserved
R4018 Reserved
R4019 Reserved
R4020
│ Reserved
R4024
R4025 Total Expansion Input Registers
R4026 Total Expansion Output Registers
R4027 Total Expansion Digital Inputs
R4028 Total Expansion Digital Outputs
R4029 Reserved for system
When the ROM Pack being used to save the ladder
R4030 program and data registers, these tables describes
Tables to save or read back the data
│ which registers will be written into the ROM Pack.
registers into or from ROM Pack
R4039 The addressed registers will be initialized from ROM
Pack while power up.
R4040 Reply delay time settings for Port 0 and Port Low Byte：For Port 0 (Unit in mS)
1 High Byte：For Port 1 (Unit in mS)
R4041 Reply delay time settings for Port 2 and Port Low Byte：For Port 2 (Unit in mS)
3 High Byte：For Port 3 (Unit in mS)
R4042 Reply delay time settings for Port 4 Low Byte：For Port 4 (Unit in mS)
High Byte：Reserved for system
R4043 Port 3 Communication Parameters Register Set Baud Rate, Data bit…of Port 3
R4044 Port 4 Communication Parameters Register Set Baud Rate, Data bit…of Port 4
R4045 Transmission Delay & Receive Low Byte：Port 3 Receive Time-out interval time
Time-out interval time Setting, (Unit in 10mS)
while Port 3 being used as the master of High Byte：Port 3 Transmission Delay
FUN151 or FUN150 (Unit in 10mS)
2-9
R4046 Power up initialization mode selection of data =5530H: Don’t initialize the addressed data registers
registers that has been written into ROM been written into ROM Pack while power up
Pack. =Others : initialize the addressed data registers been
written into ROM Pack while power up
R4047 Communication protocol setting for Port1～ Set the FATEK or Modbus RTU communication
Port4 protocol
R4048 Transmission Delay & Receive Low Byte：Port 4 Receive Time-out interval time (Unit
Time-out interval time Setting, in 10mS)
R4049 CPU Status Indication =A55AH, Force CPU RUN
=0, Normal Stop
=1, Function(s) existed that CPU does not support
=2, PLC ID not matched with Program ID
=3, Ladder checksum error
=4, System STACK error
=5, Watch-Dog error
=6, Immediate I/O over the CPU limitation
=7, Syntax not OK
=8, Qty of expansion I/O modules exceeds
=9, Qty of expansion I/O points exceeds
=10, CRC error of system FLASH ROM
R4050 Port 0 Communication Parameters Register Set Baud Rate of Port 0
R4051 Reserved
R4052 Indicator while writing ROM Pack
R4053 Reserved
R4054 Define the master station number If the master station number is 1,it can ignore this
of the High-Speed CPU Link network register.
(FUN151 Mode 3) To set the master station number other than 1 should:
Low Byte : Station number
High Byte: 55H
R4055 PLC station number y If high byte is not equal 55H, R4055 will show the
station number of this PLC
y If want to set PLC station number then R4055
should set to:
Low Byte : Station number
High Byte: 55H
High Byte :Reserved
R4056 Low Byte: High speed pulse output frequency Low Byte: =5AH, can dynamically change the output
dynamic control frequency of High Speed Pulse Output
R4057 Power off counter The value will be increased by 1 while power up
R4058 Error station number while Port 2 in High Used by FUN151 Mode 3 of Port 2
Speed CPU Link
2 - 10
R4059 Error code while Port 2 in High Speed CPU Used by FUN151 Mode 3 of Port 2
LINK mode High byte Low Byte
R4059 Err code Err count H
Error code： 0AH, No response

01H, Framing Error
02H, Over-Run Error
04H, Parity Error
08H, CRC Error
R4060 Error code of PSO 0 The error codes are:

1: Parameter 0 error
30: Speed setting reference number error
31: Speed value error
32: Stroke setting reference number error
33: Stroke value error
34: Illegal positioning program
35: Step over
36: Step number exceeds 255
37: Highest frequency error
38: Idle frequency error
39: Movement compensation value too large
40: Movement value exceeds range
41: DRVC instruction not allow ABS addressing
R4061 Error code of PSO 1 Same as above
R4064 PSO 0
R4065 Being completed step number of positioning PSO 1
R4066 program PSO 2
R4067 PSO 3
R4068
│ Reserved
R4071
2 - 11
R4072 Low Word of PSO 0

R4073 High Word of PSO 0
R4076 Pulse count remaining for output Low Word of PSO 2

R4083 Current output frequency High Word of PSO 1

R4091 Current pulse position High Word of PSO 1
2 - 12
R4096 HSC0 current value Low Word

R4097 HSC0 current value High Word
R4098 HSC0 preset value Low Word
R4099 HSC0 preset value High Word
R4128 Second of calendar
R4129 Minute of calendar
R4130 Hour of calendar
R4131 Day of calendar
R4132 Month of calendar

R4133 Year of calendar
R4134 Day of week of calendar
R4135 Reserved
◤ R4136 Current scan time
y Error < ±1ms
◤ R4137 Maximum scan time
y Re-calculate when PLC changes from STOP to RUN
◤ R4138 Minimum scan time
2 - 13
R4139 CPU Status Bit0 =0, PLC STOP

=1, PLC RUN
Bit1 , Reserved
Bit2 =1, Ladder program checksum error
Bit3 =0, Without ROM Pack
=1, With ROM Pack
Bit4 =1, Watch-Dog error
Bit5 =1, MA model main unit
Bit6 =1, With ID protection
Bit7 =1, Emergency stop
Bit8 =1, Immediate I/O over range
Bit9 =1, System STACK error
Bit10 =1, ASIC failed
Bit11 =1, Function not allowed
Bit12 , Reserved
Bit13 =1, With communication board
Bit14 =1, With calendar
Bit15 =1, MC main unit
R4140
R4141
R4142 Telephone Number
R4143
R4144
R4145
2 - 14
R4146 Port 1 Communication Parameters Set Baud Rate, Data bit… of Port 1
Register
Transmission Delay & Receive Low Byte：Port 1 Receive Time-out interval time
R4147
.While the communication port being used as the master or
R4148 Message Frame Detection Time Interval
slave of Modbus RTU protocol, the system will give the
default time interval to identify each packet of receiving
message; except this, the user can set this time interval
through the high byte setting of R4148 and let M1956 be
1, to avoid the overlap of different packet of message
frame.
M1956=1, High Byte of R4148 is used to set the new

message detection time interval for Port 1～Port 4 (Unit
in mS)
.While the communication port being used to communicate

with the intelligent peripherals through FUN151
instruction, if the communication protocol without the end
of text to separate each packet of message frame, it
needs message detection time interval to identify the
different packet. High byte of R4148 is used for this
setting for Port 1～Port 4.
(Unit in mS)
y High Byte of R4149:
R4149 Modem Interface Setting & Port0
=55H, Remote-Diagnosis/Remote-CPU-Link
without checking of station number for by way of Port 1 through Modem
FATEK's external communication protocol connection, it supports user
program controlled dial up function
=AAH, Remote diagnosis by way of Port 1
through Modem connection, it
supports Passive receiving & Active
dialing operation mode
=Others, without above function
y Low Byte of R4149:

=1, Port 0 without checking of station number
for FATEK's external
communication protocol (communicating with
MMI/SCADA)
=Others, Port 0 checks station number, it allows
multi-drop network for data acquisition.
R4150 Power on I/O service delay time setting y PLC is ready for I/O service after this delay time while
power up. The unit is in 0.01S. The default value is 100.
R4151 Circular 1mS time base timer y The content of R4151 will be increased by 1 every 1mS.
It can be used for a more precise timing application.
R4152 Low word of HSTA CV register HSTA is high speed timer in 0.1 mS resolution
R4153 High word of HSTA CV register The HSTA can act as 32-bit cyclic timer or fixed time
R4154 PV register of HSTA interrupt timer
2 - 15
R4155 Port 1 & Port 2 without station number
checking for FATEK's external
=1, Port 1 without station number
communication protocol
(communicating with MMI/SCADA)
=Others,Port 1 checks station number, it allows
multi-drop network for data acquisition

R4156 Port 3 & Port 4 without station number

R4157 System used

R4158 Port 2 Communication Parameters Set Baud Rate, Data bit…of Port 2
Register
(Not for High Speed CPU Link)
Transmission Delay & Receive Low Byte：Port 2 Receive Time-out interval time
R4159
R4160 Port2 RX/TX time out setting for High High Byte of R4160 :
Speed CPU Link =56H, User setting mode if the system default works not
well, Low Byte of R4160 is used for this setting (Not
suggest)
=Others, system will give the default value according to
the setting of R4161
R4161 Port 2 Communication Parameters ySet Baud Rate, Parity…of Port 2
Register y Data bit is fixed to 8-bit
(For High Speed CPU Link) y Baud Rate≧38400 bps
R4162 Fixed time interrupt enable/disable B7 B6 B5 B4 B3 B2 B1 B0
control 100mS 50mS 10mS 5mS 4mS 3mS 2mS 1mS
Bit=0, interrupt enabled
Bit=1, interrupt disabled
2 - 16
R4163 Modem dialing control setting y Low Byte of R4163 :

=1, Ignore the dialing tone and the busy tone when
dialing.
=2, Wait the dialing tone but ignore the busy tone when
dialing.
=3, Ignore the dialing tone but detect the busy tone
when dialing.
=4, Wait the dialing tone and detect the busy tone when
dialing.
=Any other value treated as value equal 4.
y High Byte of R4163 :

The Ring count setting for Modem auto answer
R4164 V index register
R4165 Z index register
R4166 System used
R4167 Model of main unit y Low Byte of R4167:
=0, 6I + 4O (FBs-10xx)
=1, 8I + 6O (FBs-14xx)
=2, 12I + 8O (FBs-20xx)
=3, 14I + 10O (FBs-24xx)
=4, 20I + 12O (FBs-32xx)
=5, 24I + 16O (FBs-40xx)
=6, 36I + 24O (FBs-60xx)
=7, 28I + 16O (FBs-44MN)
=0, MA
=1, MC
=2, MN
=3, MU
2 - 17
D4000 Port 1 User-defined Baud Rate Divisor Port 1 user-defined Baud Rate (1125~1152000 bps)
(R4146 must be 56XFH) D4000 = (18432000/Baud Rate) - 1
D4004
│ Reserved
D4079
D4080 P0 index register
D4090
│ Reserved
D4095
Remark: All the special relays or registers attached with “◤” symbol shown in the above table are write prohibited.
For the special relays attached with “◤” symbol also has following characteristics
. Forced and Enable/Disable operation is not allowed.
. Can’t be referenced by TU/TD transitional contact (contact will always open)
2 - 18
Chapter 3 FBs-PLC Instruction Lists
3.1 Sequential Instructions
Execution
Instruction Operand Symbol Function Descriptions Instruction type
Time
Starting a network with a normally open (A)
ORG
contact
0.33uS
Starting a network with a normally closed
ORG NOT X,Y,M, (B) contact
S,T,C Starting a network with a differential up Network
ORG TU (TU) contact
0.54uS starting
Starting a network with a differential down
ORG TD (TD) contact instructions
Starting a network with a open circuit
ORG OPEN
contact
0.33uS
Starting a network with a short circuit
ORG SHORT
contact
Starting a relay circuit from origin or branch
LD
line with a normally open contact
0.33uS
LD NOT X,Y,M, line with a normally closed contact
Starting a relay circuit from origin or branch Origin or
S,T,C
LD TU line with a differential up contact branch line
0.54uS
Starting a relay circuit from origin or branch starting
LD TD line with a differential down contact
instructions
LD OPEN
line with a open circuit contact
0.33uS
LD SHORT
line with a short circuit contact
AND Serial connection of normally open contact

0.33uS
Serial connection of normally closed
AND NOT X,Y,M, contact
S,T,C Serial connection of differential up contact Serial
AND TU
0.54uS connection
Serial connection of differential down
AND TD contact instructions
AND OPEN Serial connection of open circuit contact

0.33uS
AND SHORT Serial connection of short circuit contact
Parallel connection of normally open
OR
contact
0.33uS
Parallel connection of normally closed
OR NOT X,Y,M, contact
S,T,C Parallel connection of differential up contact Parallel
OR TU
0.54uS connection
Parallel connection of differential down
OR TD contact instructions
OR OPEN Parallel connection of open circuit contact

0.33uS
OR SHORT Parallel connection of short circuit contact
ANDLD Serial connection of two circuit blocks

Blocks merge
0.33uS
ORLD Parallel connection of two circuit blocks instructions
3-1
Execution
Instruction Operand Symbol Function Descriptions Instruction type
Time
OUT Send result to coil

Y,M,S
0.33uS
OUT NOT Send inverted result to coil Coil output
│
instruction
Send result to an external output coil and 1.09uS
OUT L Y L
appoint it as of retentive type
OUT Save the node status to a temporary relay

TR 0.33uS
LD Load the temporary relay
Node operation
TU Take the transition up of the node status 0.33uS
instruction
TD Take the transition down of the node status 0.33uS
NOT Invert the node status 0.33uS
0.33uS
SET (S) Set a coil │
1.09uS
0.33uS
( R)
RST Reset a coil │
1.09uS
● The 36 sequential instructions listed above are all applicable to every models of FBs-PLC.
3.2 Function Instructions
There are more than 100 different FBs-PLC function instructions. If put the “D” and “P” derivative instructions into account,
the total number of instructions is over 300. On top of these, many function instructions have multiple input controls (up to
4 inputs) which can have up to 8 different types of operation mode combinations. Hence, the size of FBs-PLC instruction
sets is in fact not smaller than that of a large PLC. Having powerful instruction functions, though may help for establishing
the complicated control applications, but also may impose a heavy burden on those users of small type PLC’s. For ease
of use, FATEK PLC function instructions are divided into two groups, the Basic function group which includes 26
commonly used function instructions and 4 SFC instructions and the advanced function group which includes other more
complicated function instructions, such as high-speed counters and interrupts. This will enable the beginners and the
non-experienced users to get familiar with the basic function very quickly and to assist experienced users in finding what
they need in the advanced set of function instructions.
The instructions attached with “ ” symbol are basic functions which amounts to 26 function instructions and 4 SFC
instructions. All the basic functions will be explained in next chapter. The details for the reset of functions please refer
advanced manual.
3-2
General Timer/Counter Function Instructions
FUN Derivative
Name Operand Function descriptions
No. Instruction
T nnn PV General timer instructions (“nnn” range 0～255)

C nnn PV General counter instructions (“nnn” range 0～255)
Single Operand Function Instructions
4 DIFU D To get the up differentiation of a D relay and store the result to D

5 DIFD D To get the down differentiation of a D relay and store the result to D
10 TOGG D Toggle the status of the D relay
Setting/Resetting
SET D DP Set all bits of register or a discrete point to 1

RST D DP Clear all bits of register or a discrete point to 0
114 Z-WR D P Zone set or clear
SFC Instructions
STP Snnn STEP declaration

STPEND End of the STEP program
TO Snnn STEP divergent instruction
FROM Snnn STEP convergent instruction
Mathematical Operation Instructions
11 (＋) Sa,Sb,D DP Perform addition of Sa and Sb and then store the result to D
12 (－) Sa,Sb,D DP Perform subtraction of Sa and Sb and then store the result to D
13 (＊) Sa,Sb,D DP Perform multiplication of Sa and Sb and then store the result to D
14 (／) Sa,Sb,D DP Perform division of Sa and Sb and then store the result to D
15 (＋1) D DP Adds 1 to the D value
16 (－1) D DP Subtracts 1 from the D value
23 DIV48 Sa,Sb,D P Perform 48 bits division of Sa and Sb and then store the result to D
Take the sum of the successive N values beginning from S and store
24 SUM S,N,D DP
it in D
Take the mean average of the successive N values beginning from S
25 MEAN S,N,D DP
and store it in D
26 SQRT S,D DP Take the square root of the S value and store it in D
Take the 2's complement (negative number) of the D value and store
27 NEG D DP
it back in D
28 ABS D DP Take the absolute value of D and store it back in D
Take the 16 bit numerical value and extend it to 1 32 bit numerical
29 EXT D P
value (value will not change)
TS,SR,OR,
30 PID PID operation
PR,WR
31 CRC MD,S,N,D P CRC16 checksum calculation
32 ADCNV PL,S,N,D Offset and full scale conversion
3-3
FUN Derivative
No. Instruction
200 I→F S,D DP Integer to floating point number conversion
201 F→I S,D DP Floating point number to integer conversion
202 FADD Sa,Sb,D D Addition of floating point number
203 FSUB Sa,Sb,D D Subtraction of floating point number
204 FMUL Sa,Sb,D D Multiplication of floating point number
205 FDIV Sa,Sb,D D Division of floating point number
206 FCMP Sa,Sb D Comparison of floating point number
207 FZCP Sa,Sb D Zone comparison of floating point number
208 FSQR S,D D Square root of floating point number
209 FSIN S,D D SIN trigonometric function
210 FCOS S,D D COS trigonometric function
211 FTAN S,D D TAN trigonometric function
212 FNEG D P Change sign of floating point number
213 FABS D P Take absolute value of floating point number
Logical Operation Instructions
18 AND Sa,Sb,D DP Perform logical AND for Sa and Sb and store the result to D
19 OR Sa,Sb,D DP Perform logical OR for Sa and Sb and store the result to D
Take the result of the Exclusive OR logical operation made between
35 XOR Sa,Sb,D DP
Sa and Sb, and store it in D
Take the result of the Exclusive OR logical operation made between
36 XNR Sa,Sb,D DP
Sa and Sb, and store it in D
Comparison Instructions
Compare the data at Sa and data at Sb and output the result to

17 CMP Sa,Sb DP
function outputs (FO)
Compare S with the zones formed by the upper limit SU and lower
37 ZNCMP S,SU,SL DP
limit SL, and set the result to FO0~FO2
3-4
Data Movement Instructions
FUN Derivative
No. instruction
8 MOV S,D DP Transfer the W or DW data specified at S to D

Invert the W or DW data specified at S, and then transfers the result
9 MOV/ S,D DP
to D
Read the status of the bits specified by N within S, and send it to

40 BITRD S,N DP
FO0
41 BITWR D,N DP Write the INB input status into the bits specified by N within D
Write the status of bit specified by N within S into the bit specified by
42 BITMV S,Ns,D,Nd DP
N within D
43 NBMV S,Ns,D,Nd DP Write the Ns nibble within S to the Nd nibble within D
Write the byte specified by Ns within S to the byte specified by Nd

44 BYMV S,Ns,D,Nd DP
within D
45 XCHG Da,Db DP Exchange the values of Da and Db
46 SWAP D P Swap the high-byte and low-byte of D
Take the nibble 0 (NB0) of the successive N words starting from S
47 UNIT S,N,D P
and combine the nibbles sequentially then store in D
De-compose the word into successive N nibbles starting from nibble
48 DIST S,N,D P 0 of S, and store them in the NB0 of the successive N words starting
from D
49 BUNIT S,N,D P Low byte of words re-unit
50 BDIST S,N,D P Words split into multi-byte
160 RW-FR Sa,Sb,Pr,L DP File register access
Shifting/Rotating Instructions
6 BSHF D DP Shift left or right 1 bit of D register

Shift left the D register N bits and move the last shifted out bits to
51 SHFL D,N DP
OTB. The empty bits will be replaced by INB input bit
Shift right the D register N bits and move the last shifted out bits to
52 SHFR D,N DP
OTB, The empty bits will be replaced by INB input bit
Rotate left the D operand N bits and move the last rotated out bits to
53 ROTL D,N DP
OTB
Rotate right the D operand N bits and move the last rotated out bits
54 ROTR D,N DP
to OTB
Code Conversion Instruction
20 →BCD S,D DP Convert binary data of S into BCD data and store the result to D
21 →BIN S,D DP Convert BCD data of S into binary data and store the result to D
55 B→G S,D DP Binary to Gray code conversion
3-5
FUN Derivative
No. instruction
56 G→B S,D DP Gray code to Binary conversion
Decode the binary data formed by NL bits starting from Ns bit within
57 DECOD S,Ns,NL,D P
S, and store the result in the register starting from D
Encoding the NL bits starting from the Ns bit within S, and store the
58 ENCOD S,Ns,NL,D P
result in D
Convert the N+1 number of nibble data within S, into 7 segment

59 →7SG S,N,D P
code, then store in D
Write the constant string S (max. 12 alpha-numeric or symbols) into

60 →ASC S,D P
the registers starting from D
Convert the time data (hours, minutes, seconds) of the three
61 →SEC S,D P successive registers starting from S into seconds data then store to
D
Convert the seconds data of S into time data (hours, minutes,
62 →HMS S,D P seconds) and store the data in the three successive registers starting
from D
Convert the successive N ASCII data starting from S into

63 →HEX S,N,D P
hexadecimal data and store them to D
Convert the successive N hexadecimal data starting from S into

64 →ASCⅡ S,N,D P
ASCII codes and store them to D
Flow Control Instructions
0 MC N The start of master control loop

1 MCE N The end of master control loop
2 SKP N The start of skip loop
3 SKPE N The end of skip loop
END End of Program
1～6
65 LBL Define the label with 1~6 alphanumeric characters
alphanumeric
66 JMP LBL P Jump to LBL label and continues the program execution
67 CALL LBL P Call the sub-program begin with LBL label
68 RTS Return to the calling main program from sub-program
69 RTI Return to interrupted main program from sub-program
70 FOR N Define the starting point of the FOR Loop and the loop count N
71 NEXT Define the end of FOR loop
3-6
I/O Function Instructions
FUN Derivative
No. instruction
74 IMDIO D,N P Update the I/O signal on the main unit immediately
76 TKEY IN,D,KL D Convenient instruction for 10 numeric keys input
77 HKEY IN,OT,D,KL D Convenient instruction for 16 keys input
78 DSW IN,OT,D D Convenient instruction for digital switch input
79 7SGDL S,OT,N D Convenient instruction for multiplexing 7-segment display
80 MUXI IN,OT,N,D Convenient instruction for multiplexing input instruction
MD, Fr, PC
81 PLSO D Pulse output function (for bi-directional drive of step motor)
UY,DY,HO
82 PWM TO,TP,OT Pulse width modulation output function
83 SPD S,TI,D Speed detection function
S,Yn,Dn,
84 TDSP 7/16-segment LED display control
PT,IT,WS
Md,Yn,Sn,Zn,
86 TPCTL Sv,Os,PR PID Temperature control
IR,DR,OR,WR
PW,OP,RS,
139 HSPWM Hardware PWM pulse output
PN,OR,WR
Cumulative Timer Function Instructions
87 T.01S CV,PV Cumulative timer using 0.01S as the time base

88 T.1S CV,PV Cumulative timer using 0.1S as the time base
89 T1S CV,PV Cumulative timer using 1S as the time base
Watch Dog Timer Control Function Instructions
90 WDT N P Set the WDT timer time out time to N mS

91 RSWDT P Reset the WDT timer to 0
High Speed Counter Control Function Instructions
Read the current CV value of the hardware HSCs, HSC0～HSC3, or

92 HSCTR CN P HST on ASIC to the corresponding CV register in the PLC
respectively
Write the CV or PV register of HSC0～HSC3 or HST in the PLC to
93 HSCTW CN,D P
CV or PV register of the hardware HSC or HST on ASIC respectively
Report Function Instructions
Parse and generate the report message based on the ASCII

94 ASCWR MD,S,Pt formatted data starting from the address S. Then report message will
send to port1
3-7
Ramp Function Instructions
FUN Derivative
No. instruction
Tn,PV,SL,
95 RAMP Ascending/Descending convenient instruction
SU,D
Communication Function Instructions
150 M-Bus MD,S,Pt Modbus protocol communication
151 CLINK MD,S,Pt Fatek/Generic protocol communication
Table Function Instructions
100 R→T Rs,Td,L,Pr DP Store the Rs value into the location pointed by the Pr in Td
101 T→R Ts,L,Pr,Rd DP Store the value at the location pointed by the Pr in Ts into Rd
Store the value at the location pointed by the Pr in Ts into the
102 T→T Ts,Td,L,Pr DP
location pointed by the Pr in Td
103 BT_M Ts,Td,L DP Copy the entire contents of Ts to Td
104 T_SWP Ta,Tb,L DP Swap the entire contents of Ta and Tb
Search the table Ts to find the location with data different or equal to
105 R-T_S Rs,Ts,L,Pr DP
the value of Rs. If found store the position value into the Pr
Compare two tables Ta and Tb to search the entry with different or

106 T-T_C Ta,Tb,L,Pr DP
same value. If found store the position value into the Pr
107 T_FIL Rs,Td,L DP Fill the table Td with Rs
IW,Ts,Td, Store the result into Td after shift left or right one entry of table Ts.
108 T_SHF DP
L,OW The shift out data is send to OW and the shift in data is from IW
109 T_ROT Ts,Td,L DP Store the result into Td after shift left or right one entry of table Ts.
IW,QU,L,
110 QUEUE DP Push IW into QUEUE or get the data from the QUEUE to OW (FIFO)
Pr,OW
IW,ST,L,
111 STACK DP Push IW into STACK or get the data from the STACK to OW (LIFO)
Pr,OW
Compare the Rs value with the upper/lower limits of L, constructed
112 BKCMP Rs,Ts,L,D DP by the table Ts, then store the comparison result of each pair into the
relay designated by D (DRUM)
Sorting the registers starting from S length L and store the sorted
113 SORT S,D,L DP
result to D
Matrix Instructions
120 MAND Ma,Mb,Md,L P Store the results of logic AND operation of Ma and Mb into Md
121 MOR Ma,Mb,Md,L P Store the results of logic OR operation of Ma and Mb into Md
122 MXOR Ma,Mb,Md,L P Store the results of logic Exclusive OR operation of Ma and Mb into Md
123 MXNR Ma,Mb,Md,L P Store the results of logic Exclusive OR operation of Ma and Mb into Md
124 MINV Ms,Md ,L P Store the results of inverse Ms into Md
Compare Ma and Mb to find the location with different value, then
125 MCMP Ma,Mb,L Pr P
store the location into Pr
3-8
FUN Derivative
No. instruction
126 MBRD Ms,L,Pr P Read the bit status pointed by the Pr in Ms to the OTB output
127 MBWR Md,L,Pr P Write the INB input status to the bits pointed by the Pr in Ms
Store the results to Md after shift one bit of the Ms. Shifted out bit will
128 MBSHF Ms,Md,L P
appear at OTB and the shift in bits comes from INB
Store the results to Md after rotate one bit of the Ms. Rotated out bit
129 MBROT Ms,Md,L P
will appear at OTB.
Calculate the total number of bits that are 0 or 1 in Ms, then store the
130 MBCNT Ms,L,D P
results into D
NC Positioning Instruction
140 HSPSO Ps,SR,WR HSPSO instruction of NC positioning control

141 MPARA Ps,SR P Parameter setting instruction of NC positioning control
142 PSOFF Ps P Stop the pulse output of NC positioning control
143 PSCNV Ps,D P Convert the Ps positions of NC positioning to mm, Inch or Deg
Disable/Enable Control of Interrupt or Peripheral
145 EN LBL P Enable HSC, HST, external INT or peripheral operation
146 DIS LBL P Disable HSC, HST, external INT or peripheral operation
3-9
Chapter 4 Sequential Instructions
The sequential instructions of FBs-PLC shown in this chapter are also listed in section 3.1. Please refer to Chapter 1,
"PLC Ladder diagram and the Coding rules of Mnemonic instruction", for the coding rules in applying those instructions. In
this chapter, we only introduce the applicable operands, ranges and element characteristics, functionality.
4.1 Valid Operand of Sequential Instructions
Operand X Y M SM S T C TR OPEN SHORT
Ranges X0 Y0 M0 M1912 S0 T0 C0 TR0

| | | | | | | | — —
Instruction
X255 Y255 M1911 M2001 S999 T255 C255 TR39
ORG ○ ○ ○ ○ ○ ○ ○ ○ ○
ORG NOT ○ ○ ○ ○ ○ ○ ○
※
ORG TU ○ ○ ○ ○ ○ ○ ○
※
ORG TD ○ ○ ○ ○ ○ ○ ○
LD ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
LD NOT ○ ○ ○ ○ ○ ○ ○
※
LD TU ○ ○ ○ ○ ○ ○ ○
※
LD TD ○ ○ ○ ○ ○ ○ ○
AND ○ ○ ○ ○ ○ ○ ○ ○ ○
AND NOT ○ ○ ○ ○ ○ ○ ○
※
AND TU ○ ○ ○ ○ ○ ○ ○
※
AND TD ○ ○ ○ ○ ○ ○ ○
OR ○ ○ ○ ○ ○ ○ ○ ○ ○
OR NOT ○ ○ ○ ○ ○ ○ ○
※
OR TU ○ ○ ○ ○ ○ ○ ○
※
OR TD ○ ○ ○ ○ ○ ○ ○
※
OUT ○ ○ ○ ○ ○
※
OUT NOT ○ ○ ○ ○
OUT L ○
ANDLD −
ORLD −
TU −
TD −
NOT −
※
SET ○ ○ ○ ○
※
RST ○ ○ ○ ○
4-1
※For the relays marked with a ‘◤’ symbol in the special relay table（please refer to section 2.3）is write prohibited. In
addition, TU and TD contacts are not supported for those relays as well. The operands marked with a ‘*‘ symbol in the
table shown above should exclude those special relays.
4.2 Element Description
4.2.1 Characteristics of A,B,TU and TD Contacts
ON
● Input X0 from the input terminal block X0
OFF
● A contact Element status 1

X0
0
● B contact Element status

1
X0
0 t: scan time
● TU contact Element status
1
X0
● TD contact Element status 0
t
1
X0 t
0
The waveform shown above reveals the function of A, B, TU and TD elements by exercising the external input X0 form
OFF to ON then OFF.
TU (Transition Up): This is the “Transition Up Contact”. Only a rising edge (0Æ1) of the referenced signal will turn on
this element for one scan time.
TD (Transition Down): This is the “Transition Down Contact”. Only a falling edge (1Æ0) of the referenced signal will
turn on this element for one scan time.
TU and TD contact will work normally as described above if the change of the status of the valid referenced operands
listed in the “Valid Range of the Operand of Sequential instructions” table are not driven by the function instructions.
Remark: For TU(TD) elements which operand is of relay will turn on after the first time the corresponding relay get
driven from 0 to 1(1 to 0). When the next time the corresponding relay get driven from 1 to 1(0 to 0) the
TD(TU) element will turn OFF. Care should be taken while there is a multiple coil usage situation existed
in the ladder program. This situation can be best illustrated at below. In the waveform we can see Y0 TU
element only turn on between ○
b and ○
e time which only the Y0 TU elements existed between rung 1
and rung 2 can detect the Y0 rising edge, while other Y0 TU elements out side these two ladder rungs will
never aware the occurrence of the rising edge. For the relays do not have the multiple coil usage in
ladder program, The ON status of corresponding TU or TD element can be sustained for one scan time,
but for relays which contrary to above, the turn on time will shorter than 1 scan time as illustrated at
below.
4-2
Ladder Diagram Mnemonic code
X0 Y0
ORG X 0 --------------------- ○
a
OUT Y 0 --------------------- ○
b
Y1
OUT Y 1 --------------------- ○
c
ORG X 1 --------------------- ○
d
X1 Y0 OUT Y 0 --------------------- ○
e
N times scan N+1 times scan
Scan Time t
a b c d e
a b c d e
X0
X1
Y0
Y0
Y0
Y1
Y1
A : The internal accumulator of PLC
Besides the TU/TD instructions which can detect the status change of reference operand, FBs-PLC also provides
the instructions to detect the change of node status (power flow). For details please refer the descriptions of FUN4
(DIFU) and FUN5 (DIFD) instructions at chapter 7.
4.2.2 OPEN and SHORT Contact
The status of OPEN and SHORT contact are fixed and can’t be changed by any ladder instructions. Those two contacts
are mainly used in the places of the Ladder Diagram where fixed contact statuses are required, such as the place where
the input of an application instruction is used to select the mode. The sample program shown below gives an example of
configuring an Up/Down counter (UDCTR) to an Up counter by using the SHORT contact.
X0 7.UDCTR ORG X 0
CK CV : R 0 CUP LD SHORT
LD X 1
U/D PV : R 10
FUN 7
X1
CV: R 0
CLR
PV: R 10
4-3
FUN7 is the UDCTR function. While rising edge of CK input occur, FUN7 will count up if the U/D status is 1 or count down
if the U/D status is 0. The example shown above, U/D status is fixed at 1 since U/D is directly connected from the
origin-line to a SHORT contact, therefore FUN7 becomes an Up counter. On the contrary, if the U/D input of FUN7 is
connected with an OPEN contact from the origin-line, the FUN7 becomes a DOWN counter.
X0 7.UDCTR ORG X 0
CK CV : R 0 CUP LD OPEN
LD X 1
U/D PV : R 10
FUN 7
X1
CV: R 0
CLR
PV: R 10
4.2.3 Output Coil and Inverse Output Coil
Output Coil writes the node status into an operand specified by the coil instruction. Invert Output Coil writes the
complement status of node status into an operand specified by the coil instruction. The characteristics depicts at below.
X0 Y0 ORG X 0
OUT Y 0
Y1
OUT NOT Y 1
X0
Y0
Y1
4.2.4 Retentive Output Coil
The coil element can be categorized into two types, namely Retentive and Non Retentive. For example, M0~M799 can be
specified as the Retentive coils and M800~M1399 can be specified as the Non Retentive coils. One way to categorize the
relay type is to divide the relays into groups. Though this method is simple but for the most applications the coils needed
to be retentive may be in a random order. FBs-PLC allows user to set the retentive status of coil individually. When input
the program with mnemonics instructions, if put an “L” after the OUT instruction can declare this specific relay as retentive
output. This can be shown in the diagram below.
X0 X0 Y0 ORG X 0
L
OR Y 0
Y0 AND NOT X 1
OUT L Y 0
4-4
From the above example, if turn the X0 "ON" then "OFF", Y0 will keep at "ON". When change the PLC state from RUN to
STOP then RUN or turn the power off then on, the Y0 still keep at ON state. But if use the OUT Y0 instruction instead of
the OUT L Y0 , Y0 status will be OFF.
4.2.5 Set Coil and Reset Coil
Set Coil writes 1 into an operand specified. Reset Coil writes 0 into an operand specified. The characteristics depicts at
below.
X0 P ORG X 0
EN SET Y 0
SET P Y 0
X1 P
ORG X 1
EN RST Y 0
RST P Y 0
X0
SET
X1
RST
Y0
4.3 Node Operation Instructions
A node is the connection between elements in a ladder diagram consisting of sequential instruction elements (please
refer to Section 1.2). There are four instructions dedicated for node status operation in FBs-PLC. The two instructions,
“OUT TR” and “LD TR”, have been discussed in Section 1.6 of this manual. Using the diagram below, the three node
operation instructions NOT, TU and TD, are illustrated.
ORG X 0
AND X 1
Node B
NOT
X0 X1 Y0 OUT TR 0
TU
Y1 OUT Y 0
Node A LD TR 0
TD
OUT Y 1
4-5
X0
X1
Node A
Incerse Inverse
Node B
differential down differential up
Y0
t
Y1
t
t : Scan time
4-6
Chapter 5 Descriptions of Function Instructions
5.1 The Format of Function Instructions
In this chapter we will introduce the function instructions of FBs-PLC in details. All the explanations for each function will
be divided into four parts including input control, instruction number/name, operand and function output. If use the FP-07
to input the mnemonic instruction, except for the T, C, SET, RST and SFC instructions that can be entered directly by
pressing a single key stroke on FP-07, other function instructions must be entered by key in the instruction number rather
than the instruction name. An example is shown in below.
Ladder Diagram FP-07 Mnemonic code
Example 1: Single input instruction
15 FUN 15
Operation control EN (+1) R 0 CY Carry(FO0)
D: R 0
Example 2: Multiple input instruction
7.UDCTR
Clock CK CV : R 0 CUP Count-Up(FO0) FUN 7
CV: R 0
Up/Down count U/D PV : 10 PV: 10
Clear control CLR
Remark：The words inside the hollow box in mnemonic code field are the prompting message from FP-07 such as D:,
CV:, and Pr: and are not entered by the user.
5.1.1 Input Control
Except for the seven function instructions that do not have input control, the number of the input control of other FBs-PLC
function instructions can be ranged from one to four. Execution of the instructions and operations is dependent on the
input control signal or the combinations of the several input control signals. The ladder programming software for FACON
PLC - Winprollader can help user to complete the complex design and document works. In the ladder program window we
can see all the function instructions were displayed by blocks surrounded with abbreviated words for ease of
comprehension, include inputs, outs, function name, and parameter names. As shown in example 2 above, the first input
mark "CK↑" indicates when the "CK↑" input changes from 0 to 1 (rising edge) the counter will be increased or
decreased by 1 (depending on the "U/D" status). The second input mark "U/D" with a status of 1 represents the word
above slash ("U") and the status 0 represents the word under slash ("D"), that is second input "U/D" states =1, the counter
will be increased by 1 when "CK↑" input from 0 to 1, and when "U/D"=0, the counter will be decreased by 1. The third
input mark "CLR" indicates when this input is 1, the counter will be cleared to 0. Chapter 8~9 give the descriptions of input
control of each function instruction.
Remark: There are total of seven instructions whose input control should be directly connected to the origin-line
those are MCE, SKPE, LBL, RTS, RTI, FOR, and NEXT. Please refer to chapter 6 and 7 for more
detailed explanations.
5-1
All input controls of the function instructions should be connected by the corresponding elements, otherwise a syntax
error will occur. As shown in example 3 below, the function instruction FUN7 has three inputs and three elements before
FUN7. ORG X0, LD X1 and LD X2 corresponds to the first input CK↑, second input U/D and third input CLR.
Example 3:
Ladder Diagram FP-07 Mnemonic code
X0 7.UDCTR
ORG X 0 FUN7 need three
CK CV : R 0 CUP
LD X 1 elements because
X1 it has three inputs
LD X 2
U/D PV : 10
FUN 7
X2 CV : R 0
CLR PV : 10
5.1.2 Instruction Number and Derivative Instructions
As mentioned before, except for the nine instructions that can be entered using the dedicated keys on the keyboard, other
function instructions must be entered using the "instruction number”. Follow the instruction number there are postfixes D,
P, DP can be added which can derive three additional function instructions.
D: Indicates a Double Word (32-bit). The 16-bit word is the basic unit of the registers in FBs-PLC. The data length of R, T
and C (except C200~C255) registers are 16-bit. If a register with 32-bit data length is required, then it is necessary to
combine two consecutive 16-bit registers together such as R1-R0, R3-R2 etc. and those registers are represented by
prefix a D letter before register name such as DR0 represents R1-R0 and DR2 represents R3-R2. If you enter DR0 or
DWY8 in the monitor mode of FP-07, then a 32-bit long value (R1-R0 or WY24-WY8) will be displayed.
B31 B16 B15 B0

DR0 =R1−R0 R1 R0
↑ ↑
High Word register Low Word register
B31 B16 B15 B0

DWY8 =WY24−WY8 WY24 WY8
=Y39～Y8 ↑ ↑
High Word register Low Word register
5-2
Remark: In order to differentiate between 16-bit and 32-bit instructions while using the ladder diagram and
mnemonic code, we add the postfix letter D after the "Instruction number" to represent 32-bit instructions
and the size of their operand are 32-bit as shown in example 4 on P.6-6. The instruction FUN 11D has a
postfix letter D, therefore the source and destination operands need to prefix a letter D as well, such as
the augend Sa : R0 is actually Sa=DR0=R1-R0 and Sb=DR2=R3-R2. Please also pay special attention to
the length of the other operands except source and destination are only one word whether 16-bit or 32-bit
instructions are used.
P: indicates the pulse mode instruction. The instruction will be executed when the status of input control changes from 0
to1 (rising edge). As shown in example 1, if a postfix letter P is added to the instruction (FUN 15P), the instruction FUN
15P will only be executed when the status of input control signal changes from 0 to 1. The execution of the instruction
is in level mode if it does not have a P postfix, this means the instruction will be executed for every scan until the status
of input control changes from 1 to 0. The pulse input is indicated by a symbol "↑", such as CK↑, EN↑, TG↑ etc.. In
this operation manual, an example of the operation statement of a function instruction is shown below.
● When the operation control〝EN〞=1 or〝EN↑〞（P instruction）from 0→1, ………
The first one indicates the execution requirement for non-P instruction (level mode) and the second one indicates the
execution requirement for P instruction (pulse mode). The following waveform shows the result (R0) of FUN15 and
FUN15P under the same input condition.
t is the scan time t t t t t t t t t t
Input control 1
Executes the FUN15P 2
(R0 initial is 0) 0001H 0002H
Executes the FUN15 3
(R0 initial is 0) 0001H 0002H 0003H 0004H 0005H 0006H
DP: Indicates the instruction is a 32-bit instruction operating with pulse mode.
Remark: P instruction is much more time saving than level instruction in program scanning, So user should use P
instruction as much as possible.
5.1.3 Operand
The operand is used for data reference and storage. The data of source (S) operand are only for reference and will not be
changed with the execution of the instruction. The destination (D) operand is used to store the result of operation and its
data may be changed after the execution of the instruction. The following table illustrates the names and functions of
FACON PLC function instruction's operands and types of contacts, coils, or registers that can be used as an operand.
5-3
The names and functions of the major operands:
Abbreviation Name Descriptions
The data of source (S) operand are only for reading and reference and will not be
S Source changed with the execution of the instruction. If there are more than one source
operands, each operand will be identified by the footnote such as Sa and Sb.
The destination (D) operand is used to store the result of operation. The original data
D Destination will be changed after operation. Only the coils and registers which are not write
prohibited can be the destination operand.
L Length Indicates the data size or the length of the table, usually are constants.
A constant most often used as numbers and times. If there are more than one
N Number
constant, each constant will be identified by the footnotes such as Na, Nb, Ns etc..
Used to point to a specific a block of data or a specific data or register in a table.
Pr Pointer Generally the Pr value can be varied, therefore cannot be constant or input register.
(R3840~R3847)
CV Current value Used in T and C instruction to store the current value of T or C
PV Set value Used in T and C instructions for reference and comparison

A combination of a set of consecutive registers forms a table. The basic operation
T Table units are word and double word. If there is more than one table, each table will be
identified by footnotes such as Ta, Tb, Ts and Td etc..
A combination of a set of consecutive registers forms a matrix. The basic operation
M Matrix unit is bit. If there is more than one matrix, each matrix will be identified by footnotes
such as Ma, Mb, Ms and Md etc..
Besides the major operands mentioned above, there are other operands which are used for certain special purposes such
as the operand Fr for frequency, ST for stack, QU for Queue etc.. Please refer to the instruction descriptions for more
details.
The types of the operand and their range: The types of operand for the function instructions are discrete, register
and constant.
a) Discrete operand :
There are total five function instructions that reference the discrete operand, namely SET, RST, DIFU, DIFD
and TOGG. Those five instructions can only be used for operations of Y (external output), M
(internal and special) and S (step) relays. The table shown below indicates the operands and ranges of
the five function instructions.
Range Y M SM S Symbol "O" indicates the D (Destination operand) can use this type of
Y0 M0 M1912 S0
Ope- ∣ ∣ ∣ ∣
coils as operands. The "*" sign above the "O" shown in SM column
rand Y255 M1911 M2001 S999 indicates that should exclude the write prohibited relays as operands.
D ○ ○ ○* ○ Please refer to page I2-8 for introduction of the special relays.
b) Register operand :
The major operand for function instructions is register operand. There are two types of register operands: the
native registers which already is of Words or Double Words data such as R, D, T, C. The other is derivative
registers (WX, WY, WM, WS) which are formed by discrete bits. The types of registers that can be used as
instruction operands and their ranges are all listed in the following table:
5-4
Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR
WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0
16/32-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
P0~P9
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 +/- number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
•
•
•
The "○" symbol in the table indicates can apply this kind of data as operand. The "○*" symbol indicates can apply this
kind of data except the write prohibited registers as operand. To learn more about write prohibited registers please refer
to page 3-6 for introduction of the special register.
When R5000～R8071 are not set to be read only registers, can used as normal registers (read, and write)
Remark 1: The registers with a prefix W, such as WX, WY, WM and WS are formed by 16 bits. For example, WX0
means the register is formed by X0(bit 0)~X15(bit 15). WY144 means the register is formed by Y144(bit
0)~Y159(bit 15). Please note that the discrete number must be the multiple of 8 such as 0, 8, 16, 24....
Remark 2: The last register (Word) in a table can not be represented as a 32-bit operand in the function because 2
Words are required for a 32-bit operand.
Remark 3: TMR（T0～T255）and CTR（C0～C255）are the registers of timers and counters respectively. Although
they can be used as general registers, they also complicate the systems and make debugging more
difficult. Therefore you should avoid writing anything into the TMR or CTR registers.
Remark 4: T0～T255 and C0～C199 are 16-bit register. But C200~C255 are 32-bit register, therefore can’t be
used as 16-bit operands.
Remark 5: Apart from being directly appointed by register’s number (address) as the foregoing discussions, the
register’s operand in the range of R0～R8071 can be combined with pointer register V or Z to make
indirect addressing. Please refer to the example in the next section (Section 5.2) for the description of
using pointer register (XR) to make indirect addressing.
c) Constant operands :
The range of 16-bit constant is between -32768~32767. The range of 32-bit constant is between
-2147483648~2147483647. The constant for several function instructions can only be a positive constant. The
range of 16-bit and 32-bit constants are listed in the table shown below.
Classification Range
16-bit signed number -32768～32767
16-bit un-signed number 0～32767
32-bit signed number -2147483648～2147483647
32-bit un-signed number 0～2147483647
-32768～32767 or
16/32-bit signed number
-2147483648～2147483647
0～32767 or
16/32-bit un-signed number
0～2147483647
It is possible that the length and size of a specific operand, such as L, bit size, N etc.., are different, and the
differences are all directly marked at the operand column. Please refer to the explanations of function
instructions.
5-5
5.1.4 Functions Output (FO)
The “Function Output” (FO) is used to indicate the operation result of the function instruction. Like control input, each
function outputs shown in the screen of programming software are all attached with a word which comes from the
abbreviation of the output functionality. Such as CY derived from CarrY. The maximum number of function outputs is 4
and those are denoted as FO0, FO1, FO2, FO3 respectively. The FO status must be taken out by FO instruction (there is
a FO special key on FP-07 program writing device). The unused FO may be left without connecting to any elements, such
as FO1 (CY) shown in Example 4 below.
Example 4 :
Ladder Diagram Mnemonic Codes
ORG X 0
X0 11D.(+) Y0 FUN 11D
EN Sa : R 0 D=0 Sa: R 0
Sb : R 2 Sb: R 2
U/S D : R 4 CY D: R 4
Y1 FO 0
BR OUT Y 0
FO 2
OUT Y 1
When M1919=0, the FO status will only be updated if the instruction is executed. It will keep the same status until
a new FO status is generated after the instruction is executed again (memory keeping).
When M1919=1, the FO status will be reset to 0 (no memory keeping) if the instruction is not executed.
5.2 Use Index Register(XR) for Indirect Addressing

In the FBs-PLC function instructions, there are some operands that can be combined with pointer register (V、Z、P0~P9)
to make indirect addressing (will be shown in the operand table if it applicable). However, only the registers in the range
R0～R8071 can be combined with an pointer register to perform indirect addressing (other operands such as discrete,
constant and D0～D3071 cannot be used for indirect addressing).
There are twelve pointer registers XR (V、Z、P0~P9). The V register in fact is the R4164 of special registers (R3840～
R4167) , the Z register is the R4165 and the P0~P9 register is the (D4080~D4089). The actual addressed register by
index addressing is just offset the original operand with the content of the index register.
Original Pointer Actual
Operand Register Operand
↓ ↓ ↓
R100 V (If V=50) = R150
100 + 50
(If V=100) = R200
• •
• •
• •
• •
5-6
As shown in the above diagram, you only need to change the V value to change the operand address. After combining
the index addressing with the FBs-PLC function instructions, a powerful and highly efficient control application can be
achieved by using very simple instructions. Using the program shown in the diagram below as an example, you only need
to use a block move instruction (BT_M) to achieve a dynamic block data display, such as a parking management system.
Index Register(P0~P9) Introduction
In indirect addressing application, Rxxxx register can combine V、Z & P0～P9 for index addressing; Dxxxx register can't
combine V、Z for index addressing, but P0～P9 are allowed.
When V、Z index register being combined with the Rxxxx register,
for example, R0 with V、Z, the instruction format is R0V(where V=100, it means R100) or R0Z(where Z=500, it means
R500); when P0～P9 index register being combined with the Rxxxx register, the instruction format is RPn (n=0～9) or
RPmPn (m,n=0～9), for example RP5 (where P5=100, it means R100) or RP0P1(where P0= 100, P1=50, it means150).
When P0～P9 index register being combined with the Dxxxx register, the instruction format is DPn (n=0～9) or DPmPn
(m,n=0～9), for example DP3 (where P3=10, it means D10) or DP4P5 (where P4=100, P5=1, it means D101).
It can combine both P0～P9 index register, for example P2=20, P3=30, when Rxxxx or Dxxxx register combines both
index register, RP2P3 will point to R50, DP2P3 will point to D50, it means the summation of both index register for indirect
addressing.
M1924 08.MOV 1. Index register P2=100 while power up or first run.

EN S: 100
D: P2 2. When X23 changes from 0Æ1, FUN103 will perform the
table movement, the source starts from R100 (P2=100),
the destination starts from R2000, the amount is 4.
X23 103.BT_M Coping the content of R100~R103 for R2000~R2003 at
EN Ts : RP3 first execution, coping the content of R104~R107 for
Td : R2000 R2000~R2003 at second execution…
L : 4
3. Increasing the P2 index register by 4 to point to next 4
X23 11P.(+)
EN Sa : 4 D=0
Sb : P2
U/S D : P2 CY
BR
5-7
Indirect addressing program example
Ladder Diagram Mnemonic Codes
ORG SHORT
103.BT_M
FUN 103
EN Ts : R100 V
Td : R2000 Ts： R100V
L : 4 Td： R2000
L： 4
resident Pointer Register

data base in PLC V Resident 2
R100 Name Sensor
4 Station
R101 Tel. No.
(V=0) Resident 1
R102 Car plate No.
˙
R103 Parking No.
˙
˙ R104 Name
R105 Tel. No.
(V=4) Resident 2
R106 Car plate No.
˙ R107 Parking No. Temporary
˙ ˙
˙ { Display Monitor
˙
˙ ˙ Storage Area ××Community Resident
˙ ˙
˙ ˙ R2000 Name Parking System
˙ ˙
R2001 Tel. No. Name: (R2000)
˙
˙ Name R2002 Car plate No. Tel. No. (R2001)
Tel. No. R2003 Parking No. Car plate No. (R2002)
(V=396) Resident 100
Car plate No. Parking No. (R2003)
Rnnn Parking No.
Description Suppose that there are 100 resident parking spaces available in a parking management system for
community residents. Each resident has a set of basic information including name, telephone number,
number plate and parking number, that occupy four consecutive PLC registers as shown in the above
diagram. A total of 400 registers (R100～R499) are occupied. Each resident is given a card with a unique
card number (the number is 0 for resident 1, 4 for resident 2 etc.. ) for the sensing pass of the main
entrance and parking lot. The card number will be sensed by the PLC and stored into the pointer register
“V”. The attendant’s monitor (LCD or CRT) will only display the data grasped by R2001～R2003 in the
PLC. For example, the card of residence 2 with the card number 4 is sensed, then the register V=4 and
the PLC will immediately move the data in R104～R107 to the temporary display storage area (R2000～
R2003). Hence, the attendant’s monitor can display the data of residence 2 as soon as its card is sensed.
5-8
 Warning
1. Although using pointer register for indirect addressing application is powerful and flexible, but
changing the V and Z values freely and carelessly may cause great damages with erroneous
writing to the normal data areas. The user should take special caution during operation.
2. In the data register range that can be used for indirect addressing application (R0～R8071), the
328 registers R3840～R4167 (i.e. IR, OR and SR) are important registers reserved for system or
I/O usage. Writing at-will to these registers may cause system or I/O errors and may result in a
major disaster. Due to the fact that users may not easily detect or control the flexible register
address changes made by the V and Z values, FBs-PLC will automatically check if the
destination address is in the R3840～R4067 range. If it is, the write operation will not be executed
and the M1969 flag “Illegal write of Indirect addressing” will be set as 1. In case it is necessary to
write to the registers R3840～R4067, please use the direct addressing.
5.3 Numbering System
5.3.1 Binary Code and Related Terminologies
Binary is the basic numbering system of digital computer. Since the PLC operates with discrete ON/OFF values, it is
natural to use binary codes. The following terminologies should be fully understood before go to further topic of
numbering system.
● Bit: (Abbreviated as B, such as B0, B1, and so on) It is the most basic unit of binary value. The status of bit is either
“1” or “0”.
● Nibble: (Abbreviated as NB, such as NB0, NB1, and so on）It is formed by four consecutive bits (e.g. B3～B0) and
can be used to represent a decimal number 0～9 or a hexadecimal number 0～F.
● Byte: (Abbreviated as BY, such as BY0, BY1, and so on) It is formed by two consecutive nibbles (or 8 bits, such as
B7～B0) and can be used to represent a 2-digit hexadecimal number 00～FF.
● Word: (Abbreviated as W, such as W0, W1, and so on) It is formed by two consecutive bytes (or 16 bits, such as B15
～B0) and can be used to represent a 4-digit hexadecimal number 0000～FFFF.
● Double Word: (Abbreviated as DW, such as DW0, DW1, and so on) It is formed by two consecutive words (or 32 bits,
such as B31～B0) and can be used to represent an 8-digit hexadecimal number 00000000～FFFFFFFF.
DW ←Double Word
W1 W0 ←Word
BY3 BY2 BY1 BY0 ←Byte
NB7 NB6 NB5 NB4 NB3 NB2 NB1 NB0 ←Nibble
B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 ←Bit
5-9
● Floating Point Number:
The format of floating point number of Fatek-PLC follows the IEEE-754 standard, which use a double word for storage
and can be expressed as follow:
floating point number = sign + Exponent + Mantissa
▲ If the sign bit is 0 the number is positive, if the sign bit is 1 the number is negative.
▲ The exponent is denoted as 8-bit excess 127.
▲ The mantissa is 23-bit with radix 2. A normalized mantissa always starts with a bit 1, followed by
the radix point, followed by the rest of the mantissa. The leading bit 1, which is always present in a
normalized mantissa, is implicit and is not represented.
● The Conversion rule of Integer to floating is :
S (E -127)
N = ( -1) *2 * ( 1.M ) 0 < E < 255
For example :
0 ( 01111111 )
(1). 1 = ( -1 ) * 2 * ( 1.000………0 )
The sign is represented by 0, the exponent's code in excess 127 is 127 = 01111111, and the significant
bit is 1, resulting in the mantissa being all O's. The simple precision IEEE 754 representation of 1, is
thus :
Code( 1 ) =
= 3F800000H
0 ( 01111110 )
(2). 0.5 = ( -1 ) * 2 * ( 1.000………0 )
The sign is represented by 0, the exponent's code in excess 127 is 127 - 1 = 01111110, and the
significant bit is 1, resulting in the mantissa being all O's. The simple precision IEEE 754 representation
of 0.5, is thus :
Code( 0.5 ) =
= 3F000000H
1 ( 10000111 )
(3). -500.125 = ( -1 ) * 2 * ( 1. 11110100001000000000000)
The sign is represented by 0, the exponent's code in excess 127 is 127 - 1 = 01111110, and the
significant bit is 1, resulting in the mantissa being all O's. The simple precision IEEE 754 representation
of -500.125, is thus :
Code( -500.125 ) =
= C3FA1000H
5 - 10
5.3.2 The Coding of Numeric Numbers for FBs-PLC
FBs-PLC use the binary numbering system for its internal operations that is the data of external BCD inputs must be
converted to binary number before the PLC can process. As we know the binary code is very difficult to read and input to
the PLC for human, therefore FP-07 and WinProladder use the decimal unit or hexadecimal unit to input or to display the
data. But in reality, all the operations taking place in the PLC are performed with binary code.
Remark: If you input or display the data without going through the FP-07 or WinProladder (For instance, input data
into or take out data from PLC through the I/O terminals using thumb wheel switch or seven segment
display), then you have to use the Ladder program to perform the Decimal to Binary conversion. This
enables you to input and display data without using the FP-07 and WinProladder. Please refer to
FUN20(BIN→BCD) and FUN21(BCD→BIN).
5.3.3 Range of Numeric Value
As we have mentioned before that FBs-PLC uses binary numbers for its internal operations. 16-bit and 32-bit are
three different numeric data of FBs-PLC. The ranges of the three numeric values are shown below.
16-bit −32768～32767
32-bit −2147483648～2147483647
-38 38
Floating point number ±(1.8*10 ～3.4*10 )
5.3.4 Representation of Numeric Value (Beginners can skip this section)
The representation and specification of 16-bit and 32-bit numeric values are provided below to enable the user to further
understand the numeric value operation for more complicated applications.
The most significant bits MSB of 16-bits and 32-bits (B15 for 16-bit and B31 for 32-bit) are used to identify positive and
negative numbers (0: positive and 1: negative). The remaining bits (B14~B0 or B30~B0) represent the magnitude of the
number. The following example uses 16-bit for further explanations. Please note that everything also applies to 32-bit
numbers and the only difference is the length.
0: Positive Number
16384
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1
12345 Ö 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 Ö 3039H
(Decimal) B15 B0 (Hexadecimal)
8192+4096+32+16+8+1=12345
In the above example, regardless of its size (16-bit or 32-bit), and starting with the least significant bit LSB (B0). B0 is 1,
B1 is 2, B2 is 4, B3 is 8, and so on. The number represented by the neighboring left bit will double its value (1, 2, 4, 8, 16,
and so on) and the value is the sum of the numbers represented by the bits that are equal to 1.
5 - 11
5.3.5 Representation of Negative Number (Beginners should skip this section)
As prior discussion, when the MSB is 1, the number will be a negative number. The FBs-PLC negative numbers are
represented by 2’S Complement, i.e. to invert all the bits (B15～B0 or B31～B0) of its equivalent positive number (The
so-called 1’S Complement is to change the bits equal 1 to 0 and the bits equal 0 to 1) then add 1. In the above example,
the positive number is 12345. The calculation of its 2’S Complement (i.e. –12345) is described below:
12345 Ö 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 Ö 3039H
1'S
Complement
Ö 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 0 Ö CFC6H
of 12345
+ 1
2'S Complement Ö 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 Ö CFC7H

of 12345
(−12345)
5.4 Overflow and Underflow of Increment (+1) or Decrement (-1) (Beginners should skip this section)
The maximum positive value that can be represented by 16-bit and 32-bit operands are 32767 and 2147483647,
respectively. While the minimum negative values that can be represented by 16-bit and 32-bit operands are –32768
and –2147483648, respectively. When increase or decrease an operand (e.g. when Up/Down Count of a counter or the
register value is +1 or −1), and the result exceeds the value of the positive limit of the operand, then “Overflow” (OVF)
occurs. This will cause the value to cycle to its negative limit (e.g. add 1 to the 16-bit positive limit 32767 will change it
to –32768). If the result is smaller than the negative limit of the operand, then “Underflow” (UDF) occurs. This will cause
the value to cycle to its positive limit (e.g. deducting 1 from the negative limit –32768 will change it to 32767) as shown in
the table below. The flag output of overflow or underflow exists in the FO of FBs-PLC and can be used in cascaded
instructions to obtain over 16-bit or 32-bit operation results.
5 - 12
Increase
(Decrease)
Result 16-bit Operand 32-bit Operand
Overflow/
Underflow
−32767 −2147483646
−32768 −2147483647
Increase OVF=1 32767 OVF=1 −2147483648
32766 2147483647
32765 2147483646
−32767 −2147483647
−32768 −2147483648
Decrease UDF=1 32767 UDF=1 2147483647
32766 2147483646
32765 2147483645
5.5 Carry and Borrow in Addition/Subtraction
Overflow/Underflow takes place when the operation of increment/decrement causes the value of the operand to exceed
the positive/negative limit that can be represented in the PLC, consequently a flag of overflow/underflow is introduced.
Carry/Borrow flag is different from overflow/underflow. At first, there must be two operands making addition (subtraction)
where a sum (difference) and a flag of carry/borrow will be obtained. Since the number of bits of the numbers to be added
(subtracted), to add (subtract) and of sum (difference) are the same (either 16-bit or 32-bit), the result of addition
(subtraction) may cause the value of sum (difference) to exceed 16-bit or 32-bit. Therefore, it is necessary to use
carry/borrow flag to be in coordination with the sum (difference) operand to represent the actual value. The carry flag is
set when the addition (subtraction) result exceeds the positive limit (32767 or 2147483647) of the sum (difference)
operand. The borrow flag is set when addition (subtraction) result exceeds the negative limit (−32768 or −2147483648)
of the sum (difference) operand. Hence, the actual result after addition (subtraction) is equal to the carry/borrow plus the
value of the sum (difference) operand. The FO of FBs-PLC addition/subtraction instruction has both carry and borrow flag
outputs for obtaining the actual result.
MSB LSB
↓ ↓
16-bit／32-bit To Be Added (Subtracted) Operand
+(−) 16-bit／32-bit Addition (Subtraction) Operand
1-bit Carry/Borrow 16-bit or 32-bit Sum (Difference) Operand

While all FBs-PLC numerical operations use 2’S Complement, the representation of the negative value of the sum
5 - 13
(difference) obtained from addition (subtraction) is different from the usual negative number representation. When the
operation result is a negative value, 0 can never appear in the MSB of the sum (difference) operand. The carry flag
represents the positive value 32768 (2147483648) and the borrow flag represents the negative value −32768
(−2147483648).
Negative Value Positive Value

(MSB=1) (MSB=0)
0 Flag
=1
xxx，−2，−1，−32768，，−2，−1，0，1，2，，32767，0，1，xxx

(−2147483648) (2147483647)
Borrow Flag=1 Carry Flag=1
MSB LSB
x x x
x ↓ x ↓ x
C=1 B=0 Z=0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 32769
C=1 B=0 Z=0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32768
C=0 B=0 Z=0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32767
Positive Value
C=0 B=0 Z=0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 32766
C=0 B=0 Z=0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 32765
x x
x x
x x
x x
x x
C=0 B=0 Z=0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2
C=0 B=0 Z=0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
C=0 B=0 Z=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
C=0 B=0 Z=0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 −1
C=0 B=0 Z=0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 −2
x x
x x
x x
x x
x x
Negative Value
C=0 B=0 Z=0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 −32766

C=0 B=0 Z=0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 −32767
C=0 B=0 Z=0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 −32768
C=0 B=1 Z=0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 −32769
C=0 B=1 Z=0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 −32770
x x x
x x x
C = Carry B = Borrow Z = Zero
5 - 14
Chapter 6 Basic Function Instruction
T …………………………………6-2
C …………………………………6-5
SET …………………………………6-8
RST …………………………………6-10
0： MC …………………………………6-12
1： MCE …………………………………6-14
2： SKP …………………………………6-15
3： SKPE …………………………………6-17
4： DIFU …………………………………6-18
5： DIFD …………………………………6-19
6： BSHF …………………………………6-20
7： UDCTR …………………………………6-21
8： MOV …………………………………6-23
9： MOV／ …………………………………6-24
10：TOGG …………………………………6-25
11：(＋) …………………………………6-26
12：(－) …………………………………6-27
13：(＊) …………………………………6-28
14：(／) …………………………………6-30
15：(＋1) …………………………………6-32
16：(－1) …………………………………6-33
17：CMP …………………………………6-34
18：AND …………………………………6-35
19：OR …………………………………6-36
20：→BCD …………………………………6-37
21：→BI
N …………………………………6-38
6 -1
Basic Function Instruction
T TIMER T
Symbol
Operand
Tn: Timer Number.

PV: Preset value of the timer.
TB: Time Base (0.01S, 0.1S, 1S)
Range WX WY WM WS TMR CTR HR IR OR SR ROR DR K

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 0
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 32767
Tn ○
PV ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
● The total number of timers is 256 (T0～T255) with three different time bases, 0.01S, 0.1S and 1S.The
default number and allocation of timers is shown as below (Can be adjusted according to user’s actual
requirements by the “Configuration” function):
T0～T49：0.01S timer（default as 0.00～327.67S）。
T50～T199：0.1S timer（default as 0.0～3276.7S）。
T200～T255：1S timer（default as 0～32767S）。
● FBs-PLC programming tool will lookup the timer’s time base automatically according to the “Memory
Configuration” after the timer number is keyed in. Timer’s time = Time base x Preset value. In the example
1 below, the time base T0 = 0.01S and the PV value = 1000, therefore the T0 timer’s time = 0.01S x 1000 =
10.00S.
● If PV is a register, then Timer’s time = Time base x register content. Therefore, you only need to change
the register content to change the timer’s time. Please refer to Example 2.
※ The maximum error of a timer is a time base plus a scan time. In order to reduce the timing error in the
application, please use the timer with a smaller time base.
Description
● When the time control “EN” is 1, the timer will start timing (the current value will accumulate from 0) until
“Time Up” (i.e. CV≧PV), then the Tn contact and TUP (FO0) will change to 1. As long as the timer control
“EN” input is kept as 1, even the CV of Tn has reached or exceeded the PV, the CV of the timer will
continue accumulating (with M1957 = 0) until it reaches the maximum limit (32767). The Tn contact status
and flag will remain as 1 when CV≧PV, unless the “EN” input is 0. When “EN” input is 0, the CV of Tn will
be reset to 0 immediately and the Tn contact and “Time Up” flag TUP will also change to 0 (please refer to
the diagram c below).
● If the FBS-PLC OS version is higher than V3.0 (inclusive), the M1957 can be set to 1 so the CV will not
accumulate further after “Time Up” and stops at the PV value. The default value of the M1957 is 0,
therefore the status of M1957 can be set before executing any timer instruction in the program to
individually set the timer CV to continue accumulating or stop at the PV after “Time Up” (please refer to the
diagram d below).
6 -2
T TIMER T
Example 1 Constant preset value
Ladder diagram Key operations Mnemonic code
ORG ORG X 1
X1 .01S Y0
EN T0 1000 TUP T0 PV: 1000
P
SET M1957
X1 FO 0
.01S
EN T1 1000 TUP OUT OUT Y 0
ORG ORG SHORT
SET M 1957
ORG ORG X 1
An example of taking
“Time-Up” signal directly T1 PV: 1000
from FO0.
X1
327.67S
32767
10.0S
1000
T0
c (CV)
0
M1957=0 T0
Y0 or
(Defaulted)
1000
T1 CV
0
(CV)
d
T1
M1957=1
Time Start Time-Up
Example 2 Variable PV
The preset value (PV) shown in example 1 is a constant which is equal to 1000. This value is fixed and can not
be changed once programmed. In many circumstances, the preset time of the timers needs to be varied while
PLC running. In order to change the preset time of a timer, can first use a register as the PV operand (R or WX,
WY...) and then the preset time can be varied by changing the register content. As shown in this example, if set
R0 to100, then T becomes a 10S Timer, and hence if set R0 to 200, then T becomes a 20S Timer.
6 -3
T TIMER T
ORG X 1
X1 .1S
EN T50 R 0 TUP
T 50 PV: R 0
T50 Y0
ORG T 50
OUT Y 0
An example of applying
the “time-up” status by
using the T50 contact.
X1
200
100
T50 0
(current value)
10.0S
c When R0=100 Y0
20.0S
d When R0=200 Y0
Time Start c Time-Up d Time-Up
Remark: If the preset value of the timer is equal to 0, then the timer's contact status and FO0 (TUP) become 1
("EN" input must be at 1) immediately after the PLC finishes its first scan because "Time-Up" has
occurred. (TUP) stays at 1 until "EN" input changes to 0.
6 -4
COUNTER
C C
（16-Bit: C0～C199，32-Bit: C200～C255）
Symbol
Operand
Cn: The Counter number

PV: Preset value

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Cn ○
PV ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
● There are total 200 16-Bit counters (C0~C199). The range of preset value is between 0~32767. C0~C139
are Retentive Counters and the CV value will be retained when the PLC turns on or RUN again after a
power failure or a PLC STOP. For Non Retentive Counters, if a power failure or PLC STOP occurs, the CV
value will be reset to 0 when the PLC turns on or RUN again.
● There are total 56 32-Bit counters (C200~C255). The range of the preset value is between 0~2147483647.
C200~C239 are Retentive Counters and C240~C255 are Non Retentive Counters.
● The default number and assignment of the counters are shown below, if necessary can use the
"CONFIGURATION" function to change the settings.
● To insure the proper counting, the sustain time of input status of CLK should greater than 1 scan time.
● The max. counting frequency with this instruction can only up to 20Hz, for higher frequency please use the
high-speed soft/hardware counter.
Description
● When "CLR" is at 1, all of the contact Cn, FO0 (CUP), and CV value of the counter CV are cleared to 0 and
the counter stops counting.
● When "CLR" is at 0, the counter is allowed to count up. The Counter counts up every time the clock "CK↑"
changes from 0 to 1 (adds 1 to the CV) until the cumulative current value is equal to or greater than the
preset value (CV>=PV), the counter "Count-Up" and the contact status of the counter Cn and FO0 (CUP)
changes to 1. If the input status of clock continues to change, even the cumulative current value is equal
and greater than the preset value, the CV value will still accumulate until it reaches the up limit at 32767 or
2147483647. The contact Cn and FO0 (CUP) stay at 1 as long as CV>=PV unless the "CLR" input is set to
1.（please refer the diagram c below）。
● If the FBS-PLC OS version is higher than V3.0 (inclusive), the M1973 can set to 1 so the CV will not
accumulate further after “Count Up” and stops at the PV. M1973 default value is 0, therefore the status of
M1973 can be set before executing any counter instruction in the program to individually set the counter
CV to continue accumulating or stops at the PV after “Count Up” (please refer to the diagram d below).
6 -5
COUNTER
C C
（16-Bit: C0～C199, 32-bit: C200～C255）
Example 1 16-Bit Fixed Counter
ORG ORG SHORT

RST M1973 RST M 1973
X0 Y1
ORG ORG X 0
CK C 1 CUP
X1 PV : 5 LD LD X 1
CLR
C 1 PV: 5
SET M1973
FO 0
X0
OUT Y 1
CK C 2 CUP
OUT
X1 PV : 5 ORG SHORT
CLR ORG
SET M 1973
ORG X 0
ORG
An example of applying LD X 1
LD
the “Count-Up” status by C 2 PV: 5
using FO0 directly.
X0
X1
32767
32766
6
5
4
3
2
1 0
0
c C1
32767 times
M1973=0 5 times
(Defaulted) Y1
5
4
3
2
C2 1 0
d (CV)
0
M1973=1 C2
Count Start Count-Up
Example 2 32-Bit counter with variable preset value
Like a timer, if the PV of a counter is changed to a register (such as R, D, and so on), the counter will use the
register contents as the counting PV. Therefore, only need to change the register contents to change the PV of
the counter while PLC is running. Below is an example of a 32-bit counter that uses the data register R0 as the
PV (in fact it is the 32-bit PV formed by R1 and R0).
6 -6
COUNTER
C C
（16-Bit: C0～C199, 32-Bit: C200～C255）
X0 ORG X 0
ORG
CK C200 CLR
X1 PV : R 0 LD LD X 1
CLR
C200
C200 Y1
PV: R 0
ORG
ORG C 200
OUT OUT Y 1
An example of applying
the “time-up” status by
using the C200 contact.
X0
X1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C200
(R1=0)
4 times
c When R0=4 Y1
9 times
d When R0=9 Y1
Count Start Count-Up Count-Up
Remark: If the preset value of the counter is 0 and "CLR" input also at 0, then the Cn contact status and FO0
(CUP) becomes 1 immediately after the PLC finishes its first scan because the "Count-Up" has occurred.
It will stay at 1 regardless how the CV value varies until "CLR" input changes to 1.
6 -7
SET
SET D P SET D P
(Set coil or all the bits of register to 1)
Symbol
Operand
D: destination to be set
(the number of a coil or a register)
Range Y M SM S WY WM WS TMR CTR HR OR SR ROR DR

Y0 M0 M1912 S0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand Y255 M1911 M2001 S999 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095
D ○ ○ ○* ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
Description
● When the set control "EN" =1 or "EN↑" ( P instruction ) is from 0 to 1, sets the bit of a coil or all bits of a
register to 1.
Example 1 Single Coil Set
Ladder Diagram Key Operations Mnemonic Codes
ORG ORG X 0
X0 P
EN SET Y 0 SET P Y 0
X1 P ORG ORG X 1
EN RST Y 0
RST P Y 0
X0
SET
X1
RST
Y0
6-8
SET
SET D P SET D P
(Set coil or all the bits of register to 1)
Example 2 Set 16-Bit Register
X0 P ORG ORG X 0
EN SET R 0
SET P R 0
B15 B0
↓ ↓
D R0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0
ØX0＝
B15 B0
↓ ↓
D R0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Example 3 32-Bit Register Set
X0 D ORG ORG X 0
EN SET R 0
SET D R 0
B31 R1 R0 B0
↓ ∣ ↓
D R0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 0 0 0 1
ØX0＝1
D R0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6-9
RESET
RST D P RST D P
(Reset the coil or the register to 0)
Symbol
Operand
D: Destination to be reset
(the number of a coil or a register)
Range Y M SM S WY WM WS TMR CTR HR OR SR ROR DR

Y0 M0 M1912 S0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand Y255 M1911 M2001 S999 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095
D ○ ○ ○* ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
Description
● When the reset control "EN" =1 or "EN↑" ( P instruction ) from 0 to 1, resets the coil or register to 0.
Example 1 Single Coil Reset
Please refer to example 1 for the SET instruction shown in page 6-8.
Example 2 16-Bit Register Reset
X0 P ORG ORG X 0
EN RST R 0
RST P R 0
6 - 10
RESET
RST D P RST D P
(Reset the coil or register to 0)
B15 B0
↓ ↓
D R0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0
ØX0＝
B15 B0
↓ ↓
D R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Example 3 32-Bit Register Reset
ORG ORG X 0
X0 D
EN RST WM1368 RST D WM1368
M1399 WM1384 WM1368 M1368

↓ ∣ ↓
D WM1368 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1
ØX0＝1
D WM1368 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6 - 11
FUN 0 FUN 0
MATER CONTROL LOOP START
MC MC
Symbol
Operand
N: Master Control Loop number (N=0~127)

the number N cannot be used repeatedly.
Description
● There are a total of 128 MC loops (N=0~127). Every Master Control Start instruction, MC N, must
correspond to a Master Control End instruction, MCE N, which has the same loop number as MC N.
They must always be used in pairs and you should also make sure that the MCE N instruction is after the
MC N instruction.
● When the Master Control input "EN/" is 1, then this MC N instruction will not be executed, as it does not
exist.
● When the Master Control input "EN/" is 0, the master control loop is active, the area between the MC N
and MCE N is called the Master Control active loop area. All the status of OUT coils or Timers within
Master Control active loop area will be cleared to 0. Other instructions will not be executed.
Example
ORG
X0 0. ORG X 0
EN MC 1
FUN 0
X1 Y0
N： 1
ORG
ORG X 1
X2 1S
T201 10 OUT
OUT Y 0
T201 Y1 ORG ORG X 2
T201 PV： 10
1.
MCE 1
ORG T 201
X1 Y2 ORG
OUT OUT Y 1
FUN 1
N： 1
ORG X 1
ORG
OUT Y 2
OUT
6 - 12
FUN 0 FUN 0
MATER CONTROL LOOP START
MC MC
X0
X1
X2
10
0
T201
Y0
10S
Y1
Y2
Remark1:MC/MCE instructions can be used in nesting or

X0 0.
interleaving as shown to the right:
MC MC 1
Remark2:•When M1918=0 and the master input changes from
0→1, and if pulse type function instructions exist in X1 0.
the master control loop, then these instructions will MC MC 2
have a chance to be executed only once (when the
first time the master control input changes from 0→1). X2 0.
Afterwards, no matter how many times the master MC MC 3
control input changes from 0→1, the pulse type
function instructions will not be executed again. 1.
• When M1918=1 and the master control input MC MC 2
changes from 0 → 1, and if pulse type function
instructions exist in the master control loop, then 1.
each time the master control input changes from 0→ MC MC 1
1 the pulse type function instructions in the master
control loop will be executed as long as the action 1.
conditions are satisfied. MC MC 3
•When a counting instruction exists in the master
control loop, set M1918 to 0 can avoid counting error.
•When the pulse type function instructions in the
master control loop must act upon the 0→1 input
change by the master control, the flag M1918 should
be set to 1.
6 - 13
FUN 1 FUN 1
MASTER CONTROL LOOP END
MCE MCE
Symbol
Operand
N: Master Control End number (N=0~127) N

can not be used repeatedly.
Description
● Every MCE N must correspond to a Master Control Start instruction. They must always be used as a pair
and you should also make sure that the MCE N instruction is after the MC N instruction. After the MC N
instruction has been executed, all output coil status and timers will be cleared to 0 and no other instructions
will be executed. The program execution will resume until a MCE instruction which has the same N number
as MC N instruction appears.
● MCE instruction does not require an input control because the instruction itself forms a network which other
instructions can not connect to it. If the MC instruction has been executed then the master control operation
will be completed when the execution of the program reaches the MCE instruction. If MC N instruction has
never been executed then the MCE instruction will do nothing.
Description
● Please refer to the example and explanations for MC instruction.
6-14
FUN 2 FUN 2
SKIP START
SKP SKP
Symbol
Operand
N: Skip loop number (N=0~127),

N can not be used repeatedly.
Description
● There are total 128 SKP loops (N=0~127). Every skip start instruction, SKP N, must correspond to a skip
end instruction, SKPE N, which has the same loop number as SKP N. They must always be used as a pair
and you should also make sure that the SKPE N instruction is after the SKP N instruction.
● When the skip control "EN" is 0, then the Skip Start instruction will not be executed.
● When the skip control "EN" is 1, the range between the SKP N and SKPE N which is so called the Skip
active loop area will be skipped, that is all the instructions in this area will not be executed. Therefore the
statuses of the discrete or registers in this Skip active loop area will be retained.
Example
X0 2. ORG ORG X 0
EN SKP 1
FUN 2
X1 Y0
N： 1
X2 1S
ORG ORG X 1
EN T201 10 OUT OUT Y 0
T201 Y1
ORG ORG X 2
T201 PV： 10
3.
SKPE 1
X1 Y2 ORG ORG T 201
OUT
OUT Y 1
FUN 3
N： 1
ORG ORG X 1
OUT OUT Y 2
6 - 15
FUN 2 FUN 2
SKIP START
SKP SKP
X0
X1
X2
10
0 0
T201
Y0
10S
Y1
Y2
6-16
FUN 3 FUN 3
SKIP END
SKPE SKPE
Symbol
Operand
N： SKIP END Loop number (N=0~127) N

can not be used repeatedly.
Description
● Every SKPE N must correspond to a SKP N instruction. They must always be used as a pair and you
should also make sure that the SKPE N instruction is behind the SKP N instruction.
● SKPE instruction does not require an input control because the instruction itself forms a network which
other instructions can not connect to it. If the SKP N instruction has been executed then the skip operation
will be completed when the execution of the program reaches the SKPE N instruction. If SKP N instruction
has never been executed then the SKPE instruction will do nothing.
Example
● Please refer to the example and explanations for SKP N instruction.
Remark : SKP/SKPE instructions can be used by nesting or interleaving. The coding rules are the same as for
the MC/MCE instructions. Please refer to the section of MC/MCE instructions.
6 - 17
FUN 4 FUN 4
DIFFERENTIAL UP
DIFU DIFU
Symbol
Operand
D: a specific coil number where the result of

the Differential Up operation is stored.
Range Y M SM S
Y0 M0 M1912 S0
Ope- ∣ ∣ ∣ ∣
rand Y255 M1911 M2001 S999
D ○ ○ ○* ○
Description
● The DIFU instruction is used to output the up differentiation of a node status (status input to "TG↑") and
the pulse signal resulting from the status change at the rising edge of the "TG↑" for one scan time is
stored to a coil specified by D.
● The functionality of this instruction can also be achieved by using a TU contact.
Example The results of the following two samples are exactly the same
Example 1
ORG ORG X 1
X1 4.
TG DIFU Y 0 FUN FUN 4
D： Y 0
Example 2
X1 Y0
ORG ORG TU X 1
OUT OUT Y 0
X1
t t : scan time
Y0
6-18
FUN 5 FUN 5
DIFFERENTIAL DOWN
DIFD DIFD
Symbol
Operand
N: a specific coil number where the result of

the Differential Down operation is stored.
Range Y M SM S
Y0 M0 M1912 S0
Ope- ∣ ∣ ∣ ∣
rand Y255 M1911 M2001 S999
D ○ ○ ○* ○
Description
● The DIFD instruction is used to output the down differentiation of a node status (status input to "TG↓") and
the pulse signal resulting from the status change at the falling edge of the "TG↓" for one scan time is
stored to a coil specified by D.
● The functionality of this instruction can also be achieved by using a TD contact.
Example The results of the following two samples are exactly the same
Example 1 ORG X 1
ORG
X1 5.
TG DIFD Y 0 FUN FUN 5
D： Y 0
Example 2
ORG ORG TD X 1
X1 Y0
OUT OUT Y 0
X1
t t : scan time
Y0
6 - 19
FUN 6 D P BIT SHIFT FUN 6 D P

BSHF (Shifts the data of the 16-bit or 32-bit register to left or to right by one bit) BSHF
Symbol
Operand
D: The register number for shifting
Range WY WM WS TMR CTR HR OR SR ROR DR

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
Description
● When the status of clear control "CLR" is at 1, then the data of register D and FO0 will all be cleared to 0.
Other input signals are all in effect.
● When the status of clear control is "CLR" at 0, then the shift operation is permissible. When the shift control
"EN" = 1 or "EN↑" ( P instruction) from 0 to 1, the data of the register will be shifted to right (L/R=0) or to
left (L/R=1) by one bit. The shifted-out bit (MSB when shift to left and LSB when shift to right) for both
cases will be sent to FO0. The vacated bit space (LSB when shift to left and MSB when shift to right) due to
shift operation will be filled in by the input status of fill-in bit "INB".
Example Shifts the 16-bit register data
Ladder diagram Key Operations Mnemonic Codes
ORG ORG X 1
X1 6P.BSHF Y0 LD LD X 2
EN D : R 3 OTB
LD LD X 3
X2
INB LD LD X 4
X3 FUN FUN 6P
L/R
D： R 3
X4
CLR FO 0
OUT OUT Y 0
B15 B0
X3=1
← ←←←←←←←←←←←←←←←← ←
(Left shift) Y0 X2
Shifts the 16-bit data to left by one bit
B15 B0
X3=0
→ →→→→→→→→→→→→→→→→ →
(Right shift) X2 Y0
Shifts the 16-bit data to right by one bit
6 - 20
FUN 7 D UP/DOWN COUNTER FUN 7 D

UDCTR (16-bit or 32-bit up and down 2-phase Counter) UDCTR
Symbol
Ladder symbol Operand
7D.UDCTR
Clock CK CV : CUP Count-UP (FO0)
CV: The number of the Up/Down Counter
PV: Preset value of the counter or it's
Up/Down count
PV :
U/D register number
Clear counter CLR

16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/− number
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095
CV ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
PV ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Description
● When the clear control “CLR” is 1, the counter’s CV will be reset to 0 and the counter will not be able to
count.
● When the clear control “CLR” is 0, counting will then be allowed. The nature of the instruction is a P
instruction. Therefore, when the clock “CK↑” is 0→1 (rising edge), the CV will increased by 1 (if U/D=1) or
decreased by 1 (if U/D=0).
● When CV=PV, FO0(“Count-Up) will change to 1”. If there are more clocks input, the counter will continue
counting which cause CV≠PV. Then, FO0 will immediately change to 0. This means the “Count-Up” signal
will only be equal to 1 if CV=PV, or else it will be equal to 0 (Care should be taken to this difference from
the “Count-Up” signal of the general counter).
● The upper limit of up count value is 32767 (16-bit) or 2147483647 (32-bit). After the upper limit is reached,
if another up count clock is received, the counting value will become –32768 or -2147483648 (the lower
limit of down count).
● The lower limit of down count value is -32767 (16-bit) or -2147483647 (32-bit). After the lower limit is
reached, if another down count clock is received, the counting value will become 32768 or 2147483648
(the upper limit of up count).
● If U/D is fixed as 1, the instruction will become a single-phase up count counter. If U/D is fixed as 0, the
instruction will become a single-phase down count counter.
Example The diagram below is an application example of UDCTR instruction being applied to an encoder.
Red (POWER + 24VDC)

Green (B phase)
White (A phase)
2-phase encoder Black
SW
C X16 X17 X18
PLC
6 - 21
FUN 7 D UP/DOWN COUNTER FUN 7 D

UDCTR (16-bit or 32-bit up/down 2-phase Counter) UDCTR
ORG ORG X 18
X18 7.UDCTR Y0 LD LD X 17
CK CV : R 0 CUP
LD LD X 16
X17
U/D PV : - 3 FUN 7
X16 CV： R 0
CLR
PV： − 3
FO 0
OUT OUT Y 0
Up(add) Down(subtract)
X16
X17
X18
3
2 2
1 1
0 0
R0
-1
-2
-3
-4
Y0
Remark 1: Since the counting operation of UDCTR is implemented by software scanning, therefore if the clock
speed is faster than the scan speed, lose count may then happen (generally the clock should not
exceed 20Hz depending on the size of the program). Please use the software or hardware high-speed
counter in the PLC. Refer to the “High Speed Counter Application” in the Advanced Manual.
Remark 2: In order to ensure the proper counting, the sustain time of the status of clock input should greater than
1 scan time.
6 - 22
FUN 8 D P MOVE FUN 8 D P

MOV (Moves data from S to D) MOV
Description
Operand
S: Source register number

D: Destination register number
The S, N, D may combine with V, Z, P0~P9 to serve
indirect addressing

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 V、Z
16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/− number
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0~P9
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Move (write) the data of S to a specified register D when the move control input "EN" =1 or "EN↑" ( P
instruction) from 0 to 1.
Example Writes a constant data into a 16-bit register.
ORG ORG X 0
X0 8P.MOV
FUN 8P
EN S : 10
D : R 0 S： 10
D： R 0
S K 10
ØX0＝
D R0 10
6 - 23
FUN 9 D P MOVE INVERSE FUN 9 D P

MOV/ (Inverts the data of S and moves the result to a specified device D) MOV/
Symbol
Operand
S: Source register number

D: Destination register number
S, N, D may combine with V, Z, P0~P9 to serve
indirect addressing

16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/− number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Inverts the data of S (changes the status from 0 to 1 and from 1 to 0) and moves the results to a specified
register D when the move control input "EN" =1 or "EN↑" ( P instruction) from 0 to1.
Example Moves the inverted data of a 16-bit register to another 16-bit register.
ORG ORG X 0
X0 9.MOV/
EN S : R 0 FUN 9
D : WY 8 S： R 0
D： WY 8
B15 B0
S R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5555H
ØX0＝1
Y23 Y8
↓ ↓
D WY8 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 AAAAH
6 - 24
FUN 10 TOGGLE SWITCH FUN 10

TOGG (Changes the output status when the rising edge of control input occur) TOGG
Symbol
Operand
D: the coil number of the toggle switch
Range Y M SM S
Y0 M0 M1912 S0
Ope- ∣ ∣ ∣ ∣
rand Y255 M1911 M2001 S999
D ○ ○ ○* ○
Description
● The coil D changes its status (from 1 to 0 and from 0 to 1) each time the input "TG↑" is triggered from 0 to
1 (rising edge).
Example
ORG ORG X 0
X0 10.
TG TOGG Y 0 FUN 10
D： Y 0
X0
Y0
6-25
FUN 11 D P ADDITION FUN 11 D P

（＋） (Performs addition of the data specified at Sa and Sb and stores the result in D) （＋）
Symbol
Operand
Sa: Augend
Sb: Addend
D : Destination register to store the results
of the addition
Sa, Sb, D may combine with V, Z, P0~P9
to serve indirect addressing

Ope- 16/32-bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +/− number
WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0~P9
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Performs the addition of the data specified at Sa and Sb and writes the results to a specified register D
when the add control input "EN" =1 or "EN↑" ( D instruction) from 0 to 1. If the result of addition is equal to
0 then set FO0 to 1. If carry occurs (the result exceeds 32767 or 2147483647) then set FO1 to 1. If borrow
occurs (adding negative numbers resulting in a sum less than -32768 or -2147483648), then set the FO2 to
1. All the FO statuses are retained until this instruction is executed again and overwritten by a new result.
Example 16-bit addition
ORG ORG X 0
X0 11P.(+)
EN Sa : R 0 D=0 FUN 11P
Sb : R 1 Y0 Sa： R 0
U/S D : R 2 CY
Sb： R 1
D： R 2
BR
FO 1
OUT OUT Y 0
Sa R0 12345
R0＋R1＝32770
Sb R1 20425
ØX0＝
D R2 2 32768+2=32770
Y0＝1 (carry 1 represents ＋32768)
6-26
FUN 12 D P SUBTRACTION FUN 12 D P

（−） (Performs subtraction of the data specified at Sa and Sb and stores the result in D) （−）
Symbol
Operand
Sa: Minuend
Sb: Subtrahend
D : Destination register to store the
results of the subtraction

Ope- 16/32-bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/− number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Performs the subtraction of the data specified at Sa and Sb and writes the results to a specified register D
when the subtract control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the result of subtraction is
equal to 0 then set FO0 to 1. If carry occurs (subtracting a negative number from a positive number and the
result exceeds 32767 or 2147483647), then set FO1 to 1. If borrow occurs (subtracting a positive number
from a negative number and the resulted difference is less than -32768 or -2147483648), then set FO2 to 1.
All the FO statuses are retained until this instruction is executed again and overwritten by a new result.
Example 16-bit subtraction
ORG ORG X 0
X0 12P.(-) FUN 12
EN Sa : R 0 D=0
Sa： R 0
Sb : R 1 Y2
Sb： R 1
U/S D : R 2 CY
D： R 2
BR
FO 2
OUT OUT Y 2
Sa R0 －5
R0－R1＝－32772
Sb R1 32767
ØX0＝1
D R2 －4 －32768－4＝－32772
Y2＝1（borrow 1 represents－32768）Please refer to section 6.5
6-27
FUN 13 D P MULTIPLICATION FUN 13 D P

（＊） (Performs multiplication of the data specified at Sa and Sb and stores the result in D) （＊）
Symbol
Operand
Sa: Multiplicand
Sb: Multiplier
D : Destination register to store the
results of the multiplication.
Sa, Sb, D may combine with V, Z,
P0~P9 to serve indirect addressing

Ope- 16/32-bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/− number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Performs the multiplication of the data specified at Sa and Sb and writes the results to a specified register
D when the multiplication control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the product of
multiplication is equal to 0 then set FO0 to 1. If the product is a negative number, then set FO1 to 1.
Example 1 16-bit multiplication
ORG ORG X 0
X0 13P.(*)
FUN 13P
EN Sa : R 0 D=0
Sb : R 1 Sa： R 0
U/S D : R 2 D<0 Sb： R 1
D： R 2
R0
Sa Multiplicand
12345
R1
× Sb Multiplier
4567
R3 R2
D Product
56379615
6-28
FUN 13 D P MULTIPLICATION FUN 13 D P

（＊） (Performs multiplication of the data specified at Sa and Sb and stores the result in D) （＊）
Example 2 32-bit multiplication
ORG ORG X 0
X0 13P.(*)
FUN 13D
EN Sa : R 0 D=0
Sb : R 2 Sa： R 0
U/S D : R 4 D<0 Sb： R 2
D： R 4
R1 R0
Sa Multiplicand
12345678
× Sb R3 R2 Multiplier
R7 R6 R5 R4
D Product
5629629168
6-29
FUN 14 D P DIVISION FUN 14 D P

（／） (Performs division of the data specified at Sa and Sb and stores the result in D) （／）
Symbol
Operand
Sa: Dividend
Sb: Divisor
of the division.

Ope- 16/32-bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +/− number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Performs the division of the data specified at Sa and Sb and writes the quotient and remainder to registers
specified by register D when the division control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the
quotient of division is equal to 0 then set FO0 to 1. If the divisor Sb=0 then set the error flag FO1 to 1 without
executing the instruction.
Example 1 16-bit division
ORG ORG X 0
X0 14P.(/)
FUN 14
EN Sa: R 0 D=0
Sb: R 1 Sa： R 0
U/S D: R 2 ERR Sb： R 1
D： R 2
R0
Sa Dividend
256
R1
÷ Sb Divisor
12
R3 R2
D
4 21
Remainder Quotient
6-30
FUN 14 D P DIVISION FUN 14 D P

（／） (Performs division of the data specified at Sa and Sb and stores the result in D) （／）
Example 2 32-bit division
ORG ORG X 0
X0 14P.(/)
FUN 14D
EN Sa: R 0 D=0
2 Sa： R 0
Sb: R
U/S D: R 4 ERR Sb： R 2
D： R 4
R1 R0
Sa Dividend
2147483647
R3 R2
÷ Sb Divisor
1234567
R7 R6 R5 R4
D
571634 1739
Remainder Quotient
6-31
FUN 15 D P INCREMENT FUN 15 D P

（＋1） (Adds 1 to the D value) （＋1）
Operand
D : The register to be increased

D may combine with V, Z, P0~P9 to serve
indirect addressing
Range WY WM WS TMR CTR HR OR HR HSCR RTCR SR ROR DR XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3920 R4096 R4128 R4136 R5000 D0 V、 Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3919 R4047 R4127 R4135 R4167 R8071 D4095 P 0 ~ P 9
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
● Adds 1 to the register D when the increment control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If
the value of D is already at the upper limit of positive number 32767 or 2147483647, adding one to this
value will change it to the lower limit of negative number -32768 or -2147483648. At the same time, the
overflow flag FO0 (OVF) is set to 1.
Example 16-bit increment register
ORG
ORG TU X 0
X0 15.
EN (+1) R 0V OVF FUN 15
D : R 0V
When V＝100，0＋100＝100
D R100 1
ØX0＝
D R100 2
6-32
FUN 16 D P DECREMENT FUN 16 D P

（－1） (Subtracts 1 from the D value) （－1）
Operand
D : The register to be decreased

D may combine with V, Z, P0~P9 to
serve indirect addressing
Range WY WM WS TMR CTR HR OR HR HSCR RTCR SR ROR DR XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3920 R4096 R4128 R4136 R5000 D0 V、 Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3919 R4047 R4127 R4135 R4167 R8071 D4095 P 0 ~ P 9
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Description
● Subtracts 1 from the register D when the decrement control input "EN" =1 or "EN↑" ( P instruction) from 0
to 1. If the value of D is already at the lower limit of negative number -32768 or -2147483648, subtracting
one from this value will change it to the upper limit of positive number 32767 or 2147483647. At the same
time, the underflow flag FO0 (UDF) is set to 1.
Example 16-bit decrement register
ORG
ORG X 0
X0 16P.
EN (-1) R 0 UDF FUN 16P
D : R 0
D R0 0
ØX0＝
D R0 －1
6-33
FUN 17 D P COMPARE FUN 17 D P

CMP (Compares the data of Sa and Sb and outputs the results to function Outputs) CMP
Operand
Sa: The register to be compared
Sb: The register to be compared

Sa, Sb may combine with V, Z, P0~P9 to
Range WX WY WM WS TMR CTR HR IR OR HR HSCR RTCR SR ROR DR K

WX0 WY0 WM0 WS0 T0 C0 R0 R3804 R3904 R3920 R4096 R4128 R4136 R5000 D0
Ope- 16/32 bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +/-number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
● Compares the data of Sa and Sb when the compare control input "EN" =1 or "EN↑" ( P instruction) from 0 to
1. If the data of Sa is equal to Sb, then set FO0 to 1. If the data of Sa>Sb, then set FO1 to 1. If the data of
Sa<Sb, then set FO2 to 1. If the data of Sa < Sb, then set the FO2 to 1.
Example Compares the data of 16-bit register
ORG
X0 17.CMP ORG X 0
EN Sa : R 0 a=b
FUN 17
Sb : R 1
Sa : R 0
U/S a>b
Sb : R 1
Y0
a<b FO 2
OUT
OUT Y 0
● From the above example, we first assume the data of R0 is 1 and R1 is 2, and then compare the data by
executing the CMP instruction. The FO0 and FO1 are set to 0 and FO2 (a<b) is set to 1 since a<b.
● If you want to have the compound results, such as≧、≦、< > etc., please send =、< and > results to relay first
and then combine the result from the relays.
● M1919=0, when this command in not executed, FO0, FO1, FO2 will remain in the status at last execution.
● M1919=1, when this command in not executed, FO0, FO1, FO2 are all cleared to 0.
● Control M1919 properly to obtain memory-holding function for functional command output.
6-34
FUN 18 D P FUN 18 D P
LOGICAL AND
AND AND
Operand
Sa: The register to be ANDed

Sb: The register to be ANDed
D : The register to store the result of AND
The Sa, Sb, D may combine with V, Z, P0~P9 to
serve indirect addressing application

16/32 bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/-number
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3919 R4047 R4127 R4135 R4167 R8071 D4095
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● Performs logical AND operation for the data of Sa and Sb when the operation control input "EN" =1 or "EN↑"
( P instruction) from 0 to 1. This operation compares the corresponding bits of Sa and Sb (B0~B15 or
B0~B31). The bit in the D is set to 1 if both of the corresponding bits data of Sa and Sb is 1. The bit in the D is
set to 0 if one of the corresponding bits is 0.
Example Operation of 16-bit logical AND
ORG ORG X 0
X0 18P.AND
FUN 18P
EN Sa : R 0 D=0
Sb : R 1 Sa : R 0
D : R 2
Sb : R 1
D: R 2
B15 B0
↓ ↓
Sa R0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1
Sb R1 1 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0
ØX0＝
B15 B0
↓ ↓
D R2 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0
6-35
LOGICAL OR
OR OR
Operand
Sa: The register to be ORed

Sb: The register to be ORed
D : The register to store the result of OR
The Sa, Sb, D may combine with V, Z, P0~P9 to

Ope- 16/32 bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +/-number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● Performs logical OR operation for the data of Sa and Sb when the operation control input "EN" =1 or "EN↑"
( P instruction) from 0 to 1. This operation compares the corresponding bits of Sa and Sb (B0~B15 or
B0~B31). The bit in the D is set to 1 if one of the corresponding of Sa or Sb is 1. The bit in the D is set to 0 if
both of the corresponding bits of Sa and Sb is 0.
Example Operation of 16-bit logical OR
ORG
ORG X 0
X0 19.OR
Sa : R 0 D=0
FUN 19
EN
Sb : R 1 Sa : R 0
D : R 2 Sb : R 1
D: R 2
B15 B0
↓ ↓
Sa R0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1
Sb R1 1 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0
ØX0＝1
B15 B0
↓ ↓
D R2 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
6-36
FUN 20 D P BIN TO BCD CONVERSION FUN 20 D P

→BCD (Converts BIN data of the device specified at S into BCD and stores the result in D) →BCD
Operand
S : The register to be converted

D : The register to store the converted data
(BCD code)
The S, D may combine with V, Z, P0~P9 to serve
indirect addressing

16/32 bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● FB-PLC uses binary code to store and to execute calculations. If want to send the internal PLC data to the
external displays such as seven-segment displays, it is more convenient for us to read the result on screen
by converting the BIN data to BCD data. For example, it is more clear for us to read the reading "12"
instead of the binary code "1100."
● Converts BIN data of the device specified at S into BCD and writes the result in D when the operation
control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the data in S is not a BCD value (0~9999 or
0~9999999), then the error flag FO0 is set to 1 and the old data of D are retained.
Example 16-bit BIN to BCD conversion
ORG ORG X 0
X0 20. BCD
FUN 20
EN S : 9999 ERR
D : R 0 S : 9999
D : R 0
B15 B0
↓ ↓
S K 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1
ØX0＝1
B15 B0
↓ ↓
D R0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
6-37
FUN 21 D P BCD TO BIN CONVERSION FUN 21 D P

→BIN (Converts BCD data of the device specified at S into BIN and stores the result in D) →BIN
Operand
S : The register to be converted

D : The register to store the converted data
(BIN code)
The S, D may combine with V, Z, P0~P9 to
Range WX WY WM WS TMR CTR HR IR OR HR HSCR RTCR SR ROR DR

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● The decimal (BCD) data must be converted to binary (BIN) data first in order for PLC to accept the data
which is originally in decimal unit (BCD code) inputted from external device such as digital switch because
the BCD data can not be accepted by PLC for its operations.
● Converts BCD data of the device specified at S into BIN and writes the result in D when the operation
control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the data in S is not in BCD, then the error flag
FO0 is set to 1 and the old data of D are retained.
● Constant is converted to BIN automatically when store in program and can not be used as a source
operand of this function.
Example 16-bit BCD to BIN conversion
ORG
21P. BIN
ORG X 0
X0
EN S : WX 0 ERR FUN 21P
D : R 1 S : WX 0
D : R 1
X15 X0
↓ 1 2 3 4 ↓
S WX0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
ØX0＝
B15 B0
↓ ↓
D R1 0 0 0 0 0 1 0 0 1 1 1 1 0 0 1 0
6-38
Chapter 7 Advanced Function Instructions
 Flow control instructions1 (FUN22).................................................. ...........7-1
 Arithmetical operation instructions (FUN23～32) ................................... . . . . 7 - 2 ~ 7 - 9
 Logical operation instructions (FUN35～36)

………………….…….
..
.7-10 ~ 7-13
 Comparison instruction (FUN37) ……………………………………….

.7-14
 Data movement instructions1 (FUN40～50) ………….

…………….
..
7-15 ~ 7-25
 Shifting／Rotating instructions (FUN51～54)………………………….

7-26 ~ 7-29
 Code conversion instructions (FUN55～64)

…………………...…….7-30 ~ 7-46
 Flow control instructions2 (FUN65～71)

……………………...….7-47 ~ 7-54
 I／O instructions (FUN74～86)

……………………….... 7-55 ~ 7-72
 Cumulative timer instructions (FUN87～89)

……………………...….7-73 ~ 7-74
 Watchdog timer instructions (FUN90～91)

……………………….... 7-75 ~ 7-76
 High speed counting／timing (FUN92～93)

……………………….... 7-77 ~ 7-78
 Report printing instructions (FUN94) ……………………………….

7-79 ~ 7-80
 Slow up／Slow down instructions (FUN95) ………………….

.………….
..
7-81 ~ 7-82
 Table instructions (FUN100～114) …………….

……….
7-84 ~ 7-101
 Matrix instructions (FUN120～130)

……………...…….7-103 ~ 7-113
 NC positioning instructions (FUN140～143).............................7-114 ~ 7-119
 Enable／Disable instructions (FUN145～146)

…………..……….7-120 ~ 7-121
 Communication instructions (FUN150～151)

……………..…….7-122 ~ 7-123
 Data movement instructions2 (FUN160) ……….

.…….
.……….
….7-124 ~ 7-125
 Floating Point Number operation instructions(FUN200～213).........7-126 ~ 7-140

Advanced Function Instruction
FUN22 P BREAK FROM FOR AND NEXT LOOP FUN22 P

BREAK （BREAK） BREAK
● When execution control〝EN〞=1 or〝EN↑〞（ P instruction）changes from 0→1，it will terminate the FOR
and NEXT program loop。
● The program within the FOR and NEXT loop will be executed N times (N is assigned by FOR instruction)
successively，but if it is necessary to terminate the execution loop less than N times，the BREAK instruction
is necessary to apply。
● The BREAK instruction must be located within the FOR and NEXT program loop。
EN RST V
70
FOR D10
17.CMP M200
EN Sa : D100 a=b
Sb : R0V a>b
a<b
M200
EN BREAK
15
EN (+1) V OVF
71
NEXT
08.MOV
EN S : V
D : D1000
Description：The loop count used to execute the FOR and NEXT program loop is assigned by register D10；the
program within the FOR and NEXT loop is designed to search the same data storing in D100 from the
register table starting at R0。If it finds，the searching loop will be terminated and then it goes to execute
the program after the NEXT instruction；If it doesn't find，the searching loop will be executed N times (N
is the content of D10) and then it goes to execute the program after the NEXT instruction。
M200 tells the status and D1000 is the pointer of searching。
7-1
FUN 23 P FUN 23 P
48-BIT DIVISION
DIV48 DIV48
Sa：Starting register of dividend

Sb：Starting register of divisor
D : Starting register for storing the division
result (quotient)
Sa，Sb，can combine V, Z, P0~P9 for index
addressing.
Range HR OR SR ROR DR XR
R0 R3904 R3968 R5000 D0 V、Z
Ope- ∣ ∣ ∣ ∣ ∣
rand R3839 R3967 R4167 R8071 D4095 P0~P9
Sa ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○
D ○ ○ ○* ○* ○ ○
z When operation control “EN”=1 or “EN↑” ( P instruction) changes from 0→1, will perform the 48 bits division
operation. Dividend and divisor are each formed by three consecutive registers starting by Sa and Sb
respectively. If the result is zero, ‘D=0’ output will be set to 1. If divisor is zero then the ‘ERR’ will be set to 1
and the resultant register will keep unchanged.
z All operands involved in this function are all 48 bits, so Sa, Sb and D are all comprised by 3 consecutive
registers.
Example: 48-bit division
In this example dividend formed by register R2, R1, R0 will be divided by divisor formed by register R5, R4, R3. The
quotient will store in R8, R7, and R6.
X0 23P.DIV48
EN Sa : R 0 D=0
Sb : R 3
U/S D : R 6 ERR
R2 R1 R0
Sa
2147483647
R5 R4 R3
÷ Sb
1234567
R8 R7 R6
1739
Quotient
7-2
FUN 24 D P SUM FUN 24 D P

SUM (Summation of block data) SUM
S : Starting number of source register

N : Number of registers to be summed
(successive N data units starting from S)
D : The register which stored the result (summation)
S, N, D, can associate with V, Z, P0~P9 index register to
serve the indirect addressing application.

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 1 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 511 P0~P9
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control “EN”=1 or “EN↑” ( P instruction) changes from 0→1, it puts the successive N units of
16bit or 32 bit ( D instruction) registers for addition calculation to get the summation, and stores the result into
the register which is designated by D.
z When the value of N is 0 or greater than 511, the operation will not be performed.
z Communication port1 or port2 can be used to serve as a general purpose ASCII communication interface. If
the data error detecting method is Check-Sum, this instruction can be used to generate the sum value for
sending data or ot use this instruction to check if the received data is error or not.
〈Example 1〉When M1 changes from OFF→ON, following instruction will calculates the summation for 16-bit data.
M1 24P.SUM
z The left illustrates that 6 16-bit registers starting from R0
EN S : R0 is calculated for summation, and the result is stored into
N : 6 the R100 register.
D : R100
R0=0030H
R1=0031H
R2=0032H
Î R100=012FH
R3=0033H
R4=0034H
R5=0035H
〈Example 2〉When M1 is ON, it calculates the summation for 32-bit data.
M1 24D.SUM
z The left illustrates that three 32-bit registers starting
EN S : R0 from DR0, is calculated for their summation, and the
N : 3 result is stored into the DR100 register.
D : R100
R1，R0=00310030H
R3，R2=00330032H Î R101，R100=00A5009BH
R5，R4=00410039H
7-3
FUN 25 D P MEAN FUN 25 D P

MEAN (Average of the block data) MEAN
S : Source register number

N : Number of registers to be averaged
(N units of successive registers starting from S）
D : Register number for storing result (mean value)
The S, N, D may combine with V, Z, P0~P9 to
serve indirect address application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, add the N successive 16-bit or 32-bit
( D instruction) numerical values starting from S, and then divided by N. Store this mean value (rounding off
numbers after the decimal point) in the register specified by D.
z While the N value is derived from the content of the register, if the N value is not between 2 and 256, then the
N range error "ERR" will be set to 1, and do not execute the operation.
z At left, the example program gets the mean value of the

25P.MEAN
3 successive 16-bit registers starting from R0, and stores
X0
the results into the 16-bit register R10
EN S : R 0 ERR
N : 3
D : R 10
R0 123
S
R1 9
(N＝3)
R2 788 123＋9＋788
3
ØX0＝ ＝306 （Rouding off the remainder）
D R10 306
7-4
SQUARE ROOT
SQRT SQRT
S : Source register to be taken square root

D : Register for storing result
(square root value)
S, D may combine with V, Z, P0~P9 to serve
indirect address application

16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, take the square root (rounding off
numbers after the decimal point) of the data specified by the S field, and store the result into the register
specified by D.
z While the S value is derived from the content of the register, if the value is negative, then the S value error
flag "ERR" will be set to 1, and do not execute the operation.
X0 26DP.SQRT
EN S : ERR z The instruction at left calculates the square root of the
2147483647 constant 2147483647, and stores the result in R0.
D : R 0
S K 2147483647
ØX0＝
D R1 R0 46340
R1 R0
2147483647 = 46340.95
↑
rounding off
7-5
FUN 27 D P NEGATION FUN 27 D P

NEG (Take the negative value) NEG
D : Register to be negated
D may combine with V, Z, P0~P9 to serve indirect address
application
Range WY WM WS TMR CTR HR OR SR ROR DR XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 P0~P9
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, negate (ie. calculate 2's complement)
the value of the content of the register specified by D, and store it back in the original D register.
z If the value of the content of D is negative, then the negation operation will make it positive.
X0 27P z The instruction at left negates the value of the R0

EN NEG R 0 register, and stores it back to R0.
D R0 12345 )3039H
ØX0＝
D R0 −12345 )CFC7H
7 -6
FUN 28 D P ABSOLUTE FUN 28 D P

ABS (Take the absolute value) ABS
D : Register to be taken absolute value

application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, calculate the absolute value of the
content of the register specified by D, and write it back into the original D register.
X0 28DP z The instruction at left calculates the absolute value of

EN ABS R 0 the R0 register, and stores it back in R0.
D R1 R0 −12345 )CFC7H
ØX0＝
D R1 R0 12345 )3039H
7 -7
SIGN EXTENSION
EXT EXT
D : Register to be taken sign extension

application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, this instruction will sign extent the 16
bit numerical value specified by D to 32-bit value and store it into the 32-bit register comprised by the two
successive words, D + 1 and D. (Both values are the same, only it was originally formated as a 16 bit
numerical value, and was then extended to be formated as a 32 bit numerical value.)
z This instruction extent the numerical value of a 16-bit register into an equivalent numerical value in a 32-bit
register (for example 33FFH converts to 000033FFH), Its main function is for numerical operations
(+,-,*,/,CMP......) which can take the 16 bit or 32 bit numerical values as operand. Before operation all the
operand should be adjusted to the same length for proper operation.
z The instruction at left takes a 16 bit numerical value R0,

X0 29P and extends it to an equivalent value in 32 bits, then
EN EXT R 0 stores it into a 32 bit register (DR0=R1R0) comprised R0
and R1
R1 B15 R0 B0
Ignore the value of R1 before
D R1 R0 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 －12345
extension
ØX0＝
B31 R1 B16 B15 R0 B0
D R1 R0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 －12345
Fill B15 value into B31-B16,(if B15 is 0, then B31-B16 are all 0)
Before extension（16 bits） R0= CFC7H=−12345

The two numerical values are actually the same
After extension（32 bits）R1R0=FFFFCFC7H=−12345
7 -8
FUN 30 GENERAL PURPOSE PID OPERATION FUN 30

PID (Brief description) PID
Ts : PID Operation time interval
SR : Starting register of process control

parameter table comprised by 8 consecutive
registers.
OR : PID output register
PR : Starting register of the process parameter

table comprised by 7 consecutive registers.
WR : Starting register of working variable for PID

Range HR ROR DR K internal operation. It requires 7 registers and
R0 R5000 D0
can’t be re-used in other part of the ladder
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095 program.
Ts ○ ○ ○ 1～3000
SR ○ ○* ○
OR ○ ○* ○
PR ○ ○* ○
WR ○ ○* ○
z PID function according to the current value of process variable (PV) derived from the external analog signal
and the setting value (SP) of process performs the calculation, which base on the PID formula. The result of
calculation is the control output for the controlled process, which can feed directly to the AO module or other
output interface or leaved for further process. The usage of PID control for process if properly can achieve a
fast and smooth result of PV tracking toward SP change or immune to the disturbance of process.
z The PID formula in digital form:
n
Mn = [(D4005/Pb)×En]+ ∑ [(D4005/Pb)×Ti×Ts×En] − [(D4005/Pb)×Td×(PVn−PVn-1)/Ts] + Bias
0
Mn : Control output at time ”n”

Pb : Proportional band ( range : 2~5000, unit 0.1%. Kc (gain) =1000/ Pb )
Ti : Intergal time constant ( range : 0~9999 corresponds to 0.00~99.99 Repeats/Minute )
Td : Differential time constant ( range : 0~9999 corresponds to 0.00~99.99 Minutes )
PVn : Process value at time ”n”
PV n-1 : Process value at time ”n”
En :Error at time ”n” =set value ( SP) − process value at time ”n” (PVn)
Ts : Interval time of PID calculation ( range: 1~3000, unit : 0.01 S )
Bias : Control output offset ( range: 0~16380 )
z For detail description of this function, please refer chapter 20.
7 -9
FUN31 P CRC16 CALCULATION FUN31 P

CRC16 （CRC16） CRC16
MD ：0, Lower byte of registers to be calculated the

CRC16
：1, Reserved
S：Starting address of CRC16 calculation
N：Length of CRC16 calculation (In Byte)
D：The destination register to store the calculation of
Range HR ROR DR K CRC16,
R0 R5000 D0 Register D stores the Upper Byte of CRC16
Ope- ∣ ∣ ∣ Register D＋1 stores the Lower Byte of CRC16
rand R3839 R8071 D4095
MD 0~1 S, N, D may associate with V、Z、P0~P9 index register to
S ○ ○ ○ serve the indirect addressing application
N ○ ○ ○ 1~256
D ○ ○* ○
● When execution control "EN"=1 or "EN↑"（ P instruction）changes from 0→1, it will start the CRC16
calculation from the lower byte of S and by the length of N, the result of calculation will be stored into register
D and D+1.
● The output indication "D=0" will be ON if the value of calculation is 0.
● It will not execute the calculation and the output indication "ERR" will be ON if the length is invalid.
● When communicating with the intelligent peripheral in binary data fromat, the CRC16 error detection is used
very often; the well known Modbus RTU communication protocol uses this method for error detection of
message frame.
● CRC16 is the check value of a Cyclical Redundancy Check calculation performed on the message contents.
● Perform the CRC16 calculation on the received message data and error check value, the result of the
calculation value must be 0, it means no error within this message frame.
M0 08P.MOV Description：When M0 changes from 0→1, it will execute the

EN S : D0 CRC16 calculation starting from lower byte of R0, the length is
D : V assigned by D0, and then stores the CRC value into register
31P.CRC16 R0+V and R0+V+1.
EN MD: 0 D=0 It is supposed D0=10, the registers R10 and R11 will store the
S : R0
CRC16 value.
N : D0 ERR
D : R0V
S D
High Byte Low Byte High Byte Low Byte
R0 Don’t care Byte-0 R10 00 CRC-Hi
R1 Don’t care Byte-1 R11 00 CRC-Lo
R2 Don’t care Byte-2
7 -1 0
FUN32 CONVERTING THE RAW VALUE OF 4～20MA ANALOG INPUT FUN32

ADCNV （ADCNV） ADCNV
Ladder symbol Pl：0, the polarity setting of analog input module is at unipolar
32.ADCNV position
Operation Control EN Pl :
：1, the polarity setting of analog input module is at bipolar
S : position
14/12 - Bit Selection F/T
N : S：Starting address of source registers
D : N：Quantity of conversion (In Word)
D：Starting address of destination registers
Range HR IR ROR DR K S, N, D may associate with V、Z、P0~P9 index register to serve

R0 R3840 R5000 D0 the indirect addressing application.
Ope- ∣ ∣ ∣ ∣
rand R3839 R3903 R8071 D4095
Pl 0~1
S ○ ○ ○ ○
N ○ ○ ○ 1~64
D ○ ○* ○
● When the analog input is 4～20mA, the analog input module is one of the solution to get this kind of signal,
but the input span of the analog input module is 0～20mA (Setting at 10V、Unipolar), however there will exist
the offset of the raw reading value; this instruction is applied to eliminate the offset and convert the raw
reading value into the range of 0～4095(12-bit) or 0～16383(14-bit), it is more convenient for following
operation.
● When execution control "EN"=1, it will execute the conversion starting from S, length by N, and then store
the results into the D registers.
● This instruction will not act if invalid length of N.
● When the input〝F/T〞=0, it assigns the 12-bit analog input module; while〝F/T〞=1, it assigns the 14-bit
analog input module.
Example：
M0 32.ADSNV
EN P1 : 0
S : R3840
F/T N : 6
D : R500
Description：When M0 is ON, it will perfom 6 points of conversion starting from R3840, where the offset of 4～
20mA raw reading value will be eliminated, and the corresponding value 0～4095 will be stored into
R500～R505.
S D
R3840 －1229 R500 0 (4 mA)

R3841 409 R501 2047 (12 mA)
R3842 2047 R502 4095 (20 mA)
R3843 －2048 Ö R503 0 (0 mA)
R3844 －2048 R504 0 (0 mA)
R3845 －2048 R505 0 (0 mA)
7 -11
EXCLUSIVE OR
XOR XOR
Sa : Source data a for exclusive or operation
Sb :Source data b for exclusive or operation
D : Register storing XOR results
Sa, Sb, D may combine with V, Z, P0~P9 to


WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number P0~P9
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, will perform the logical
XOR (exclusive or) operation of data Sa and Sb. The operation of this function is to compare the
corresponding bits of Sa and Sb (B0~B15 or B0~B31), and if bits at the same position have different status,
then set the corresponding bit within D as 1, otherwise as 0.
z After the operation, if all the bits in D are all 0, then set the 0 flag "D = 0" to 1.
35P.XOR z The instruction at left makes a logical XOR operation

X0
D=0
using the R0 and R1 registers, and stores the result
EN Sa : R 0
in R2.
Sb : R 1
D : R 2
Sa R0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1
Sb R1 1 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0
ØX0＝
D R2 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1
7-12
EXCLUSIVE NOR
XNR XNR
Ladder symbol
Sa : Data a for XNR operation
36DP.XNR
Operation control EN Sa : D=0 Result as 0 Sb : Data b for XNR operation
Sb : D : Register storing XNR results
D : Sa, Sb, D may combine with V, Z, P0~P9 to serve


16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand ± number
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
● When operation control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, will perform the logical
XNR (inclusive or) operation of data Sa and Sb. The operation of this function is to compare the
corresponding bits of Sa and Sb (B0~B15 or B1~B31), and if the bit has the same value, then set the
corresponding bit within D as 1. If not then set it to 0.
● After the operation, if the bits in D are all 0, then set the 0 flag "D=0" to 1.
36P.XNR z The instruction at left makes a logical XNR operation

X0
D=0
of the R0 and R1 registers, and the results are stored
EN Sa : R 0
in the R2 register.
Sb : R 1
D : R 2
Sa R0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1
Sb R1 1 1 1 0 1 1 1 0 1 0 1 0 0 1 1 0
ØX0＝
D R2 1 0 1 0 1 0 1 0 0 0 1 1 0 1 0 0
7-13
ZONE COMPARE
ZNCMP ZNCMP
S : Register for zone comparison
SU : The upper limit value
SL : The lower limit value
S, SU, SL may combine with V, Z,

P0~P9 to serve indirect address
application

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
SU ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
SL ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, compares S with upper
limit SU and lower limit SL. If S is between the upper limit and the lower limit (SL≦S≦SU), then set the
inside zone flag "INZ" to 1. If the value of S is greater than the upper limit SU, then set the higher than
upper limit flag "S>U" to 1. If the value of S is smaller then the lower limit SL, then set the lower than lower
limit flag "S<L" as 1.
z The upper limit SU should be greater than the lower limit SL. If SU<SL, then the limit value error flag "ERR"
will set to 1, and this instruction will not carry out.
37P.ZNCMP
z The instruction at left compares the value of R0 with the
X0 Y0
S : R 0 INZ
upper and lower limit zones formed by R1 and R2. If the
EN
values of R0~R2 are as shown in the diagram at bottom
SU : R 1
S>U left, then the result can then be obtained as at the right
SL : R 2
of this diagram.
S<L
z If want to get the status of out side the zone, then OUT
ERR
NOT Y0 may be used, or an OR operation between the
two outputs S>U and S<L may be carried out, and move
the result to Y0.
S R0 200
Y0
SU R1 300 （Upper limit value） X0＝
1
SL
R2 100
（Lower limit value） )
Results of execution
Before-execution
7-14
BIT READ
BITRD BITRD
S : Source data to be read
N : The bit number of the S data to be read out.
S, N may combine with V, Z, P0~P9 to serve


16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～31 ○
z When read control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, take the Nth bit of the S data
out , and put it to the output bit "OTB".
z When read control "EN" = 0 or "EN↑" ( P instruction) is not change from 0 to 1, The output “OTB” can be
selected to keep at the last state( if M1919=0 ) or set to zero ( if M1919=1 ).
z When the operand is 16 bit, the effective range for N is 0~15. For 32 bit operand ( D instruction) it is 0~31.
N beyond this range will set the N value error flag "ERR" to 1, and do not carry out this instruction.
40P.BITRD
z The instruction at left reads the 7th bit (X7) status from
X0 Y0
WX0 (X0~X15) and output to Y0. The results are as
EN S : WX 0 OTB
follows:
N : 7 ERR
X15 X7 X0
S WX0 1 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1
N＝7────────── ØX0＝
Y0 1
7-15
BIT WRITE
BITWR BITWR
D : Register for bit write
N : The bit number of the D register to be

written.
D, N may combine with V, Z , P0~P9 to serve


WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 0 0 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ or ∣
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 15 31 P0~P9
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When write control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, will write the write bit (INB) into
the Nth bit of register D.
z When the operand is 16 bit, the effective range of N is 0~15. For 32 bit ( D instruction) operand it is 0~31. N
beyond this range, will set the N value error flag "ERR" to 1, and do not carry out this instruction.
41P.BITWR
X0
z The instruction at left writes the status of the write bit
EN D : R 0 ERR
INB into B3 of R0. Assuming
X1
INB N : 3 X1 = 1, the result will be as follows:
X1 1
N＝3───────────── ØX0＝
D R0 1
B15 B3 B0
Bits other than B3 remain unchanged
7-16
BIT MOVE
BITMV BITMV
S : Source data to be moved
Ns : Assign Ns bit within S as source bit
D : Destination register to be moved

Nd : Assign Nd bit within D as target bit
S, Ns, D, Nd may combine with V, Z, P0~P9 to


16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +/- number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ns ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～31 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Nd ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～31 ○
z When move control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, will move the bit status specified
by Ns within S into the bit specified by Nd within D.
z When the operand is 16 bit, the effective range of N is 0~15. For 32 bit ( D instruction) operand the effective
range is 0~31. N beyond this range will set the N value error flag "ERR" to 1, and do not carry out this
instruction.
X0 42P.BITMV
z The instruction at left moves the status of B11 (X11)
EN S : WX 0 ERR within S into the B7 position within D. Except bit B7,
Ns : 11 other bits within D does not change.
D : R 0
Nd : 7
X15 X11 X0
S WX0 1
Ns＝11─────
ØX0＝
Nd＝7 ────────
D R0 1
B15 B7 B0
7-17
NIBBLE MOVE
NBMV NBMV

Ns: Assign Ns nibble within S as source nibble
Nd: Assign Nd nibble within D as target nibble

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ns ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～7 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Nd ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～7 ○
z When move control "EN" = 1 or "EN↑" ( P instruction)has a transition from 0 to 1, will move the Ns’th nibble
from within S to the nibble specified by Nd within D. (A nibble is comprised by 4 bits. Starting from the lowest
bit of the register, B0, each successive 4 bits form a nibble, so B0~B3 form nibble 0, B4~B7 form nibble 1,
etc...)
z When the operand is 16 bit, the effective range of Ns or Nd is 0~3. For 32 bit ( D instruction) operand the
range is 0~7. Beyond this range, will set the N value error flag "ERR" to 1 , and do not carry out this
instruction.
X0 43P.NBMV z The instruction at left moves the third nibble NB2

EN S : R 0 ERR (B8~B11) within S to the first nibble NB1 (B4~B7) within
Ns : 2 D. Other nibbles within D remain unchanged.
D : R 1
Nd : 1
B15 B0
S R0 1 1 0 1
NB3 NB2 NB1 NB0
Ns＝2 ───────
ØX0＝
Nd＝1 ─────────
NB3 NB2 NB1 NB0
D R1 1 1 0 1
B15 B0
7-18
BYTE MOVE
BYMV BYMV
Ns : Assign Ns byte within S as source byte
Nd : Assign Nd byte within D as target byte


16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ns ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～3 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Nd ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～3 ○
z When move control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, move Nsth byte within S
to Ndth byte position within D. (A byte is comprised of 8 bits. Starting from the lowest bit of the register, B0,
each successive eight bits form a byte, so B0~B7 form byte 0, B8~B15 form byte 1, etc...)
z When the operand is 16 bit, the effective range of Ns or Nd is 0~1. For 32 bit ( D instruction) operand, the
range is 0~3. Beyond this range, will set the N value error flag "ERR" to 1, and do not carry out this
instruction.
X0 44DP.BYMV z The instruction at left moves the third byte (B16~B23)

EN S : R 0 ERR within S (32 bit register composed of R1R0), to the first
Ns : 2 byte within D (32 bit register composed of R3R2). Other
bytes within D remain unchanged.
D : R 2
Nd : 1
B15 B0
S R1 R0 1 0 1 1 1 0 1 1
Byte3 Byte2 Byte1 Byte0
Ns＝2──────────────
ØX0＝
Nd＝1────────────────────
Byte3 Byte2 Byte1 Byte0
D R3 R2 1 0 1 1 1 0 1 1
B31 B0
7-19
EXCHANGE
XCHG XCHG
Ladder symbol Da : Register a to be exchanged
45DP.XCHG Db : Register b to be exchanged

Exchange control EN Da : Da, Db may combine with V, Z, P0~P9 to serve indirect
address application
Db :

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Da ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Db ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When exchange control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will exchanges the
contents of register Da and register Db in 16 bits or 32 bits ( D instruction) format.
X0 45P.XCHG
z The instruction at left exchanges the contents of the
EN Da : R 0 16-bit R0 and R1 registers.
Db : R 1
B15 B0
Da R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Db R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ØX0＝
B15 B0
Da R0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Db R1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7-20
FUN 46 P FUN 46 P
BYTE SWAP
SWAP SWAP
D : Register for byte data swap

application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When swap control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, swap the data of the low
byte, Byte 0 (B0~B7), and the high byte, Byte 1 (B8~B15), in the 16 bit register specified by D.
B15 B8 B7 B0
Byte 1（high） Byte 0（low）
X0 46P z The instruction at left swaps the data of the low byte
EN SWAP R 0 (B0~B7) and the high byte (B8~B15) in R0. The results
are as follows:
Byte1 Byte0

D R0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0
B15 B8 B7 B0
ØX0＝
B15 B0
D R0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1
7-21
FUN 47 P FUN 47 P
NIBBLE UNITE
UNIT UNIT
S : Starting source register to be united
N : Number of nibbles to be united
D : Registers storing united data
S, N, D may combine with V, Z, P0~P9 to serve


Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When unite control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, take out the lowest
nibbles NB0, of N successive registers starting from S, and fill them into NB0, NB1, .....NBn-1 of D in
ascending order. Nibbles not yet filled in D (when N is odd) are filled with 0. (A nibble is comprised by 4 bits.
Starting from the lowest bit in the register, B0, each successive four bits form a nibble, so B0~B3 form nibble
0, B4~B7 form nibble 1, etc...).
z This instruction only provides WORD (16 bit) operand. Because of this, there are usually only 4 nibbles can
be involved. Therefore the effective range of N is 1~4. Beyond this range, will set the N value error flag
"ERR" to 1, and do not carry out this instruction.
z The instruction at left takes out NB0 from 3 registers, R0,

X0 47P.UNIT
EN S : R 0 ERR R1 and R2, and fills them into NB0~NB2 within WY0
N : 3 register.
D : WY 0
N＝3
NB3 NB2 NB1 NB0

D W Y 0 0000 0100 0010 0001
Y15 Y0
Set the not united NB as 0
B15 B12 B11 B8 B7 B4 B3 B0
S R0 0001
N＝3 S＋1 R1 0010
S＋2 R2 0100
Ö
NB3 NB2 NB1 NB0 X0＝
7-22
FUN 48 P FUN 48 P
NIBBLE DISTRIBUTE
DIST DIST
S : Source data to be distributed

N : Number of nibbles to be distributed
D : Starting register storing distribution data
S, N, D may combine with V, Z, P0~P9 to

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16-bit V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 1~4 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When distribution control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will take N
successive nibbles starting from the lowest nibble NB0 within S, and distribute them in ascending order into
the 0 nibbles of N registers starting from D. The nibbles other than NB0 in each of the registers within D are
all set to zero. (A nibble is comprised by 4 bits. Starting from the lowest bit in a register, B0, each successive
4 bits form a nibble, so B0~B3 form nibble 0, B4~B7 form nibble 1, etc...)
z This instruction only provides WORD (16 bit) operand. Therefore there are usually only 4 nibbles can be
involved, so the effective value of N is 1~4. Beyond this range, will set the N value error flag "ERR" to 1, and
do not carry out this instruction.
X0 48P.DIST z The instruction at left writes NB0~NB2 from the WX0

EN S : WY 0 ERR
register into the NB0 of the 3 consecutive registers
N : 3
R0~R2.
D : R 0
N=3 NB3 NB2 NB1 NB0

X15 X11 X0 B15 B0
S WX0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 D R0 0 0 0 0 0000 0000 0001
NB3 NB2 NB1 NB0 D+1 R1 0 0 0 0 0000 0000 0010
D+2 R2 0 0 0 0 0000 0000 0100
Ö NB1～NB3 are all set a "0 "
X0＝
7-23
FUN49 P FUN49 P
BYTE UNITE
BUNIT BUNIT
S ：Starting address of source register to be united

N ：Number of bytes to be united
D ：Registers to store the united data
S, N, D may associate with V、Z、P0~P9 index register to
serve the indirect addressing application
Range HR ROR DR K
R0 R5000 D0
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095
S ○ ○ ○
N ○ ○ ○ 1~256
D ○ ○* ○
● When execution control "EN"=1 or "EN↑"（ P instruction）changes from 0→1, it will perform the byte
combination starting from S, length by N, and then store the results into D registers.
● This instruction will not act if invalid range of length.
● When communicating with intelligent peripheral in binary data format, this instruction may be applied to do
byte combination for following word data processing.
Example：
M2 49P.BUNIT
EN S : R 1500
N : R 999
D : R 2500
Description：When M2 changes from 0→1, it will perform the byte combination starting from R1500, the length is
assigned by R999, and then store the results into registers starting from R2500.
It is supposed R999=10, the results of combination will store into R2500～R2504.
S D
R1500 Don’t care Byte-0 R2500 Byte-0 Byte-1
7-24
FUN50 P FUN50 P
BYTE DISTRIBUTE
BDIST BDIST
S ：Starting address of source register to be distributed

N ：Number of bytes to be distributed
D ：Registers to store the distributed data
S, N, D may associate with V、Z、P0~P9 index register to serve
the indirect addressing application.
Range HR ROR DR K
R0 R5000 D0
Ope- ∣ ∣ ∣
rand R3839 R8071 D4095
S ○ ○ ○
N ○ ○ ○ 1~256
D ○ ○* ○
● When execution control "EN" =1 or "EN↑"（ P instruction）changes from 0→1, it will perform the byte
distribution starting from S, length by N, and then store the results into D registers.
● This instruction will not act if invalid range of length.
● When communicating with intelligent peripheral in binary data format, this instruction may be applied to do
byte distribution for data transmission。
Example：
M2 50P.BDIST
EN S : R 1000
N : R 999
D : R 1500
Description：When M2 changes from 0→1, it will perform the byte distribution starting from R1000, the length is
assigned by R999, and then store the results into registers starting from R1500.
It is supposed R999=9, the results of distribution will store into R1500～R1508.
S D
R1000 Byte-0 Byte-1 R1500 00 Byte-0
R1004 Byte-8 Don’t care R1504 00 Byte-4
R1505 00 Byte-5
R1506 00 Byte-6
R1507 00 Byte-7
R1508 00 Byte-8
7-25
SHIFT LEFT
SHFL SHFL
D : Register to be shifted
N : Number of bits to be shifted
N, D may combine with V, Z, P0~P9 to serve


Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ or ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When shift control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will shift the data of the D
register towards the left by N successive bits (in ascending order). After the lowest bit B0 has been shifted
left, its position will be replaced by shift-in bit INB, while the status of shift-out bits B15 or B31 ( D instruction)
will appear at shift-out bit "OTB".
z If the operand is 16 bit, the effective range of N is 1~16. For 32 bits ( D instruction) operand, it is 1~32.
Beyond this range, will set the N value error flag "ERR" to 1, and do not carry out this instruction.
z The instruction at left shifts the data in register R0

51P.SHFL Y0
X0 towards the left by 4 successive bits. The results are
EN D :R 0 OTB shown below.
N : 4
INB ERR
Y0 B15 R0 B0 INB
← 0 0 1 1 0 0 1 0 1 1 1 1 0 0 0 0 ← 1
* △
ØX0＝
Y0 B15 R0 B0 INB
1 0 0 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1
* △ △ △ △ △
7-26
SHIFT RIGHT
SHFR SHFR
D : Register to be shifted
N : Number of bits to be shifted
D, N may combine with V, Z, P0~P9 to serve


Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ or ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When shift control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will shift the data of D
register towards the right by N successive bits (in descending order). After the highest bits, B15 or B31 ( D
instruction) have been shifted right, their positions will be replaced by the shift-in bit INB, while shift-out bit
B0 will appear at shift-out bit "OTB".
z The instruction at left shifts the data in R0 register
52P.SHFR
towards the right by 15 successive bits. The
X0 Y0
results are shown below.
EN D :R 0 OTB
N : 15
INB ERR
INB B15 R0 B0 Y0
0 → 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 →
△ *
ØX0＝
INB B15 R0 B0 Y0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
△ △ △ △ △ △ △ △ △ △ △ △ △ △ △ △ *
7-27
ROTATE LEFT
ROTL ROTL
D : Register to be rotated
N : Number of bits to be rotated
D, N may combine with V, Z , P0~P9 to serve


Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ or ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When rotate control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will rotate the data of D
register towards the left by N successive bits (in ascending order, ie. in a 16-bit instruction, B0→B1, B1→
B2, .... , B14→B15, B15→B0. In a 32-bit instruction, B0→B1, B1→B2, .... , B30→B31, B31→B0). At the
same time, the status of the rotated out bits B15 or B31 ( D instruction) will appear at rotate-out bit "OTB".
z The instruction at left rotates data from the R0

53P.ROTL Y0 register towards the left 9 successive bits. The
X0
EN D :R 0 OTB results are shown below.
N : 9
ERR
R0 B0
1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0
*
Y0
ØX0＝
B15 R0 B0
0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1
*
1 Y0
*
7-28
ROTATE RIGHT
ROTR ROTR
D : Register to be rotated
N : Number of bits to be rotated
D, N may combine with V, Z, P0~P9 to serve


Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ or ∣
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z When rotate control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will rotate the bit data of
D register towards the right by N successive bits (in descending order, ie. in a 16-bit instruction, B15→B14,
B14→B13, .... , B1→B0, B0→B15. In a 32-bit instruction, B31→B30, B30→B29, .... , B1→B0, B0→B31). At
the same time, the status of the rotated out B0 bits will appear at the rotate-out bit "OTB".
z The instruction at left rotates data from R0 register

54P.ROTR Y0 towards the right 8 successive bits. The results are
X0
EN D :R 0 OTB shown below.
N : 8
ERR
B15 R0 B0
1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0
*
Y0
ØX0＝
B15 R0 B0
1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0
*
Y0 1
*
7-29
FUN55 D P FUN55 D P
BINARY - CODE TO GRAY - CODE CONVERSION
B→G B→G
Ladder symbol S ：Starting of source

55DP.B G
D ：Starting address of destination
Operation control EN S :
S，D operand can combine V、Z、P0~P9 for index
D : addressing

0~FFFFH
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
0~FFFFFFFFH
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○* ○ ○
● When operation control "EN"=1 or "EN↑"( P instruction) changes from 0→1, it will perform the code conversion; where S
is the source (Binary code), and D is the destination (Gray code) for storing the result.
● The conversion method shown as below
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR
1 0 0 1 1 0 0 0 1 1 1 0 1 1 0 1
1 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1
Example 1: When M0 changes from 0→1, it will perform the 16-bit code conversion
˙ Converting the 16-bit Binary-code in R0 into Gray-code, and

M0 55P.B G then storing the result into R100.
EN S : R0
D : R100
R0＝ 1001010101010011B Î R100＝ 1101111111111010B
7-30
FUN55 D P FUN55 D P
BINARY - CODE TO GRAY - CODE CONVERSION
B→G B→G
Example 2: When M0 =1, it will be perform the 32-bit code conversion
55DP.B G ˙ Converting the 32-bit Binary-code in DR0 into Gray-code,

M0
EN S : R0 and then storing the result into DR100.
D : R100
DR0＝ 00110111001001000010111100010100B Î DR100＝ 00101100101101100011100010011110B
7-31
FUN56 D P FUN56 D P
GRAY - CODE TO BINARY - CODE CONVERSION
G→B G→B
S ：Starting of source
D ：Starting address of destination
S，D operand can combine V、Z、P0~P9 for index addressing

0~FFFFH
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand 0~FFFFFFFFH
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○* ○ ○
● When operation control "EN"=1 or "EN↑"( P instruction) changes from 0→1, it will perform the code conversion; where S
is the source (Gray code), and D is the destination (Binary code) for storing the result.
● The conversion method shown as below :
Example 1: When M0 changes from 0→1, it will perform the 16-bit code conversion
M0 56P.G B
˙ Converting the 16-bit Gray-code in D0 into
EN S : D0
Binary-code, and then storing the result into D100.
D : D100
D0＝ 1001010101010011B Î D100＝ 1110011001100010B
7-32
FUN56 D P FUN56 D P
GRAY - CODE TO BINARY - CODE CONVERSION
G→B G→B
Example 2: When M0 =1, it will perform the 32-bit code conversion
56DP.G B ˙ Converting the 32-bit Gray-code in DD0 into

M0
EN S : D0
Binary-code, and then storing the result into
D100
DD100.
D :
DD0＝ 00110111001001000010111100010100B Î DD100＝ 00100101110001111100101000011000B
7-33
FUN 57 P FUN 57 P
DECODE
DECOD DECOD
Ladder symbol S : Source data register to be decoded

57P.DECOD (16 bits)
Decode control EN S : ERR Range error NS : Starting bits to be decoded within S
Ns : NL : Length of decoded value (1~8 bits)

D : Starting register storing decoded results
NL :
(2~256 points = 1~16 words)
D :
S, NS, NL, D may combine with V, Z, P0~P9
to serve indirect address application

Ope- 16-bit
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +/- number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
NS ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～15 ○
NL ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 1～8 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
NL
● This instruction, will set a single bit among the total of 2 discrete points (D) to 1 and the others bit are set to
0. The bit number to be set to 1 is specified by the value comprised by BNS～BNS+NL−1 of S（which is called
the decode value, BNS is the starting bit of the decode value, and BNS+NL−1 is the end value）,.
● When decode control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will take out the value
BNS～BNS+NL−1 from S. And with this value to locate the bit position and set D accordingly, and set all the
other bit to zero
● This instruction only provides 16 bit operand, which means S only has B0~B15. Therefore the effective range
of Ns is 0~15, and the NL length of the decode value is limited to 1~8 bits. Therefore the width of the decoded
1～8
result D is 2 points = 2~256 points = 1~16 words (if 16 points are not sufficient, 1 word is still occupied). If
the value of NS or NL is beyond the above range, will set the range-error flag "ERR" to 1, and do not carry out
this instruction.
● If the end bit value exceeds the B15 of S, then will extend toward B0 of S + 1. However if this occurs then
S+1 can’t exceed the range of specific type of operand (ie. If S is of D type register then S+1 can’t be D3072).
If violate this, then this instruction only takes out the bits from starting bit BNs to its highest limit as the decode
value.
X0 57P.DECOD z The instruction at left takes out the data of five

EN S : WX 0 ERR
successive bits from X3 to X7 within the WX0
Ns : 3
register and decodes it. The results are then stored
NL : 5
in the 32-bit register starting at R2.
D : R 2
X15 X7 X3 X0
S 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 0
Length of decode value NL=5,so bit value is formed by X7~X3 (equal 9)
ØX0＝
R3 R2
D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
B31 B9 B0
5
Because NL=5,the width of D is 2 = 32 point = 2 word. That is, D is formed by R3R2, and the decoded value is
01001=9, therefore B9 (the 10th point) within D is set to 1, and all other points are 0.
7-34
FUN 58 P FUN 58 P
ENCODE
ENCOD ENCOD
S : Starting register to be encoded

NS : Bit position within S as the encoding start
point
NL : Number of encoding discrete points (2~256)
D : Number of register storing encoding results
(1 word)
S, NS, NL, D may combine with V, Z, P0~P9 to

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
NS ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～15 ○
NL ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 2～256 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
● When encode control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will starting from the
points specified by Ns within S, take out towards the left (high position direction) NL number of successive bits
BNS～BNS+NL−1 (BNS is called the encoding start point, and its relative bit number is b0;BNS+NL−1 is called
the encoding end point, and its relative bit number is BNL-1). From left to right do higher priority (when H/L=1)
encoding or from right to left do lower priority (when H/L=0) encoding (i.e. seek the first bit with the value of 1,
and the relative bit number of this point will be stored into the low byte (B0~B7) of encoded resultant register
D, and the high byte of D will be filled with 0.
（bNL−1）（bH）（bL）（b0）← Relative bit number

BNS＋NL−1 BNS
↓ B15 ↓ B1 B0
← …Direction of extension… 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 S
High Total NL discrete points Low
High priority search direction Ø Low priority search direction
D 00000000 H or L
● As shown in the diagram above, for high priority encoding, the bit first to find is bH (with a value of 12), and for
low priority encoding, the bit first to find bL (with a value of 4). Among the NL discrete points there must be at
least one bit with value of 1. If all bits are 0, will not to carry out this instruction, and the all zero flag "D=0" will
set to 1.
● Because S is a 16-bit register, Ns can be 0~15, and is used to assign a point of B0~B15 within S as the
encoding start point (b0). The value of NL can be 2~256, and it is used to identify the encoding end point, i.e. it
assigns NL successive single points starting from the start point (b0) towards the left (high position direction)
as the encoding zone (i.e. b0～bNL−1). If the value of Ns or NL exceeds the above value, then do not carry out
this instruction, and set the range-error flag "ERR" as 1.
7-35
FUN 58 P FUN 58 P
ENCODE
ENCOD ENCOD
● If the encoding end point (bNL−1) beyond the B15 of S, then continue extending towards S+1, S+2, but it must
not exceed the range of specific type of operand. If it goes beyond this, then this instruction can only take the
discrete points between b0 and the highest limit into account for encoding.
z The instruction at left is a high priority encode example.

When X0 goes from 0 to 1, will take out toward left 36
X0 58P.ENCOD
successive bits starting from B9 (b0) specified by Ns
EN S : R 0 D=0
within S, and perform high priority encoding (because
Ns : 9
ERR
H/L = 1). That is, starting from b35 (encoding end point),
H/L NL : 36
D : WY 0
move right to find the first bit with the value of 1. The
resultant value of this example is b26, so the value of D
is 001AH=26, as shown in the diagram below.
S D
(b0)
B15 B9 B0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y15 Y0
X0＝
R1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WY0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0
R2 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0
Ö
B47 B44 ↑ B32 High byte always ＝26
（b35）（b26）（encode value）
fill with "0"
The first bit with the value of 1

for high priority encoding
7-36
FUN 59 P FUN 59 P
7-SEGMENT CONVERSION
→7SG →7SG
Ladder symbol
59P. 7SG S : Source data to be converted
Conversion control EN S : ERR N value error N : The nibble number within S for conversion
N : D : Register storing 7-segment result

D : S, N, D may combine with V, Z,P0~P9 to serve

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～3 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
● When conversion control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will convert N+1
number of nibbles (A nibble is comprised by 4 successive bits, so B0~B3 of S form nibble 0, B4~B7 form
nibble 1, etc...)within S to 7-segment code, and store the code into a low byte of D (High bytes does not
change). The 7 segment within D are put in sequence, with "a" segment placed at B6, "b" segment at
B5, .... ,"g" segment at B0. B7 is not used and is fixed as 0. For details please refer the "7-segment code
and display pattern table" shown in page 9-31.
● Because this instruction is limited to 16 bits, and S only has 4 nibbles (NB0~NB3), the effective range of N
is 0~3. Beyond this range, will set the N value flag error "ERR" to 1, and does not carry out this instruction.
● Care should be taken on total nibbles to be converted is N+1. N=0 means one digit to convert, N=1 means
two digits to convert etc…
● When using the FATEK 7-segment expansion module(FBs-7SG) and the FUN84 (7SEG) handy instruction
for mixing decoding and non-decoding application, FUN59 and FUN84 can be combined to simplify the
program design.(Please refer the example in chapter 16)
7-37
FUN 59 P FUN 59 P
→7SG →7SG
〈Example 1〉When M1 OFF→ON, convert hexadecimal to 7-Segment
M1 59P. 7SG ˙Figure left shown the conversion of first digit(nibble) of

EN S : R0 ERR R0 to 7-segment and store in low byte of R100, the
N : 0 high byte of R100 remain unchanged.
D : R100
Original R100＝0000H
R0＝0001H Î R100＝0030H（1）
〈Example 2〉When M1 ON, convert the hexadecimal to 7-Segment
M1 59. 7SG ˙Instruction at left will convert the first and the second
EN S : R0 ERR digit of R0 to 7-segment and store in R100.
N : 1 ˙The low byte of R100 stores first digit.
D : R100 ˙The high byte of R100 stores second digit.
R0＝0056H Î R100＝5B5FH（56）
〈Example 3〉When M1 ON, converting hexadecimal to 7-Segment
˙Instruction at left will convert the first, second and third

digit of R0 to 7-segment and store in R100 and R101.
M1 59. 7SG ˙The low byte of R100 stores first digit.
EN S : R0 ERR
˙The high byte of R100 stores second digit.
N : 2
˙The low byte of R101 stores third digit.
D : R100
˙The high byte of R10 remain unchanged.
Original R101=0000H
R0=0A48H Î R100=337FH（48）
R101=0077H（A）
〈Example 4〉When M1 ON, convert hexadecimal to 7-Segment
˙Instruction at left will convert 1~4 digit of R0 to

M1 59. 7SG
7-segment and store in R100 and R101.
EN S : R0 ERR
˙The low byte of R100 stores first digit.
N : 3
˙The high byte of R100 stores second digit.
D : R100
˙The low byte of R101 stores third digit.
th
˙The high byte of R10 stores 4 digit.
R0=2790H Î R100=7B7EH（90）
R101=6D72H（27）
7-38
FUN 59 P FUN 59 P
→7SG →7SG
Nibble data of S Low byte of D

7-segment Display
Hexadecimal Binary display format B7 B6 B5 B4 B3 B2 B1 B0 pattern
number number z a b c d e f g
0 0000 0 1 1 1 1 1 1 0
1 0001 0 0 1 1 0 0 0 0
2 0010 0 1 1 0 1 1 0 1
3 0011 0 1 1 1 1 0 0 1
B6
4 0100 a 0 0 1 1 0 0 1 1
B1 f b B5
5 0101 B0
g
0 1 0 1 1 0 1 1
B2 e c B4
6 0110 0 1 0 1 1 1 1 1
d
B7
B3 P
7 0111 0 1 1 1 0 0 1 0
8 1000 0 1 1 1 1 1 1 1
9 1001 0 1 1 1 1 0 1 1
A 1010 0 1 1 1 0 1 1 1
B 1011 0 0 0 1 1 1 1 1
C 1100 0 1 0 0 1 1 1 0
D 1101 0 0 1 1 1 1 0 1
E 1110 0 1 0 0 1 1 1 1
F 1111 0 1 0 0 0 1 1 1
7-segment display pattern table
7-39
FUN 60 P FUN 60 P
ASCII CONVERSION
→ASC →ASC
S : Alphanumerics to be converted into ASCII code
D : Starting register storing ASCII results
Range WY WM WS TMR CTR HR OR SR ROR DR Alphanumeric

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0
Ope- 1～12
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand alphanumeric
WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095
S ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● When conversion control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will convert
alphabets and numbers stored in S (S has a maximum of 12 alphanumeric character) into ASCII and store
it into registers starting from D. Each 2 alphanumeric characters occupy one 16-bit register.
● The application of this instruction, most often, stores alphanumeric information within a program, and waits
until certain conditions occur, then converts this alphanumeric information into ASCII and conveys it to
external display devices which can accept ASCII code.
z The instruction at left converts the 6 alphabets

-ABCDEF into ASCII then stores it into 3 successive
X0 60P. ASC registers starting from R0.
EN S : ABCDEF ERR
D : R0
S D
High Byte Low Byte
R0 42（B） 41（A）
Alphabet X0＝
R1 44（D） 43（C）
ABCDEF Ö R2 46（F） 45（E）
7-40
FUN 61 P FUN 61 P
HOUR:MINUTE:SECOND TO SECONDS CONVERSION
→SEC →SEC
Ladder symbol S : Starting calendar data register to be

61P. SEC converted
Conversion control EN S : D=0 Result as 0 D : Starting register storing results
D :

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 －117968399
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When conversion control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will convert the hour:
minute: second data of S~S+2 into an equivalent value in seconds and store it into the 32-bit register formed
by combining D and D+1. If the result = 0, then set the "D = 0" flag as 1.
z Among the FBs-PLC instructions, the hour: minute: second time related instructions (FUN61 and 62) use 3
words of register to store the time data, as shown in the diagram below. The first word is the second register,
the second word is the minute register, and finally the third word is the hour register, and in the 16 bits of
each register, only B14~B0 are used to represent the time value. While bit B15 is used to express whether
the time values are positive or negative. When B15 is 0, it represents a positive time value, and when B15
is 1 it represents a negative time value. The B14~B0 time value is represented in binary, and when the time
value is negative, B14~B0 is represented with the 2's complement. The number of seconds that results from
this operation is the result of summation of seconds from the three registers representing hours: minutes:
seconds.
B15 B14 B0 B15B0
S (sec) －32768 sec～32767 sec D the sec. value.
S＋1 (min) －32768 min～32767 min Ö D＋1
S＋2 (hr) －32768 hr～32767 hr B31 B30 B16
↑ ↑ B31 is used to represent the positive or
The B15 of each registers is used to represent the sign of each time value └ negative nature of the sec. value
z Besides FUN61 or 62 instruction which treat hour: minute: second registers as an integral data, other
instructions treat it as individual registers.
z The example program at below converts the hour: minute: second data formed by R20~R22 into their
equivalent value in seconds then stored in the 32-bit register formed by R50~R51. The results are shown
below.
R20 0E11H ＝3601 sec

X0 61P. SEC S R21 FD2FH ＝−721 min
EN S : R 20 D=0 R22 03F3H ＝1011 hr
D : R 50 ØX0＝
R50 EE45H
D ＝3599941 sec
R51 0036H
7-41
FUN 62 P FUN 62 P
SECOND→HOUR：MINUTE：SECOND
→HMS →HMS
S :Starting register of second to be converted
D :Starting register storing result of conversion

(hour : minute : second)

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 －117968399
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When conversion control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will convert the
second data from the S~S+1 32-bit register into the equivalent hour : minute : second time value and store it
in the three successive registers D~D+2. All the data in this instruction is represented in binary (if there is a
negative value it is represented using the 2's complement.)
B15 B0 B15 B0
S D (sec) －59 sec～59 sec
S＋1
Second Ö D＋1 (min) －59 min～59 min
B31 B16 D＋2 (hr) －32768 hr～32767 hr
↑ ↑
The bit B31 of the second The bits B15 of each register are used as
register is used as the sign the sign bit of the hour : minute : second
bit of the second value. value.
z As shown in the diagram above, after convert to hour : minute : second value, the minute : second value can
only be in the range of -59 to 59, and the hour number can be in the range of -32768 to 32767 hours.
Because of this, the maximum limit of D is -32768 hours, -59 minutes, -59 seconds to 32767 hours, 59
minutes, 59 seconds, the corresponding second value of S which is in the range of -117968399 to
117964799 seconds. If the S value exceeds this range, this instruction cannot be carried out, and will set the
over range flag "OVR" to 1. If S = 0 then result is 0 flag "D = 0" will be set to 1.
z The program in the diagram below is an example of this instruction. Please note that the content of the
registers are denoted by hexadecimal, and on the right is its equivalent value in decimal notation.
X0 62P. HMS R0 5D17H

6315287 sec
EN S : R 0 D=0 R1 0060H
D : R 10 OVR ØX0＝
R10 002FH 47 sec
R11 000EH 14 min
R12 06DAH 1754 hr
7-42
FUN 63 P FUN 63 P
CONVERSION OF ASCII CODE TO HEXADECIMAL VALUE
→HEX →HEX
Ladder symbol S : Starting source register.

63P. HEX N : Number of ASCII codes to be converted to
Conversion control EN S : ERR hexadecimal values.
N : D : The starting register that stores the result

(hexadecimal value).
D : S, N, D, can associate with V, Z, P0~P9 to do the
indirect addressing application.

16-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand +number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 1～511 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When conversion control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, it will convert the N
successive hexadecimal ASCII character(‘0’~’9’,’A’~’F’) convey by 16 bit registers (Low Byte is effective) into
hexadecimal value, and store the result into the register starting with D. Every 4 ASCII code is stored in one
register. The nibbles of register, which does not involve in the conversion of ASCII code will remain
unchanged.
z The conversion will not be performed when N is 0 or greater than 511.
z When there is ASCII error (neither 30H～39H nor 41H～46H), the output “ERR” is ON.
z The main purpose of this instruction is to convert the hexadecimal ASCII character (‘0’~’9’,’A’~’F’), which is
received by communication port1 or communication port2 from the external ASCII peripherals, to the
hexadecimal values that the CPU can process directly.
7-43
FUN 63 P FUN 63 P
CONVERSION OF ASCII CODE TO HEXADECIMAL VALUE
→HEX →HEX
〈Example 1〉When M1 from OFF→ON, ASCII code converted to hexadecimal value.

M1 63P. HEX
˙ Converts the ASCII code of R0 into hexadecimal
EN S : R0
value and store to nibble0 (nibble1~nibble3 remain
N : 1
unchanged) of R100
D : R100
Originally R100＝0000H
R0＝0039H（9）Î R100＝0009H
〈Example 2〉When M1 is ON, ASCII code converted to hexadecimal value.

M1 63. HEX
˙ Converts the ASCII code of R0 and R1 into
EN S : R0
hexadecimal value and store to low byte (high byte
N : 2
remain unchanged) of R100
D : R100
R0＝0039H（9） Originally R100＝0000H

R1＝0041H（A）Î R100＝009AH

M1 63. HEX
EN S : R0 ˙ Converts the ASCII code of R0 and R1 into
N : 3 hexadecimal value and store result into R100 (nibble
D : R100 3 remain unchanged)
R0＝0039H （9） Originally R100＝0000H

R1＝0041H （A）
R2＝0045H （E）Î R100＝09AEH

M1 63. HEX
˙Converts the ASCII code of R0~R5 into hexadecimal
EN S : R0
value and store it to R100~R101
N : 6
D : R100
R0＝0031H（1） Originally R100＝0000H

R1＝0032H（2） R101＝0000H
R2＝0033H（3）
R3＝0034H（4）
R4＝0035H（5）Î R100＝3456H
R5＝0036H（6） R101＝0012H
7-44
FUN 64 P FUN 64 P
CONVERSION OF HEXADECIMAL VALUE TO ASCII CODE
→ASCII →ASCII
S : Starting source register

N : Number of hexadecimal digit to be converted to
ASCII code.
D : The starting register storing result.
S, N, D, can associate with V, Z, P0~P9 to do the
indirect addressing application.

16-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand + number
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 1~511 ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z When conversion control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, will convert the N
successive nibbles of hexadecimal value in registers start from S into ASCII code, and store the result to
low byte (high byte remain unchanged) of the registers which start from D.
z The conversion will not be performed when the value of N is 0 or greater than 511.
z The main purpose of this instruction is to convert the numerical value data, which PLC has processed, to
ASCII code and transmit to ASCII peripherals by communication port1 or communication port 2.
7-45
FUN 64 P FUN 64 P
CONVERSION OF HEXADECIMAL VALUE TO ASCII CODE
→ASCII →ASCII
〈Example 1〉When M1 changes from OFF→ON, it converts hexadecimal value to ASCII code.
M1 64P. ASCII
˙Converts the Nibble 0 of R0 to ASCII code and stores
EN S : R0
it into R100 (High byte does not change).
N : 1
D : R100
R0＝0009H Î R100＝0039H（9）
〈Example 2〉When M1 is ON, it converts hexadecimal value to ASCII code.

M1 64. SCII
EN S : R0 ˙Converts the NB0～NB1 of R0 to ASCII code and
N : 2 stores it into R100 ～ R101 (high bytes remain
D : R100 unchanged).
R0＝009AH Î R100＝0039H（9）
R101＝0041H（A）

M1 64. SCII
EN S : R0 ˙Converts the NB0～NB2 of R0 to ASCII code and
N : 3 stores it into R100～R102
D : R100
R0＝0123H Î R100＝0031H（1）
R101＝0032H（2）
R102＝0033H（3）

M1 64. SCII
˙Converts the NB0～NB5 of R0～R1 to ASCII code
EN S : R0
and stores it into R100～R105
N : 6
D : R100
R0＝3456H Î R100＝0031H（1）
R1＝0012H R101＝0032H（2）
R102＝0033H（3）
R103＝0034H（4）
R104＝0035H（5）
R105＝0036H（6）
7-46
END PROGRAM END END
No operand
z When end control "EN" = 1, this instruction is activated. Upon executing the END instruction and "EN" = 1, the
program flow will immediately returns to the starting point (0000M) to restart the next scan – i.e. all the
programs after the END instruction will not be executed. When "EN" = 0, this instruction is ignored, and
programs after the END instruction will continue to be executed as the END instruction is not exist.
z This instruction may be placed more than one point within a program, and its input (end control "EN") controls
the end point of program execution. It is especially useful for debugging and for testing.
z It’s not necessary to put any END instructions in the main program, CPU will automatic restart to start point
when reach the end of main program.
0000M
Program 1 Program 1
Program execution
X0=1 X0
ORG X0
EN END END
Program 2 Program 2
X0=0
X1=1
X1 ORG X1
EN END END
X0=X1=0 Program 3 Program 3
7-47
FUN 65 FUN 65
LABEL
LBL LBL
S : Alphanumeric, 1~6 characters
z This instruction is used to make a tag on certain address within a program, to provide a target address for
execution of JUMP, CALL instruction and interrupt service. It also can be used for document purpose to
improve the readability and interpretability of the program.
z This instruction serves only as the program address marking to provide the control of procedure flow or for
remark. The instruction itself will not perform any actions; whether the program contains this instruction or not,
the result of program execution will not be influenced by this instruction.
z The label name can be formed by any 1～6 alphanumeric characters and can’t be duplicate in the same
program. The following label names are reserved for interrupt function usage. These “reserved words”, can’t
be used for normal program labels.
Reserved words Description

X0+I～X15+I（INT0～INT15） labels for external input (X0～X15) interrupt
X0−I～X15−I（INT0−～INT15−） service routine.
labels for high speed counter HSC0～HSC7
HSC0I～HSC7I
interrupt service routine.
1MSI（1MS）、2MSI（2MS），3MSI（3MS），
Labels for 8 kinds of internal timer interrupt
4MSI（4MS），5MSI（5MS），10MSI（10MS），
service routine.
50MSI（50MS），100MSI（100MS）
Label for High speed fixed timer interrupt
HSTAI（ATMRI）
service routine.
Labels for the pulse output command
PSO0I～PSO3I
finished interrupt service routine.
Only the interrupt service routine can use the label names listed on above table, if mistaken on using the
reserved label on the normal subroutine can cause the CPU fail or unpredictable operation.
The label of following diagram illustration served only as program remarks (it is not treated as a label for call
or jump target). For the application of labeling in jump control, please refer to JMP instruction for
explanation. As to the labeling serves as subroutine names, please refer to CALL instruction for details.
65
LBL PGM1
Program 1
65
LBL PGM2
Program 2
7-48
FUN 66 P FUN 66 P
JUMP
JMP JMP
LBL : The program label to be jumped
z When jump control “EN”=1 or “EN↑” ( P instruction) changes from 0→1, PLC will jump to the location behind
the marked label and continuous to execute the program.
z This instruction is especially suit for the applications where some part of the program will be executed only
under certain condition. This can shorter the scan time while not executes the whole program.
z This instruction allows jump backward (i.e. the address of LBL is comes before the address of JMP
instruction). However, care should be taken if the jump action cause the scan time exceed the limit set by the
watchdog timer, the WDT interrupt will be occurred and stop executing.
z The jump instruction allows only for jumping among main program or jumping among subroutine area, it can’t
jump across main/subroutine area.
X0 66
˙In the left diagram, when X0=1, the program will jump
EN JMP PATHB directly to the LBL position named PATHB and
continuing to execute program B. Therefore it will
Program A skip the program A and none of the instructions of
program A will be executed. The status of registers
65
LBL PATHB and the coils associated with program A will keep
unchanged (as if there is no program section A).
Program B
7-49
FUN 67 P FUN 67 P
CALL
CALL CALL
LBL : The subroutine label name to be called.
z When call control “EN”=1 or “EN↑” ( P instruction) changes from 0→1, PLC will call (perform) the
subroutine bear the same label name as the one being called. When execute the subroutine, the program
will execute continuous as normal program does but when the program encounter the RTS instruction then
the flow of the program will return back to the address immediately after the CALL instruction.
z All the subroutines must end with one “return from 65

subroutine instruction RTS” instruction; otherwise it LBL SUB1
will cause executing error or CPU shut down.

Nevertheless, an RTS instruction can be shared by Program 1
subroutines (so called as multiple entering 66

SUB1 + JMP SUB3
subroutines; even though the entry points are
different, they have a same returning path) as
65
illustrated in the right diagram subroutine SUB1～3. LBL SUB2
z When main program called a subroutine, the Program 2

subroutine also can call the other subroutines (so
65
called the nested subroutines) for up to 5 levels at LBL SUB3
SUB2
the most (include the interrupt routine).
SUB3 Program 3
1X 2X 3X 4X 5X
68
RTS
LBL SUB1 LBL SUB2 LBL SUB3 LBL SUB4
CALL SUB1 CALL SUB2 CALL SUB3 CALL SUB4
RTS RTS RTS RTS
Main program area Subroutine area
z Interrupt service programs （HSC0I～HSC7I、PSO0I～PSO3I、X0+I～X15+I／INT0～INT15、X0−I～X15−I

／INT0−～INT15−、HSTAI／ATMRI、1MSI／1MS、2MSI／2MS、3MSI／3MS、4MSI／4MS、5MSI／5MS、
10MSI／10MS、50MSI／50MS、100MSI／100MS） are also a kind of subroutine. It is also placed in sub
program area. However, the calling of interrupt service program is triggered off by the signaling of
hardware to make the CPU perform the corresponding interrupt service program (which we called as the
calling of the interrupt service program). The interrupt service program can also call subroutine or
interrupted by other interrupts with higher priority. Since it is also a subroutine (which occupied one level),
it can only call or interrupted by 4 levels of subroutine or interrupt service program. Please refer to RTI
instruction for explanation.
7-50
FUN 68 FUN 68
RETURN FROM SUBROUTINE
RTS RTS
z This instruction is used to represent the end of a subroutine. Therefore it can only appear within the
subroutine area. Its input side has no control signal, so there is no way to serially connect any contacts.
This instruction is self sustain, and is directly connected to the power line.
z When PLC encounter this instruction, it means that the execution of a subroutine is finished. Therefore it will
return to the address immediately after the CALL instruction, which were previously executed and will
continue to execute the program.
z If this instruction encounters any of the three flow control instructions MC, SKP, or JMP, then this instruction
may not be executed (it will be regarded as not exist). If the above instructions are used in the subroutine
and causing the subroutine not to execute the RTS instruction, then PLC will halt the operation and set the
M1933( flow error flag) to 1. Therefore, no matter what the flow is going, it must always ensure that any
subroutine must be able to execute a matched RTS instruction.
z For the usage of the RTS instruction please refer to instructions for the CALL instruction.
7-51
FUN 69 FUN 69
RETURN FROM INTERRUPT
RTI RTI
z The function of this instruction is similar to RTS. Nevertheless, RTS is used to end the execution of sub
program, and RTI is used to end the execution of interrupt service program. Please refer to the explanation
of RTS instruction.
z A RTI instruction can be shared by more than one interrupt service program. The usage is the same as the
sharing of an RTS by many subroutines. Please refer to the explanation of CALL instruction.
z The difference between interrupts and call is that the sub program name (LBL) of a call is defined by user,
and the label name and its call instruction are included in the main program or other sub program.
Therefore, when PLC performs the CALL instruction and the input “EN”=1 or “EN↑” ( instruction)
changes from 0→1, the PLC will call (execute) this sub program. For the execution of interrupt service
program, it is directly used with hardware signals to interrupt CPU to pause the other less important works,
and then to perform the interrupt service program corresponding to the hardware signal (we call it the
calling of interrupt service program). In comparing to the call instruction that need to be scanned to
execute, the interrupt is a more real time in response to the event of the outside world. In addition, the
interrupt service program cannot be called by label name; therefore we preserve the special “reserved
words” label name to correspond to the various interrupts offered by PLC (check FUN65 explanation for
details). For example, the reserved word X0+I is assigned to the interrupt occurred at input point X0; as
long as the sub program contains the label of X0+I, when input point X0 interrupt is occurred (X0: ), the
PLC will pause the other lower priority program and jump to the subroutine address which labeled as X0+I
to execute the program immediately.
z If there is a interrupt occurred while CPU is handling the higher priority (such as hardware high speed
counter interrupt) or same priority interrupt program (please refer to Chapter 10 for priority levels), the PLC
will not execute the interrupt program for this interrupt until all the higher priority programs were finished.
z If the RTI instruction cannot be reached and performed in the interrupt service routine, may cause a serious
CPU shut down. Consequently, no matter how you control the flow of program, it must be assured that the
RTI instruction will be executed in any interrupt service program.
z For the detailed explanation and example for the usage of interrupts, please refer to Chapter 10 for
explanation.
7-52
FUN 70 FUN 70
FOR
FOR FOR
Ladder symbol
70. N : Number of times of loop execution

FOR N
WX WY WM WS TMR CTR HR IR OR SR ROR DR K

Range

Ope-
rand ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
N ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z This instruction has no input control, is connected directly to the power line, and cannot be in series with
any conditions.
z The programs within the FOR and NEXT instructions form a program loop (the start of the loop program is
the next instruction after FOR, and the last is the instruction before NEXT). When PLC executes the FOR
instruction, it first records the N value after that instruction (loop execution number), then for N times
successively execution from start to last of the programs in the loop. Then it jumps out of the loop, and
continues executes the instruction immediately after the NEXT instruction.
z The loop can have a nested structure, i.e. the loop includes other loops, like an onion. 1 loop is called a
level, and there can be a maximum of 5 levels. The FOR and NEXT instructions must be used in pairs. The
first FOR instruction and the last NEXT instruction are the outermost (first) level of a nested loop. The
second FOR instruction and the second last NEXT instruction are the second level, the last FOR instruction
and the first NEXT instruction form the loop's innermost level.
˙In the example in the diagram at left, loop c will be

70 executed 4 ×3 ×2 = 24 times, loop d will be
FOR 2
executed 3 ×2 = 6 times, and loop e will be
executed 2 times.
70 ˙If there is a FOR instruction and no corresponding NEXT
FOR 3
instruction, or the FOR and NEXT instructions in the
nested loop have not been used in pairs, or the sequence
70 of FOR and NEXT has been misplaced, then a syntax
FOR 4 error will be generated and this program may not be
executed.
1 2 3
71 ˙In the loop, the JMP instruction may be used to jump out
NEXT of the loop. However, care must be taken that once the
loop has been entered (and executed to the FOR
instruction), no matter how the program flow jumps, it
71 must be able to reach the NEXT instruction before
NEXT reaching the END instruction or the bottom of the
program. Otherwise FBs-PLC will halt the operation and
show an error message.
71
NEXT ˙The effective range of N is 1~16383 times. Beyond this
range FBs-PLC will treat it as 1. Care should be taken , if
the amount of N is too large and the loop program is too
big, a WDT may occur.
7-53
FUN 71 FUN 71
LOOP END
NEXT NEXT
Ladder symbol
71.
NEXT
z This instruction and the FOR instruction together form a program loop. The instruction itself has no input
control, is connected directly to the power line, and cannot be in series with any conditions.
z When PLC has not yet entered the loop (has not yet executed to the FOR instruction, or has executed but
then jumped out), but the NEXT instruction is reached, then PLC will not take any action, just as if this
instruction did not exist.
z For the usage of this instruction please refer to the explanations for the FOR instruction on the preceding
page.
7-54
FUN 74 P FUN 74 P
IMMIDIATE I/O
IMDIO IMDIO
D : Starting number of I/O points to be refreshed

N : Number of I/O points to be refreshed
Range X Y K
Xn of Yn of 1
Ope- Main Main ∣
rand Unit. Unit. 36
D ○ ○
N ○
● For normal PLC scan cycle, the CPU gets the entire input signals before the program is executed, and then
perform the executing of program based on the fresh input signals. After finished the program execution the
CPU will update all the output signals according to the result of program execution. Only after the complete
scan has been finished will all the output results be transferred all at once to the output. Thus for the input
event to output responses, there will be a delay of at least 1 scan time (maximum of 2 scan time). With this
instruction, the input signals or output signals specified by this instruction can be immediately refresh to get
the faster input to output response without the limitation imposed by the scan method.
● When refresh control "EN" = 1 or "EN↑" ( P instruction) has a transition from 1 to 0, then the status of N
input points or output points (D~D+N-1) will be refreshed.
● The I/O points for FBs-PLC's immediate I/O are only limited to I/O points on the main unit. The table below
shows permissible I/O numbers for 20, 32, 40 and 60 point main units:
Main-unit type
20 points 32 points 40 points 60 points
Permissible numbers
Input signals X0～X11 X0～X19 X0～X23 X0～X35
Output signals Y0～Y7 Y0～Y11 Y0～Y15 Y0～Y23
● If the intended refresh I/O signals of this instruction is beyond the range of I/O points specified on above
table then PLC will be unable to operate and the M1931 error flag will be set to 1. ( for example, if in a
program, D=X11, N=10, which means X11 to X20 are to be immediately retrieved. Supposing the main unit
is FBs-32MA, then its biggest input point is X19, and clearly X20 has already exceeded the main unit's input
point number so under such case M1931 error flag will be set to 1).
● With this instruction, PLC can immediately refresh input/output signals. However, the delay of the hardware
or the software filter impose on the I/O signals still exist. Please pay attention on this.
7-55
FUN 76 D FUN 76 D
DECIMAL- KEY INPUT
TKEY TKEY
IN : Key input point

D : register storing key-in numerals
KL: starting coil to reflect the input status
Range X Y M S WY WM WS TMR CTR HR OR SR ROR DR XR

X0 Y0 M0 S0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand X240 Y240 M1896 S984 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 P0~P9
IN ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
KL ○ ○ ○
z This instruction has designated 10 input points IN~IN+9 (IN0~IN9) to one decimal number entry (IN->0,
IN+1->1…). According to the key-in sequence (ON) of these input points, it is possible to enter 4 or 8
decimal numbers into the registers specified by D.
z When input control "EN" = 1, this instruction will monitor the

10 input points starting from IN and put the corresponding
number into D register while the key were depressed. It will
wait until the input point has released, then monitor the next
"ON" input point, and shift in the new number into D register
(high digit is older than low digit ) . For the 16-bit operand, D
register can store up to 4 digits, and for the 32-bit operand 8 Key-in
digits may be stored. When the key numbers full fill the D IN0 ~ IN9 0 1 2 9
register, new key-in number will kick out the oldest key
number of the D register. The key-in status of the 10 input
points starting from IN will be recorded on the 10 BCD Code
corresponding coil starting from KL. These coils will set to 1
while the corresponding key is depressed and remain Forced out
unchanged even if the corresponding key is released. Until
other key is depressed then it will return to zero. As long as 1000S 100S 10S 1S
any input point is depressed (ON), then the key-in flag KPR
will set to 1. Only one of IN0~IN9 key can be depressed at
the same time. If more than one is pressed, then the first D BIN(0~9999)
one is the only one taken. Below is a schematic diagram of
the function with 16-bit operand.
z When input control "EN" = 0, this instruction will not be executed. KPR output and KL coil status will be 0.
However, the numerical values of D register will remain unchanged.
76.TKEY Y0 ˙The instruction at left represents the input point X0 with

X20
EN IN : X 0 KPR the number "0", X1 is represented by 1, ... , M0 records
D : R 0 the action of X0, M1 records the action of X1 ... , and the
KL : M 0 input numerical values are stored in the R0 register.
7-56
FUN 76 D FUN 76 D
DECIMAL- KEY INPUT
TKEY TKEY
The following diagram is the input wiring schematic for this example:
0 1 2 3 4 5 6 7 8 9
C X0 X1 X2 X3 X4 X5 X6 X7 X8 X9
FBS-PLC input side
z If the X0~X3 key-in sequence follow the cdefghi sequence in the following diagram. At step c
and i the X20 is 0, so there was no key generated, only steps defgh are effective. Because the
register can only hold 4 key numbers, Of these 5 steps the first key was kick out. The key strokes 3302 of
the steps efgh are entered in the R0 register.
X20
5
X0
2 7
X1
1 6
X2
3 4
X3
M0
M1
M2
M3
2 3 4
4 5 6
Y0
R0 0000
0000 0001
0001 0013
0013 0133
0133 1330
1330 3302
3302
7-57
FUN 77 D FUN 77 D
HEX-KEY INPUT
HKEY HKEY
Ladder symbol
IN : Starting of digital input for key scan
77D.HKEY
OT: Starting of digital output for multiplexing
Execution control EN IN : NKP Number key press key scan (4 points)
OT : D : Register to store key-in numbers
D : FKP Function key press KL : Starting relay for key status
WR: Working register, it can't repeat in use
KL :
D may combine with V、Z、P0~P9 to serve
WR : indirect addressing application
Range X Y M S WY WM WS TMR CTR HR OR SR ROR DR XR

X0 Y0 M0 S0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand X240 Y240 M1896 S984 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 P0~P9
IN ○
OT ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
KL ○ ○ ○
WR ○ ○* ○
z The numeric (0~9) key function of this instruction is similar as for the TKEY instruction. The hardware
connection for TKEY and HKEY is different. For TKEY instruction each key have one input point to connect,
while HKEY use 4 input points and 4 output points to form a 4x4 multiplex 16 key input. 4×4 means that
there can be 16 input keys, so in addition to the 10 numeric keys, the other 6 keys can be used as function
keys (just like the usual discrete input). The actions of the numeric keys and the function keys are
independent and have no effect on each other.
z When execution control "EN" = 1, this instruction will scan the numeric keys and function keys in the matrix
formed by the 4 input points starting from IN and the 4 output points starting from OT. For the function of the
numeric keys and "NKP" output please refer to the TKEY instruction. The function keys maintain the key-in
status of the A~F keys in the last 6 relays specified by KL (the first 10 store the key-in status of the numeric
keys). If any one of the A~F keys is depressed, FKP (FO1) will set to 1. The OT output points for this
instruction must be transistor outputs.
z The biggest number for a 16-bit operand is 4 digits (9999), and for 32-bit operand is 8 digits (99999999).
However, there are only 6 function keys (A~F), no matter whether it is a 16-bit or 32-bit operand.
77D.HKEY
X10 M10
Function
EN IN : X0 NKP Keys C D E F
OT : Y0
D : R0 M11 8 9 A B
KL : M0 FKP
WR : D0 Numeric
4 5 6 7
Keys
0 1 2 3
˙ The instruction in the diagram above S/S X0 X1 X2 X3
uses X0~X3 and Y0~Y3 to form a +
24V PLC (transistor output)
multiplex key input. It can input numeric -
values of 8 digits and stores the results
in R1R0. The input status of the function
keys is stored in M10(A)~M15(F). C Y0 Y1 Y2 Y3
7-58
FUN 78 D FUN 78 D
DIGITAL SWITCH INPUT
DSW DSW
IN : Starting of input for thumb wheel switch
OT : Starting of output for multiplexing scan
(4 points)
D : Register to store readout value
WR: Working register, it can't repeat in use
(WR & WR+1 for 16-bit operation;
WR, WR+1 & WR+2 for 32-bit operation)
D may combine with V、Z、P0~P9 to serve
indirect addressing application
Range X Y WY WM WS TMR CTR HR OR SR ROR DR XR

X0 Y0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand X240 Y240 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 P0~P9
IN ○
OT ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
WR ○ ○* ○
z When input control "EN" = 1, this instruction will readout one digit data from the 4 input points starting from
IN (IN0~IN3). It takes 4 scans to read out a group of 4-digit BCD values (0000~9999) and store them into D
register. With a 32-bit operand, each scan can get 2 digits of data by reading the additional digit from
IN4-IN7 and store it in the D+1 register. Each bit of OT0~OT3 will sequentially set to 1 and get the digit data
0 1 2 3
respectively into 10 (ones), 10 (tens), 10 (hundreds), and 10 (thousands). As long as EN is 1, PLC will
scan and read out in continuous cycles. When each complete cycle is finished (i.e. the 4 digit readout of
0 3
10 ~10 is completed), the readout completed flag "DN" is set to 1. However, it is only kept for one scan. If
any digital readout value is not within the range of 0~9 (BCD), then reading error "ERR" will be set to 1 and
the value of that group of digits will be set to 0000.
z The output points must be transistor outputs.
78.DSW ˙In this example, when X10 is 1, then the numeric value of the
X10 M10
thumb wheel switch (5678 in this example) will be read out
EN IN : X0 DN
and stored into the R0 register.
OT : Y0
M11 ˙The bits (8,4,2,1) with same digit should be connect together
D : R0
ERR and series with a diode (as shown in diagram below).
WR : D0
˙With 32-bit operand a set of similar thumb wheel switch may
be added to X4~X7 (Y0~Y3 are shared with another group).
10 3 (5) 10 2 (6) 10 1 (7) 10 0 (8)
BCD thumb
wheel swith
8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1
1 2 4 8
S/S X0 X1 X2 X3 X4 X5 X6 X7
+ first group input second group input

24V (only effective in
- 32-bit operand)
C Y0 Y1 Y2 Y3
PLC
7-59
FUN 79 D FUN 79 D
7-SEGMENT OUTPUT WITH LATCH
7SGDL 7SGDL
S : Register storing the data (BCD) to be

displayed
OT : Starting number of scanning output
N : Specify signal output and polarity of latch
WR : Working register, it can't repeat in use
S may combine with V、Z、P0~P9 to serve
indirect addressing application
Range Y WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR

Y0 WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 V、Z
16-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
number
rand Y240 WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0~P9
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OT ○
N 0～3
z When input control "EN" = 1, the 4 nibbles of the S register, from digit 0 to digit 3, are sequentially sent out to
the 4 output points, OT0~OT3. While output the digit data, the latch signal of that digit (OT4 corresponds to
digit 0, OT5 corresponds to digit 1, etc...) at the same time is also sent out so that the digital value will be
loaded and latched into the 7-segment display respectively.
z When in D (32-bit) instruction, nibbles 0~3 from the S register, and nibbles 0~3 from the S+1 register are
transferred separately to OT0~OT3 and OT8~OT11. Because they are transferred at the same time, they can
use the same latch signal. 16-bit instructions do not use OT8~OT11.
z As long as "EN" remains 1, PLC will execute the transfer cyclically. After each transfer of a complete group of
numerical values (nibbles 0~3 or 0~7), the output completed flag "DN" will set to 1. However, it will only be kept
for 1 scan.
79D.7SGDL z In this example, when X0=1, the 4 nibbles of R0

X0 M10
EN S : R0 DN will be transferred to the first group 7-segment
OT : Y0 display in the diagram below. The 4 nibbles of R1
N : 2 will be transferred to the second group 7-segment
WR : D0 display.
first group second group

8 8
4 VCC 4 VCC
2 COM 2 COM
1 1
3 2 1 0 3 2 1 0
10 10 10 10 10 10 10 10
0 1 2 3
1 2 4 8 10 10 10 10 1 2 4 8
C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11
NPN
PLC transistor output
7-60
FUN 79 D FUN 79 D
7-SEGMENT OUTPUT WITH LATCH
7SGDL 7SGDL
z FACON PLC's transistor output has both a negative logic transistor output (NPN transistor - when the output
status is ON, the terminal voltage of the transistor output is low), and a positive logic transistor output (PNP -
when the output status is ON, the terminal voltage of the transistor output is high). Their structure is as follows:
FBs-PLC negative logic output (NPN transistor) FBs-PLC positive logic output (PNP transistor)
+24V +24V +24V C +24V

Yn
When Yn is When Yn is "ON",
Yn Yn
"ON", this output Yn Yn's terminal
voltage is low voltage is high
0V C 0V 0V
z The data inputs (8,4,2,1) and latch signals of the 7-segment displays on the shelf for positive and negative logic
are all available. For example, for numerical value "8", the positive logic input should be 1000, and the negative
logic input 0111. Similarly, when the latch signal is 0, the positive logic latch permits the display numerical values
to enter through the latch (i.e. be loaded). When the latch signal is 1, the numerical values in the latch are
latched (maintained), and with negative logic they are not. The following diagram of a CD-4511 7-segment
display IC is an example of a positive logic numerical value input with latch.
CD4511
Numberical value input
R
a a
(1)A b
(2)B BCD to LED c f g b
4bit d
(4)C latch 7-segment Drive e e c
f
(8)D g d
n
(10 ) LE LT BI
VCC
Latch sing 1
z Because the PLC output and the 7-segment display input polarity can be positive and negative logic. Therefore,
the polarities between output and input must be coordinated to get the correct result. This instruction uses N to
specify the polarity relation between the PLC transistor output, and the 7-segment display. The table below
shows all the possibility.
0 3
Numerical value input (8~1) Latch signal (10 -10 ) Value of N
Same 0
Same
Different 1
Same 2
Different
Different 3
z In the diagram above, CD4511 is used as an example. If use NPN output, the data input polarity is different to
PLC, and its latch input polarity is the same as PLC, so N value should chosen as 2.
7-61
FUN 80 FUN 80
MULTIPLEX INPUT
MUXI MUXI
IN : Multiplex input point number

OT : Multiplex output point number
(must be transistor output point)
N : Multiplex input lines (2~8)
D : Register for storing results
Range X Y WY WM WS TMR CTR HR OR SR ROR DR K XR

X0 Y0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 2 V 、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand X240 Y240 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 8 P0~P0
IN ○
OT ○
N ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
z This instruction uses the multiplex method to read out N lines of input status from 8 consecutive input points
(IN0~IN7) starting from the input point specified by IN. With this method we can obtain 8×N input status, but
only need to use 8 input points and N output points.
z The multiplex scanning method goes through N output points starting from the OT output point. Each scan one
of the N bits will set to 1 and the corresponding line will be selected. OT0 responsible for first line, while OT1
responsible for second line, etc. Until it read all the N lines the 8×N status that has been read out is then stored
into the register starting at D, and the execution completed flag "DN" is set as 1 (but is only kept for one
scanning period).
z With every scan, this instruction retrieves a line for 8 input status, so N lines require N scan cycles before they
can be completed.
80.MUXI z This example retrieves 4 lines×8 points of input,

X0 M10
EN IN : X24 DN 32 point status in all. They are stored into the
OT : Y16 32-bit register of DWM0 (M0~M31).
N : 4
D : WM0
WR : D0
Fourth line
M24 M25 M26 M27 M28 M29 M30 M31

Third line
M16 M17 M18 M19 M20 M21 M22 M23 Second line
M8 M9 M10 M11 M12 M13 M14 M15 First line
M0 M1 M2 M3 M4 M5 M6 M7
S/S X24 X25 X26 X27 X28 X29 X30 X31

PLC NPN transistor output
24V
C Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23
7-62
FUN 81 D FUN 81 D
PULSE OUTPUT
PLSO PLSO
MD : Output mode selection

Fr : Pulse frequency
PC : Output pulse count
UY : Up pulse output point (MD=0).
DY : Down pulse output point (MD=0).
HO : Cumulative output pulse register.
(Can be not assigned).
CK : Pulse output point (MD=1).
DR : Up/Down output point (MD=1).
DIR: 1- up; 0- down.
Range Y WX WY WM WS TMR CTR HR OR SR ROR DR K

Yn of WX0 WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0
16/32-bit
Ope- Main ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
rand Unit WX240 WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095
MD 0～1
Fr ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 8～2000
PC ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
UY，CK ○
DY，DR ○
HO ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When MD=0, this instruction performs the pulse output control as following:
z Whenever the output control “EN” changes from 0→1, it first performs the reset action, which is to clear the
output flag “OUT” and “DN” as well as the pulse out register HO to be 0. It gets the pulse frequency and
output pulse count values, and reads status of up and down direction “U/D”, so as to determine the direction
to be upward or downward. As the reset finished, this instruction will check the input status of pause output
“PAU”. No action will be taken if the pause output is 1 (output pause). If the PAU is 0, it will start to output
the ON/OFF pulse with 50% duty at the frequency Fr to the UY(U/D=1) or DY(U/D=0) point. It will increment
the value of HO register each time when a pulse is output, and will stop the output when HO register’s pulse
count is equal to or greater than the cumulative pulse count of PC register and set the output complete flag
“DN” to 1. During the time when output pulse is transmitting the output transmitting flag “OUT” will be set to 1,
otherwise it will be 0.
z Once it starts to transmit pulse, the output control “EN” should kept to 1. If it is changed to 0, it will stop the
pulse sending (output point become OFF) and the flag “OUT” changes back to 0, but the other status or data
will keep unchanged. However, when its “EN” changes again from 0 to 1, it will lead to a reset action and
treat as a new start; the entire procedure will be restarted again.
z If you want to pause the pulse output and not to restart the entire procedure, the ‘pause output’ “PAU” input
can be used to pause it. When “PAU” =1, this instruction will pause the pulse transmitting (output point is
OFF, flag “OUT” change back to 0 and the other status or data keeps unchanged). As it waits until the
“PAU” changes back from 1 to 0, this instruction will return to the status before it is paused and continues the
pulse transmitting output.
z During the pulse transmission, this instruction will keep monitoring the value of pulse frequency Fr and output
pulse count PC. Therefore, as long as the pulse output is not finished, it may allow the changing of the pulse
frequency and pulse count. However, the up/down direction “U/D” status will be got only once when it takes
the reset action (“EN” changes from 0→1), and will keep the status until the pulse output completed or
another reset occur. That is to say, except that at the very moment of reset, the change of “U/D” does not
influence the operation of this instruction.
z The main purpose of this instruction is to drive the stepping motor with the UY (upward) and DY (downward)
two directional pulses control, so as to help you control the forward or reverse rotating of stepping motor.
Nevertheless, if you need only single direction revolving, you can assign just one of the UY or DY (which will
save one output point), and leaving the other output blank. In such case, the instruction will ignore the
up/down input status of “U/D”, and the output pulse will send to the output point you assigned.
7-63
FUN 81  FUN 81 
PULSE OUTPUT
PLSO PLSO
z When MD=1, the pulse output will reflect on the control output DIR (pulse direction. DIR=1, up; DIR=0, down)
and CK (pulse output).
z This instruction can only be used once, and UY (CK) and DY (DR) must be transistor output point on the PLC
main unit.
z The effective range of output pulse count PC for 16 bit operand is 0～32767. For the 32 bit operand(
instruction), it is 0～2147483647. If the PC value = 0, it is treated as infinite pulse count, and this instruction
will transmit pulses without end with HO value and “DN” flag set at 0 all the time. The effective range of pulse
frequency (Fr) is 8～2000. If the value PC or Fr exceeds the range, this instruction will not be carried out and
the error flag “ERR” will set to 1.
z In this example, the program controls the stepping motor

81D.PLSO
X0 M0 to drive forward for 80 pulses (steps) at the speed of
EN MD : 0 OUT
100Hz first, and then makes it turn reverse for 40 pulses
X1 Fr : R 0 M1
PAU PC : R 1 DN the speed of 50Hz. Make sure that the up/down direction,
X2 UY : Y 0 frequency Fr and the pulse count PC must be set before
U/D DY : Y 1 ERR the reset take action(“EN” changes from 0→1).
HO : R 5
Turn forward Turn reverse

100Hz going 80 steps 50Hz going 40 steps Stop
Reset Stop
enable re-start (finished) Reset Start (finished)
Output enable X0
Pause
Pause X1
Forward Recerse
Direction X2
1 2 76 77 78 79 80
Up-pulse Y0
1 2 40
Down-pulse Y1
Under output M0
Output done M1
Frequency R0 100 50
Pulse to output R1 80 40
Output pulse count R5 0 1 2 75 76 77 78 79 80 0 1 2 39 40
7-64
FUN 82 FUN 82
PULSE WIDTH MODULATION
PWM PWM
To : Pulse ON width
(0~32767mS)
Tp : Pulse period
(1~32676mS)
OT: Pulse output point
Range Y WX WY WM WS TMR CTR HR IR OR SR ROR DR K

Yn WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 0
Ope- of main ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand unit WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 32767
To ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Tp ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
OT ○
z When execution control "EN" = 1, will send the pulse to output point OT with the "ON" state for To ms and
period as Tp. OT must be a transistor output point on the main unit. When "EN" is 0, the output point will be
OFF.
To
Tp
z The units for Tp and To are mS, resolution is 1 mS. The minimum value for To is 0 (under such case the
output point OT will always be OFF), and its maximum value is the same as Tp (under such case the output
point OT will always be on). If To > Tp there will be an error, this instruction will not be carried out, and the
error flag "ERR" will set to 1.
z This instruction can only be used once.
7-65
FUN 83 FUN 83
SPEED DETECTION
SPD SPD
S : Pulse input point for speed detection

TI : Sampling duration
(units in mS)
D : Register storing results
Range X WX WY WM WS TMR CTR HR IR OR SR ROR DR K

X0 WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 1
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand X7 WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 32767
S ○
TI ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z This instruction uses the interrupt feature of the 8 high speed input points (X0~X7) on the PLC main unit to
detect the frequency of the input signal. Within a specific sampling time (TI), it will calculate the input pulse
count for S input point, and indirectly find the revolution speed of rotating devices (such as motors).
z While use this instruction to detect the rotating speed of devices, The application should design to generate
more pulse per revolution in order to get better result, but the sum of input frequency of all detected signals
should under 5KHz, otherwise the WDT may occur.
z The D register for storing results uses 3 successive 16-bit registers starting from D (D0~D2). Besides D0
which is used to store counting results, D1 and D2 are used to store current counting values and sampling
duration.
z When detection control "EN" = 1, it starts to calculate the pulse count for the S input point, which can be
shown in D1 register. Meanwhile the sampling timer (D2) is switched on and keeps counting until the value of
D2 is reach to the sampling period (TI). The final counted value is stored into the D0 register, and then a new
counting cycle is started again. The sampling counting will go on repeating until "EN" = 0.
z Because D0 only has 16 bits, so the maximum count is 32767. If the sampling period is too long or the input
pulse is too fast then the counted value may exceed 32767, under that case the overflow flag will set to 1, and
the counting action will stop.
z Because the sampling period TI is already known and if every revolution of attached rotating device produces
"n" pulses, then the following equation can be used to get the revolution
(D0) × 60
speed : N = × 103 
(rpm)
n × TI
83.SPD X20
X20
EN S : X 0 OVF
TI : 1000 X0
D : R 0 1000
z In the above example, if every revolution of the rotating R2 0

1000mS 1000mS 1000mS
device produces 20 pulses (n = 20), and the R0 value is
200, then the revolution per minute speed "N" is as
R1a R1b R1c
( 200 ) × 60 0
follows : N = × 10 3 = 200 rpm R1
60 × 1000 a b c
R0 R1a R1b R1c
7-66
FUN 84 FUN 84
PATTERN CONVERSION FOR 16/7-SEGMENT DISPLAY
TDSP TDSP
Md : Mode selection
S : Starting address of begin converted characters
Ns : Start of character
Nl : Length of character
D : Starting address to store the converted pattern
S operand can be combined with V, Z, P0~P9 index
registers for indirect addressing
HR OR ROR DR K XR
Range
R0 R3904 R5000 D0 V、Z
∣ ∣ ∣ ∣ 16/32 bit
Operand P0~P9
R3839 R3967 R8071 D4095
Md 0~1
S ○ ○ ○ ○ ○ ○
Ns ○ ○ ○ ○ ○
Nl ○ ○ ○ ○ ○
D ○ ○ ○* ○
● This instruction is used for FBs-7SG1/FBs-7SG2 module’s application. It can convert the source
alphanumeric characters into display patterns suited for 16 segment encoded mode display or perform the
leading zero substitution of the packed BCD number for non-decoded mode 7 segment display.
● When execution control “EN” = 1, and input “OFF” = 0, input “ON” = 0, if Md = 0, this instruction will
perform the display pattern conversion, where S is the starting address storing the begin converted
characters, Ns is the pointer to locate the starting address character, Nl tells the length of begin converted
characters, and D is the starting address to store the converted result.
Byte 0 of S is the “1st” displaying character, byte 1 of S is the 2nd displaying character,…….
Ns is the pointer to tell where the start character is.
Nl is the character quantity for conversion.
After execution, each 8-bit character of the source will be converted into the corresponding 16-bit display
pattern.
● When input “OFF” = 1, all bits of display pattern will be ‘off’ if Md = 0. if Md=1, all BCD codes will be
substituted by blank code(0F)
● When input “ON”= 1,all bits of display pattern will be ‘on’ if Md = 0. if Md = 1, all BCD codes will be
substituted by code 8(all light).
● Please refer Chapter 16 “FBs-7SG display module” for more detail description.
16-Segment display patterns shown as below :
7-67
FUN 84 FUN 84
PATTERN CONVERSION FOR 16/7-SEGMENT DISPLAY
TDSP TDSP
MSB
x000 x001 x010 x011 x100 x101 ● If you don’t find the pattern that you want in left table,
LSB
you can create the pattern by yourself just reference
0000 below table.
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
7-68
FUN 86 FUN 86
PID TEMPERATURE CONTROL INSTRUCTION
TPCTL TPCTL
Md: Selection of PID method

=0, Modified minimum overshoot method
=1, Universal PID method
Yn: Starting address of PID ON/OFF output;
it takes Zn points.
Sn: Starting point of PID control of this instruction;
Sn = 0～31.
Zn: Number of the PID control of this instruction;
1≤Sn+Zn≤32
Sv: Starting register of the set point:
it takes Zn registers.
Os: Starting register of the in-zone offset;
PR: Starting register of the gain (Kc):
IR: Starting register of integral tuning constant
(Ti);it takes Zn registers..
Range Y HR ROR DR K
Y0 R0 R5000 D0 DR: Starting register of derivative tuning constant
Ope- ∣ ∣ ∣ ∣ (Td); it takes Zn registers.
rand Y255 R3839 R8071 D3999
OR: Starting register of the PID analog output.
Md 0～1
Yn ○
Sn 0～31 WR: Starting of working register for this
Zn 1～32 instruction.
Sv ○ ○* ○ It takes 9 registers and can’t be repeated in
using.
Os ○ ○* ○
PR ○ ○* ○
IR ○ ○* ○
DR ○ ○* ○
OR ○ ○* ○
WR ○ ○* ○
Function guide and notifications

z By employing the temperature module and table editing method to get the current value of temperature and
let it be as so called Process Variable (PV); after the calculation of software PID expression, it will respond
the error with an output signal according to the setting of Set Point (SP),the error's integral and the rate of
change of the process variable. Through the closed loop operation, the steady state of the process may be
expected.
z Convert the output of PID calculation to be the time proportional on/off (PWM) output, and via transistor
output to control the SSR for heating or cooling process; this is a good performance and very low cost
solution.
z Through the analog output module (D/A module), the output of PID calculation may control the SCR or
proportional valve to get more precise process control.
z Digitized PID expression is as follows:
n
Mn = [Kc×En]+ ∑ [Kc×Ti×Ts×En]−[Kc×Td×(PVn−PVn-1)/Ts]
0
Where,
Mn: Output at time “n”.
Kc: Gain (Range: 1～9999；Pb=100(%) / Kc)
Ti: Integral tuning constant (Range:0～9999, equivalent to 0.00～99.99 Repeat/Minute)
Td: Derivative tuning constant (Range:0～9999, equivalent to 0.00～99.99 Minute)
7-69
FUN 86 FUN 86
TPCTL TPCTL
PVn : Process variable at time “n”

PVn_1: Process variable when loop was last solved
En: Error at time “n” ; E= SP – PVn
Ts: Solution interval for PID calculation (Valid value are 10, 20, 40, 80,160, 320; the unit is in 0.1Sec)
PID Parameter Adjustment Guide
z As the gain (Kc) adjustment getting larger, the larger the proportional contribution to the output. This can
obtain a sensitive and rapid control reaction. However, when the gain is too large, it may cause oscillation.
Do the best to adjust “Kc” larger (but not to the extent of making oscillation), which could increase the
process reaction and reduce the steady state error.
z Integral item may be used to eliminate the steady state error. The larger the number (Ti, integral tuning
constant), the larger the integral contribution to the output. When there is steady state error, adjust the “Ti”
larger to decrease the error.
When the “Ti” = 0, the integral item makes no contribution to the output.
For exam. , if the reset time is 6 minutes, Ti=100/6=17；if the integral time is 5 minutes, Ti=100/5=20.
z Derivative item may be used to make the process smoother and not too over shoot. The larger the number
(Td, derivative tuning constant), the larger the derivative contribution to the output. When there is too over
shoot, adjust the “Td” larger to decrease the amount of over shoot.
When the “Td” = 0, the derivative item makes no contribution to the output.
For exa, if the rate time is 1 minute, then the Td = 100; if the differential time is 2 minute, then the Td = 200.
z Properly adjust the PID parameters can obtain an excellent result for temperature control.
z The default solution interval for PID calculation is 4 seconds (Ts=40)
z The default of gain value (Kc) is 110, where Pb=1000/110×0.1%≒0.91%; the system full range is 1638°, it
means 1638×0.91≒14.8°to enter proportional band control.
z The default of integral tuning constant is 17, it means the reset time is 6 minutes (Ti=100/6=17).
z The default of derivative tuning constant is 50, it means the rate time is 0.5 minutes (Td=50).
z When changing the PID solution interval, it may tune the parameters Kc, Ti, Td again.
Instruction guide
z FUN86 will be enabled after reading all temperature channels.
z When execution control “EN” = 1, it depends on the input status of H/C for PID operation to make heating
(H/C=1) or cooling (H/C=0) control. The current values of measured temperature are through the
multiplexing temperature module ; the set points of desired temperature are stored in the registers starting
from Sv. With the calculation of software PID expression, it will respond the error with an output signal
according to the setting of set point, the error's integral and the rate of change of the process variable.
Convert the output of PID calculation to be the time proportional on/off (PWM) output, and via transistor
output to control the SSR for heating or cooling process; where there is a good performance and very low
cost solution. It may also apply the output of PID calculation (stored in registers starting from OR), by way
of D/A analog output module, to control SCR or proportional valve, so as to get more precise process control.
z When the setting of Sn, Zn (0 Sn 31 and 1 Zn 32, as well as 1 Sn + Zn 32) comes error, this
instruction will not be executed and the instruction output “ERR” will be ON.
This instruction compares the current value with the set point to check whether the current temperature falls within
deviation range (stored in register starting from Os). If it falls in the deviation range, it will set the in-zone bit of
that point to be ON; if not, clear the in-zone bit of that point to be OFF, and make instruction output “ALM” to be
ON.
7-70
FUN 86 FUN 86
TPCTL TPCTL
z In the mean time, this instruction will also check whether highest temperature warning (the register for the set
point of highest temperature warning is R4008). When successively scanning for ten times the current
values of measured temperature are all higher than or equal to the highest warning set point, the warning bit
will set to be ON and instruction output “ALM” will be on. This can avoid the safety problem aroused from
temperature out of control, in case the SSR or heating circuit becomes short.
z This instruction can also detect the unable to heat problem resulting from the SSR or heating circuit runs open,
or the obsolete heating band. When output of temperature control turns to be large power (set in R4006
register) successively in a certain time (set in R4007 register), and can not make current temperature fall in
desired range, the warning bit will set to be ON and instruction output “ALM” will be ON.
z WR: Starting of working register for this instruction. It takes 9 registers and can’t be repeated in using.
The content of the two registers WR+0 and WR+1 indicating that whether the current temperature falls
within the deviation range (stored in registers starting from Os). If it falls in the deviation range, the
in-zone bit of that point will be set ON; if not, the in-zone bit of that point will be cleared OFF.
Bit definition of WR+0 explained as follows:
Bit0=1, it represents that the temperature of the Sn+0 point is in-zone…
Bit15=1, it represents that the temperature of the Sn+15 point is in-zone.
Bit0=1, it represents that the temperature of the Sn+16 point is in-zone…
Bit15=1, it represents that the temperature of Sn+31 point is in-zone.
The content of the two registers WR+2 and WR+3 are the warning bit registers, they indicate that
whether there exists the highest temperature warning or heating circuit opened.
Bit0=1, it means that there exists the highest warning or heating circuit opened at the Sn+0 point...
Bit15=1, it means that there exists the highest warning or heating circuit opened at the Sn+15 point.
Bit0=1, it means that there exists the highest warning or heating circuit opened at the Sn+16 point...
Bit15=1 , it means that there exists the highest warning or heating circuit opened at the Sn+31 point.
Registers of WR+4 ～ WR+8 are used by this instruction.
z It needs separate instructions to perform the heating or cooling control.
Specific registers related to FUN86

z R4005 : The content of Low Byte to define the solution interval between PID calculation
=0, perform the PID calculation every 1 seconds.
=2, perform the PID calculation every 4 seconds. (System default)
≥5, perform the PID calculation every 32 second.
: The content of High Byte to define the cycle time of PID ON/OFF（PWM）output.
=0，PWM cycle time is 1 seconds.
=1，PWM cycle time is 2 seconds. (System default)
≥5，PWM cycle time is 32 second.
Note 1: When changing the value of R4005, the execution control “EN” of FUN86 must be set at 0. The next time
when execution control “EN” =1, it will base on the latest set point to perform the PID calculation.
Note 2: The smaller the cycle time of PWM, the more even can it perform the heating. However, the error caused
by the PLC scan time will also become greater. For the best control, it can base on the scan time of PLC
to adjust the solution interval of PID calculation and the PWM cycle time.
7-71
FUN 86 FUN 86
TPCTL TPCTL
z R4006: The setting point of large power output detection for SSR or heating circuit opened, or heating band
obsolete. The unit is in % and the setting range falls in 80～100(%); system default is 90(%).
z R4007: The setting time to detect the continuing duration of large power output while SSR or heating circuit
opened, or heating band obsolete. The unit is in second and the setting range falls in 60～65535
(seconds); system default is 600 (seconds).
z R4008: The setting point of highest temperature warning for SSR, or heating circuit short detection. The
unit is in 0.1 degree and the setting range falls in 100～65535; system default is 3500 ( Unit in 0.1
°).
z R4012: Each bit of R4012 to tell the need of PID temperature control.
st
Bit0=1 means that 1 point needs PID temperature control.
nd
‧
‧
th
(The default of R4012 is FFFFH)
z R4013: Each bit of R4013 to tell the need of PID temperature control.
th
th
‧
‧
th
(The default of R4013 is FFFFH)
z While execution control “EN”=1 and the corresponding bit of PID control of that point is ON (corresponding
bit of R4012 or R4013 must be 1), the FUN86 instruction will perform the PID operation and respond to the
calculation with the output signal.
z While execution control “EN”=1 and the corresponding bit of PID control of that point is OFF (corresponding
bit of R4012 or R4013 must be 0), the FUN86 will not perform the PID operation and the output of that point
will be OFF.
z The ladder program may control the corresponding bit of R4012 and R4013 to tell the FUN86 to perform or
not to perform the PID control, and it needs only one FUN86 instruction.
7-72
FUN89/FUN89D (T1S) FUN89/FUN89D (T1S)

FUN88/FUN88D (T.1S) CUMULATIVE TIMER FUN88/FUN88D (T.1S)
FUN87/FUN87D (T.01S) FUN87/FUN87D (T.01S)
CV : Register storing elapse time

(current value)
PV : Preset value of timer

WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 0～32767
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ or
rand WX240 WY240 WM1896 WS984 T255 C199 R3839 R3903 R3967 R4167 R8071 D4095 0～2147483647
CV ○ ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
PV ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
z The operation for this instruction is the same as that for the basic timer (T0~T255), except that the basic
timer only has a "timing control" input - when its input is 1 it starts timing, and when input is 0 it get clear.
Every time the input changes, it starts timing again and is unable to accumulate. Timing with this instruction
is only permissible when enable control "EN" = 1. With this instruction, when timing control "TIM" is 1, it is
the same as a basic timer, but when "TIM" is 0, it does not clear, but keeps the current value. If the timer
need to clear, then change enable control "EN" to 0. When timing control "TIM" is once again to be 1, it will
continue to accumulate from the previous value when the timer last paused. In addition, this instruction also
has two outputs, "Time up TUP" (when time up it is 1, usually it is 0) and "Time not up" (usually it is 1, when
time is up it is 0). Users can utilize input and output combinations to produce timers with various different
functions. For example:
z On delay energizing timer:

z This timer's output (Y0 in this example) is
89.T1S
normally not energized. When this timer's
X0 Y0
input control (X0 in this example) is activated
TIM CV : R 0 TUP
PV : 10 (ON), only after delay by 10 sec will output
EN NUP Y0 become energized (ON).
z On delay de-energizing timer:

z The output Y0 of this timer is usually
89.T1S
energized. When this timer's input control X0
X0
is on, only after delay by 10 sec will the
TIM CV : R 0 TUP
PV : 10 Y0 output become de-energized (OFF).
EN NUP
7-73
FUN89/FUN89D (T1S) FUN89/FUN89D (T1S)

FUN88/FUN88D (T.1S) CUMULATIVE TIMER FUN88/FUN88D (T.1S)
FUN87/FUN87D (T.01S) FUN87/FUN87D (T.01S)
z Off delay energizing timer:

z This timer's output Y0 is usually
de-energized. When this timer's input control
89.T1S Y0 X0 is off, only after delay by 10 sec will
X0
TIM CV : R 0 TUP output Y0 become energized (ON).
PV : 10
EN NUP
z Off delay de-energizing timer:

z This timer's output Y0 is usually energized.
89.T1S
When this timer's timing control X0 is off,
X0
only after delay by 10 sec will output Y0
TIM CV : R 0 TUP
PV : 10 Y0 become de-energized (OFF).
EN NUP
z The diagram below shows the relation on input and output for the above 4 kinds of timers.
"ON" (X0 pressed down) "OFF" (X0 released)

ON
X0 OFF OFF
10S
ON
ON delay energizing OFF OFF
ON 10S
ON delay de-energizing
ON
OFF
10S
OFF delay energizing
ON ON
OFF
ON 10S
OFF delay de-enrgizing

OFF OFF
7-74
FUN 90 P FUN 90 P
WATCHDOG TIMER
WDT WDT
N : The watchdog time. The range of N is 5~120, unit

in 10mS (i.e. 50ms~1.2 sec)
z When execution control "EN" = 1 or "EN↑" ( P instruction) transition from 0 to 1, will set the watchdog time
to Nx10ms. If the scan time exceeds this preset time, PLC will shut down and not execute the application
program.
z The WDT feature is designed mainly as a safety consideration from the system view for the application. For
example, if the CPU of PLC is suddenly damaged, and there is no way to execute the program or refresh I/O,
then after the WDT time expired, the WDT will automatically switch off all the I/Os, so as to ensure safety. In
certain applications, if the scan time is too long, it may cause safety problems or problems of
non-conformance with control requirements. This instruction can used to establish the limitation of the scan
time that you require.
z Once the WDT time has been set it will always be kept, and there is no need to set it again on each scan.
Therefore, in practice this instruction should use the P instruction.
z Default WDT time is 0.25 sec.
z For the operation principles of WDT please refer to the RSWDT(FUN 91) instruction.
7-75
FUN 91 P FUN 91 P
RESET WATCHDOG TIMER
RSWDT RSWDT
This instruction has no operand.
z When execution control "EN" = 1 or "EN↑" ( P instruction), the WDT timer will be reset (i.e. WDT will start
timing again from 0).
z The functions of WDT have already been described in FUN90 (WDT instruction).
The operation principles of watch dog timer are as follows:
The watchdog timer is normally implemented by a hardware one-shot timer (it can not be software,
otherwise if CPU fail, the timer becomes ineffective, and safeguards are quite impossible). "One-shot"
means that after triggered the timer once, the timing value will immediately be reset to 0 and timing will
restart. If WDT has begun timing, and never triggered it again, then the WDT timing value will continue
accumulating until it reach the preset value of N, at that time WDT will be activated, and PLC will be shut
down. If trigger the WDT once every time before the WDT time N has been reached, then WDT will never
be activated. PLC can use this feature to ensure the safety of the system. Each time when PLC enters into
system housekeeping after finished the program scanning and I/O refresh, it will usually trigger WDT once,
so if the system functions normally and scan time does not exceed WDT time then WDT is never activated.
However, if CPU is damaged and unable to trigger WDT, or the scan time is too long, then there will not be
enough time to trigger WDT within the period N, WDT will be activated and will shut off PLC.
z In some applications, when you set the WDT time (FUN90) to desire, the scan time of your program in certain
situations may temporarily exceed the preset time of WDT. This situation can be anticipated and allowed for,
and you naturally do not wish PLC to shut down for this reason. You can use this instruction to trigger WDT
once and avoid the activation of WDT. This is the main purpose of this instruction.
7-76
FUN 92 P FUN 92 P
HARDWARE HIGH SPEED COUNTER CURRENT VALUE (CV) ACCESS
HSCTR HSCTR
CN : Hardware high speed counter number

0: SC0 or HST0
1: SC1 or HST1
2: SC2 or HST2
3: SC3 or HST3
4: STA
z The HSC0～HSC3 counters of FBs-PLC are 4 sets of 32bit high speed counter with the variety counting
modes such as up/down pulse, pulse-direction, AB-phase. All the 4 high speed counters are built in the ASIC
hardware and could perform count, compare, and send interrupt independently without the intervention of the
CPU. In contrast to the software high speed counters HSC4～HSC7, which employ interrupt method to
request for CPU processing, hence if there are many counting signals or the counting frequency is high, the
PLC performance (scanning speed) will be degraded dramatically. Since the current values CV of HSC0～
HSC3 are built in the internal hardware circuits of ASIC, the user control program (ladder diagram) cannot
retrieve them directly from ASIC. Therefore, it must employ this instruction to get the CV value from hardware
HSC and put it into the register which control program can access. The following is the arrangement of CV,
PV in ASIC and their corresponding CV, PV registers of PLC for HSC0~HSC3.
PLC register ASIC

DR4096 CV
CV register H L
HSC0 DR4098 PV HSC0
PV register H L
DR4100 CV
CV register H L
HSC1 DR4102 PV HSC1
PV register H L
DR4104 CV
CV register H L
HSC2 DR4106 PV HSC2
PV register H L
DR4108 CV
CV register H L
HSC3 DR4110 PV HSC3
PV register H L
DR4152 CV
CV register H L
HSTA R4154 PV HSTA
PV register
z When access control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, will gets the CV value of HSC
designated by CN from ASIC and puts into the HSC corresponding CV register (i.e. the CV of HSC0 will be
read and put into DR4096 or the CV of HSC1 will be read and put into DR4100).
z Although the PV within ASIC has a corresponding PV register in CPU, but it is not necessary to access it
(actually it can’t be) for that the PV value within ASIC comes from the PV register in CPU.
z HSTA is a timer, which use 0.1ms as its time base. The content of CV represents elapse time counting at
0.1mS tick.
z For detailed applications, please refer to Chapter 10 “The high speed counter and high speed timer of
FBs-PLC”.
7-77
FUN 93 P HARDWARE HIGH SPEED COUNTER CURRENT VALUE AND PRESET FUN 93 P
HSCTW VALUE WRITING HSCTW
S : The source data for writing
CN : Hardware high speed counter to be written

0: HSC0 or HST1
1: HSC1 or HST2
2: HSC2 or HST3
3: HSC3 or HST4
4: HSTA
D : Write target (0 represents CV, 1 represents PV)
z Please refer first to FUN92 for the relation between the CV or PV value of HSC0～HSC3 and HSTA within
ASIC and their corresponding CV and PV registers in CPU.
z When write control “EN”=1 or “EN↑” ( P instruction) changes from 0→1, it writes the content of CV or PV
register of high speed counter designed by CN of CPU, to the corresponding CV or PV of HSC within ASIC.
z It is quit often to set the PV value for most application program, When the count value reaches the preset
value, the counter will send out interrupt signal immediately. By way of the interrupt service program, you can
implement different kinds of precision counting or positioning control.
z When there is an interrupt of power supply for FBs-PLC, the values of current value registers CV of HSC0～
HSC3 within ASIC will be read out and wrote into the HSC0～HSC3 CV registers (with power retentive
function) of CPU automatically. When power comes up, these CV values will be restored to ASIC. However,
if your application demands that when power is on, the values should be cleared to 0 or begin counting from a
certain value, then you have to use this instruction to write in the CV value for HSC in ASIC.
z When write a non-zero value into the PV register of HSTA will cause the HSTAI interrupt subroutine to be
executed for every PV×0.1ms.
z For detailed applications, please refer Chapter 10 “The high speed counter and high speed timer of
FBs-PLC”.
z As the program in the left diagram, when M0 changes

from 0→1, it clears the current value of HSC0 to 0,
93D.HSCTW
M0 and writes into ASIC hardware through FUN93.
EN S : 0
CN : HSC0
D : CV
M0 92 z When M0 is 0, it reads out the current counting value.

EN HSCTR HSC0
z When M1 changes from 0 →1, it moves DR500 to
93D.HSCTW DR4098, and writes the preset value into ASIC
M1 hardware through FUN93.
EN S : R500
CN : HSC0 z Whenever the current value equals to the DR500,
D : PV The HSC0I interrupt sub program will be executed.
7-78
FUN 94 FUN 94
ASCII WRITE
ASCWR ASCWR
Ladder symbol
94D.ASCWR MD: Output mode
Output control EN MD : ACT Acting =0, output to communication port1.
S : others, reserved for future usage.
Pause control PAU Pt : ERR Error S : Starting register of file data.
Pt : Starting working register for this instruction
instance. It taken up 8 registers and can’t
Abort output ABT DN Output completed
be reused in other part of program.

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
MD ○
S ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Pt ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When MD=0 and output control “EN↑” changes from 0→1, it transmits the ASCII data which starting from S
to the communication port 1 (Port1), until reach end of file.
z S file data can be edited with the programming software PROLADDER or WinProladder (please refer to the
explanation of chapter 15 “ASCII function application”.). If necessary the user can also edit the ASCII file
directly by change the value of data registers. However, the edited data must be follow the ASCII file format
(the details described in chapter 15), otherwise, this instruction will halt the transmission and set the error flag
“ERR” to 1. If the entire file is correctly and successfully transmitted, then the output is completed and “DN”
is set to 1.
z The control input of this instruction is of positive edge triggered. Once “EN↑” changes from 0→1 then this
instruction starts the execution, until finished the transmission of the entire file then the execution is completed.
During the transmission, the action flag “ACT” will be kept at 1 all the time. Only when output pause, error, or
abort occurs, will it change back to 0.
z This instruction can be repeatedly used, but only one will be executed (transmit data) at any certain time. It is
the obligation of user to make sure the right execution sequence.
z While this instruction is in execution, if the pause “PAU” is 1, this instruction will pause the transmission of file
data. It will resume transmission when the pause “PAU” backs to 0.
z While this instruction is in execution, if the abort “ABT” is 1, this instruction will abandon the transmission of
file data, and then it is able to take next instruction for execution.
z or detail applications, please refer to chapter 14 “The Application of ASCII file output function”.
7-79
FUN 94 FUN 94
ASCII WRITE
ASCWR ASCWR
z Interface signals:
M1927: This signal is control by CPU, it is applied in ASCWR MD:0
: ON, it represents that the RTS (connect to the CTS of PLC) of the printer is “False”.
I.e. the printer is not ready or abnormal.
: OFF, it represents that the RTS of the Printer is “True”; Printer is Ready.
Note: Using the M1927 associates with timer can detect if the printer is abnormal or not.
R4158: The setting of communication parameters (refer to section 11.7.2)
7-80
FUN 95 FUN 95
RAMP FUNCTION FOR D/A OUTPUT
RAMP RAMP
Tn : Timer for ramp function

PV : Preset value of ramp timer (the unit is 0.01 second)
or the increment value of every 0.01 second
SL : Lower limit value
(ramp floor value).
SU : Upper limit value
(ramp ceiling value).
D : Register storing current ramping value.
D+1 : Working register
SU, SL could be positive or negative value when incorporate
with AO module application.

16-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
rand WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095
Tn ○
PV ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
SL ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
SU ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○ ○* ○
Description
z Tn must be a 0.01 sec time base timer and never used in other part of program.
z PV is the preset value of ramp timer. Its unit is 10ms (0.01 second).
z When input control “EN↑” changes from 0→1, it first reset the timer Tn to 0.
When “U/D”=1 it will load the value of SL to register D. And when M1974 = 0 it will be increased by SU−SL /
PV every 0.01 sec or when M1974 = 1 it will increase by PV every 0.01 sec. When the D value reaches the
SU value the output “ASU” =1.
When “U/D”=0 it will load the value of SU to register D. When M1974 = 0 it will be decreased by SU−SL / PV
every 0.01 sec or when M1974 = 1 it will be decreased by PV every 0.01 sec. When the D value reaches the
SL value the output “ASL” =1.
z The ramping direction(U/D) is determined at the time when input control “EN↑” changes from 0→1. After the
output D start to ramp, the change of U/D is no effect.
z If it is required to pause the ramping action, it must let the input control “PAU” = 1; when “PAU”=0, and the
ramping action is not completed, it will continue to complete the ramping action.
z The value of SU must be larger than SL, otherwise the ramp function will not be performed, and the output
“ERR” will set to 1.
z This instruction use the register D to store the output ramping value; if the application use the D/A module to
send the speed command, then speed command can be derived from the RAMP function to get a more
smooth movement.
z In addition to use register D to store the ramping value, this instruction also used the register D+1 to act as
internal working register; therefore the other part of program can not use the register D+1.
7-81
FUN 95 FUN 95
RAMP FUNCTION FOR D/A OUTPUT
RAMP RAMP
Program example
95.RAMP
M0 M100
EN Tn : T20 ERR Move the ramping value to AO output register
M1 PV : R100 M101 R3904
PAU SL : R101 ASL
M2 SU : R102 M102
U/D D : R103 ASU
8.MOV
M0
EN S : R103
D : R3904
T20: Ramp timer (timer with 0.01 second time base)

R100: preset value of ramp timer (the unit is 0.01 second, 100 for a second).
R101: Lower limit value.
R102: Upper limit value.
R103: Register storing current ramp value.
R104: Working register
z If M1974=0, When input control M0 changes from 0→1, it first reset the timer T20 to 0. If M2=1, it will load
the R101 (lower limit) value into the R103, and it will increase the output with fixed value (R102-R101 / R100)
for every 0.01 second and stores it to register R103. When the T2 timer going up to the preset value R100,
the output value equals to R102, and the output M102 will set to 1. If M2=0, will load the R102 (upper limit)
value into the R103, and it will decrease the output amount with fixed ratio (R102-R101 / R100) for every 0.01
second and store it to register R103. The T2 timer going up to the preset value R100, the output value equals
to R102, and the output M101 will set to 1.
z M1=1, pause the ramping action.
z The value of R102 must be greater than R101, otherwise the ramp action will not be performed, and the
output M100 will set to 1.
SU
SL
t
PV PV
7-82
Table Instructions
Fun No. Mnemonic Functionality Fun No. Mnemonic Functionality

100 R→T Register to table data move 107 T_FIL Table fill
101 T→R Table to register data move 108 T_SHF Table shift
102 T→T Table to table data move 109 T_ROT Table rotate
103 BT_M Block table move 110 QUEUE Queue
104 T_SWP Block table swap 111 STACK Stack
105 R-T_S Register to table search 112 BKCMP Block compare
106 T-T_C Table to table compare 113 SORT Data Sort
● A table consists of 2 or more consecutive registers (16 or 32 bits). The number of registers that comprise the
table is called the table length (L). The operation object of the table instructions always takes the register as
unit (i.e. 16 or 32 bit data).
● The operation of table instructions are used mostly for data processing such as move, copy, compare, search
etc, between tables and registers, or between tables. These instructions are convenient for application.
● Among the table instructions, most instructions use a pointer to specify which register within a table will be
the target of operation. The pointer for both 16 and 32-bit table instructions will always be a 16-bit register.
The effective range of the pointer is 0 to L-1, which corresponds to registers T0 to TL-1 (a total of L registers).
The table shown below is a schematic diagram for 16-bit and 32-bit tables.
● Among the table operations, shift left/right, rotate left/right operations include a movement direction. The
direction toward the higher register is called left, while the direction toward the lower register is called right, as
shown in the diagram below.
Pointer Pr Pointer Pr
4 ──┐ 2 ──┐
B15 B0 │ B15 B0 │
│ │
T │ T │
(right) │ │
B15 B0 B31 B0 (right)│
(right)│
T0 R0 │ T0 R1 R0 │
T1 R1 │ T1 R3 R2 │
T2 R2 │ T2 R5 R4 │
│ │
Table length
Table length
T3 R3 T3 R7 R6
｛ T4 R4 ←─┘
｛ T4 R9 R8 ←─┘
．．．．．．
．．．．．．
．．．．．．
．．．．．．
TL−1 RL-1 (left) TL−1 R 2L−1 R 2L−2 (left)
16bit table 32bit table
7-83
FUN100 D P FUN100 D P
REGISTER TO TABLE MOVE
R→T R→T
Ladder symbol Rs : Source data , can be constant or register

100DP.R T Td : Source register for destination table
Move control EN Rs : END Move to end
L : Length of destination table
Td :
Pointer increment PAU L : ERR Pointer error Pr : Pointer register
Pr : Rs, Td can associate with V, Z, P0~P9 index

Pointer clear CLR register as indirect addressing

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
Rs ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~2048
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
● When move control "EN" = 1 or "EN↑" ( P instruction) transition from 0 to 1, the contents of the source
register Rs will be written onto the register Tdpr indicated by the pointer Pr within the destination table Td
(length is L). Before executing, this instruction will first check the pointer clear "CLR" input signal. If "CLR" is
1, it will first clear the pointer Pr, and then carry out the move operation. After the move has been completed,
it will then check the Pr value. If the Pr value has already reached L-1 (point to the last register in the table)
then it will only set the move-to-end flag "END" to 1, and finish execution of this instruction. If the Pr value is
less than L-1, then it must again check the pointer increment "INC" input signal. If "INC" is 1, then Pr value
will be also increased. Besides, pointer clear "CLR" is able to operate independently, without being
influenced by other input.
● The effective range of the pointer is 0 to L-1. Beyond this range, the pointer error "ERR" will be set to 1, and
this instruction will not be performed.
z The example at left at the very beginning pointer Pr = 4,

100P.R T
X1 the entire content of table Td is 0, and the Rs value is
EN RS : R 0 END
8888. The diagram below shows the operation results
Td : R 10
INC L : 8 ERR when X1 have the transition of 0→1 twice.
Pr : R 50 z Because INC is 1, Pr will increase by 1 each time the
CLR instruction is executed.
Pr Pr Pr
4 R50 5 R50 6 R50
Td Td Td
0000 R10(T0) 0000 R10 0000 R10
0000 R11(T1) 0000 R11 0000 R11
Rs 0000 R12(T2) X0＝ 0000 R12 X0＝ 0000 R12
R0 8888 0000 R13(T3) (First) 0000 R13 (Second) 0000 R13
0000
0000
R14(T4)
R15(T5)
Ö 8888
0000
R14
R15
Ö 8888
8888
R14
R15
0000 R16(T6) 0000 R16 0000 R16
0000 R17(T7) 0000 R17 0000 R17
Before First time result Second time result
7-84
TABLE TO REGISTER MOVE
T→R T→R
Ladder symbol
Ts : Source table starting register
101DP.T R L : Length of source table
Move control EN Ts : END Move to end
Pr : Pointer register
L : Rd : Destination register
Pointer increment PAU Pr : ERR Pointer error Ts, Rd may combine with V, Z, P0~P9 to
Rd : serve indirect address application
Pointer clear CLR

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ 2~2048
Rd ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When move control "EN" = 1 or "EN↑" ( P instruction) transition from 0 to 1, the value of the register Tspr
specified by pointer Pr within source table Ts (length is L) will be written into the destination register Rd. Before
executing, this instruction will first check the input signal of pointer clear "CLR". If "CLR" is 1, it will first clear Pr
and then carry out the move operation. After completing the move operation, it will then check the value of Pr.
If the Pr value has already reached L-1 (point to the last register in the table), then it sets the move-to-end flag
to 1, and finishes executing of this instruction. If Pr is less than L-1, it check the status of "INC". If "INC" is 1,
then it will increase Pr and finish the execution of this instruction. Besides, pointer clear "CLR" can execute
independently and is not influenced by other inputs.
z The effective range of the pointer is 0 to L-1. Beyond this range the pointer error "ERR" will be set to 1 and this
instruction will not be carried out.
z In the example at left, at the very beginning Pr = 7 and Ts

101P.T R
X0 and Rd are as shown at left in the diagram below. When X0
EN TS : R 0 END
have a transition from 0→1 twice, the results are shown at
L : 9
INC Pr : R 19 ERR right in the diagram below.
Rd : R 20 z At the second time execution, the pointer has already
CLR reached to the end so there will be no increment.
Ts Pr Pr Pr
R0(T0) 1111 7 R19 8 R19 8 R19
R1(T1) 2222
R2(T2) 3333 X0＝ X0＝
R3(T3) 4444 Rd (first) Rd (second) Rd
R4(T4)
R5(T5)
5555
6666
0 0 0 0 R20
Ö 8 8 8 8 R20
Ö 9 9 9 9 R20
R6(T6) 7777 END END END

R7(T7) 8888 0 0 1
R8(T8) 9999
Before execution First time execution Second time execution
7-85
TABLE TO TABLE MOVE
T→T T→T
Ladder symbol Ts : Starting number of source table register

102DP.T T Td : Starting number of destination table
Move control EN Ts : END Move to end register
L : Table (Ts and Td) length
Td :
Pointer increment PAU L : ERR Pointer error Ts, Rd may combine with V, Z, P0~P9 to
Pr : serve indirect address application
Pointer clear CLR

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When move control "EN" = 1 or "EN↑" ( P instruction) have a transition from 0 to 1, the register Tspr pointed
by pointer Pr within the source table will be moved to a register Tdpr, which also pointed by the pointer Pr in the
destination table. Before execution, it will first check the input signal of pointer clear "CLR". If "CLR" is 1, it will
first clear Pr to 0 and then do the move (in this case Ts0→Td0). After the move action has been completed it
will then check the value of pointer Pr. If the Pr value has already reached L-1 (point to the last register on the
table), then it will set the move-to-end flag "END" to 1 and finish executing of this instruction. If the Pr value is
less than L-1, it will check the status of "INC". If "INC" is 1, then the Pr value will be increased by 1 before
execution. Besides, pointer clear "CLR" can execute independently, and will not be influenced by other input.
z The effective range of the pointer is 0 to L-1. Beyond this range, the pointer error flag "ERR" will be set to 1,
and this instruction will not be carried out.
z The diagram at left below is the status before execution.

102P.T T
X0 When X0 from 0→1, the content of R5 in Ts table will copy to
EN TS : R 0 END
R15 and pointer R20 will be increased by 1.
Td : R 10
INC L : 10 ERR
Pr : R 20
CLR
Pr Pr
R20 5 R20 6
Ts Td Td
R0 1111 R10 0000 R10 0000
R1 1111 R11 0000 R11 0000
R2 1111 R12 0000 R12 0000
R3 1111 R13 0000 X0＝ R13 0000
R4 1111 R14 8888 Ö R14 8888
R5 1111 R15 0000 R15 1111
R6 1111 R16 0000 R16 0000
R7 1111 R17 0000 R17 0000
R8 1111 R18 0000 R18 0000
R9 1111 R19 0000 R19 0000
Before execution result
7-86
BLOCK TABLE MOVE
BT_M BT_M
Ts :Starting register for source table
Td : Starting register for destination table
L: Lengths of source and destination tables
Ts, Rd may combine with V, Z, P0~P9 to serve indire

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
z In this instruction the source table and destination table are the same length. When this instruction was
executed all the data in the Ts table is completely copied to Td. No pointer is involved in this instruction.
z When move control "EN" = 1 or "EN↑" ( P instruction) have a transition from 0 to 1, all the data from source
table Ts (length L) is copied to the destination table Td, which is the same length.
z One table is completely copied every time this instruction is executed, so if the table length is long, it will be
very time consuming. In practice, P modifier should be used to avoid time waste caused by each scan
repeating the same movement action.
z The diagram at left below is the status before execution. When

103P.BT_M
X0 X0 from 0→1, the content of R0~R9 in Ts table will copy to
EN TS : R 0 R10~R19.
Td : R 10
L : 10
Ts Td Td
R0 0000 ──→ R10 0000 R10 0000
R1 1111 ──→ R11 0000 R11 1111
R2 2222 ──→ R12 0000 R12 2222
R3 3333 ──→ R13 0000 X0＝ R13 3333
R4 4444 ──→ R14 0000 Ö R14 4444
R5 5555 ──→ R15 0000 R15 5555
R6 6666 ──→ R16 0000 R16 6666
R7 7777 ──→ R17 0000 R17 7777
R8 8888 ──→ R18 0000 R18 8888
R9 9999 ──→ R19 0000 R19 9999
Execute
Before executed result
7-87
BLOCK TABLE SWAP
T_SWP T_SWP
Ta : Starting register of Table a

Tb : Starting register of Table b
L : Lengths of Table a and b
Ts, Rd may combine with V, Z, P0~P9 to serve
Range WY WM WS TMR CTR HR OR SR ROR DR K XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 256 P0~P9
Ta ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
Tb ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
z This instruction swaps the contents of Tables a and b, so the table must be the same length, and the registers
in the table must of write able. Since a complete swap is done with each time the instruction is executed, no
pointer is needed.
z When move control "EN" = 1 or "EN↑" ( P instruction) have a transition from 0 to 1, the contents of Table a
and Table b will be completely swapped.
z This instruction will swap all the registers specified in L each time the instruction is executed, so if the table
length is big, it will be very time consuming, therefor P instruction should be used.
z The diagram at left below is the status before execution.

104P.T_SWP When X0 from 0→1, the contents of R0~R9 in Ts table will
X0
EN TS : R 0 swap with R10~R19.
Td : R 10
L : 10
Ta Tb Ta Tb
R0 0000 R10 1111 R0 1111 R10 0000
R1 0000 R11 1111 R1 1111 R11 0000
R2 0000 R12 1111 R2 1111 R12 0000
R3 0000 R13 1111 X0＝ R3 1111 R13 0000
R4 0000 R14 1111 Ö R4 1111 R14 0000
R5 0000 R15 1111 R5 1111 R15 0000
R6 0000 R16 1111 R6 1111 R16 0000
R7 0000 R17 1111 R7 1111 R17 0000
R8 0000 R18 1111 R8 1111 R18 0000
R9 0000 R19 1111 R9 1111 R19 0000
Before executed After executed
7-88
REGISTER TO TABLE SEARCH
R-T_S R-T_S
Rs : Data to search, It can be a constant

or a register
Ts : Starting register of table being
searched
L : Label length
Pr : Pointer of table
Rs, Ts may combine with V, Z, P0~P9 to

16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
Rs ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ 2~256
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When search control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will search from the first
register of Table Ts (when "FHD" = 1 or Pr value has reached L-1), or from the next register (Tspr + 1) pointed
by the pointer within the table ("FHD" = 0, while Pr value is less than L-1) to find the first data different with
Rs(when D/S = 1) or find the first data the same with Rs (when D/S = 0). If it find a data match the condition it
will immediately stop the search action, and the pointer Pr will point to that data and found objective flag "FND"
will set to 1. When the searching has searched to the last register of the table, the execution of the instruction
will stop, whether it was found or not. In that case the search-to-end flag "END" will be set to 1 and the Pr value
will stop at L-1. When this instruction next time is executed, Pr will automatically return to the head of the table
(Pr = 0) before the search begin.
z The effective range of Pr is 0 to L-1. If the value exceeds this range then the pointer error flag "ERR" will
change to 1, and this instruction will not be carried out.
105P.R-T_S
X0 z The instruction at left is searching the table for a register with the
EN RS : 5555 FND
value 5555 (because D/S = 0, it is searching for same value).
TS : R 0 Before execution, the pointer point to R2, but the starting point of
FHD L : 10 END the search is Pr + 1 (i.e. it starts from R3). After X0 has transition
Pr : R 20 from 0→1 3 times, the results of each search may be obtained
D/S ERR as shown in the diagram below.
Pr Ts Pr FND END
R20 2 R0 5555 cX0＝ R20 6 1 0
R1 0000 (First)
R2 5555
Start
Rs R3 2222← Pr FND END
point
5555 R4 3333 dX0＝ R20 9 0 1
R5 4444 (Second)
R6 5555
R7 6666 Pr FND END
R8 7777 eX0＝ R20 0 1 0
R9 8888 (Third)
Before execution After execution
7-89
TABLE TO TABLE COMPARE
T-T_C T-T_C
Ta : Starting register of Table a

Tb : Starting register of Table b
L : Lengths of Table
Pr : Pointer
Ta, Tb may combine with V, Z, P0~P9 to

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ta ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Tb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When comparison control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, then starting from the
first register in the tables Ta and Tb (when "FHD" = 1 or Pr value has reached L-1) or starting from the next
pair of registers (Tapr+1 and Tbpr+1) pointed by Pr ("FHD" = 0, while Pr is less than L-1), this instruction will
search for pairs of registers with different values (when "D/S" = 1) or the same value (when "D/S" = 0). When
search found (either different or the same), it will immediately stop the search and the pointer Pr will point to
the register pairs met the search criteria. The found flag "FND" will be set to 1. When it has searched to the last
register of the table, the instruction will stop executing. whether it found or not. The compare-to-end flag "END"
will be set to 1, and the pointer value will stop at L-1. When this instruction is executed next time, Pr will
automatically return to the head of the table to begin the search.
z The effective range of Pr is 0 to L-1. The Pr value should not changed by other programs during the operation.
As this will affect the result of the search. If the Pr value not in the effective range, the pointer error flag "ERR"
will be set to 1, and this instruction will not be carried out.
z The instruction at left starts from the register next to the register
106P.T-T_C pointed by the pointer (because "FHD" is 0) to search for register
X0
EN Ta : R 0 FND pairs with different data (because "D/S" is 1) within the 2 tables.
Tb : R 11 At the very beginning, Pr points to Ta1 and Tb1. There are 3
FHD L : 10 END different pairs of data at the position 1,3,6 of the table.
Pr : R 10
However, it does not compare from the beginning, and this
ERR instruction will start searching from position 3 downwards. After
D/S
X0 has changed 3 times from 0 to 1, the results are shown in the
diagram below.
Pr
R10 1
Ta Tb Pr F E
R0 0000 R11 0000 cX0＝ R10 3 1 0
R1 1111 R12 0000
(First)
R2 2222 R13 2222←
Start
R3 3333 R14 1234 Pr F E
point
R4 4444 R15 4444 dX0＝ R10 6 1 0
R5 5555 R16 5555 (Second)
R6 6666 R17 0000
R7 7777 R18 7777 Pr F E
R8 8888 R19 8888 eX0＝ R10 9 0 1
R9 9999 R20 9999 (Third)
7-90
TABLE FILL
T_FIL T_FIL
Rs : Source data to fill, can be a constant or a register
Td : Starting register of destination table
L :Table length
Rs, Td may combine with V, Z, P0~P9 to serve indirect

address application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~256
z When fill control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, the Rs data will be filled into all
the registers of the table Td.
z This instruction is mainly used for clearing the table (fill 0) or unifying the table (filling in the same values). It
should be used with the P instruction.
107P.T_FIL
X0 z The instruction at left will fill 5555 into the whole table
EN TS : 5555 Td. The results are as shown in the diagram below.
Td : R 0
L : 10
Td Td
R0 1547 R0 5555
R1 2314 R1 5555
R2 7725 R2 5555
Rs R3 0013 X0＝ R3 5555
5555 R4 5247 Ö R4 5555
R5 1925 R5 5555
R6 6744 R6 5555
R7 5319 R7 5555
R8 9788 R8 5555
R9 2796 R9 5555
7-91
TABLE SHIFT
T_SHF T_SHF
Ladder symbol IW : Data to fill the room after shift operation, can be a
108DP.T_SF constant or a register
Shift control EN IW : Ts : Source table
Ts : Td : Destination table storing shift results
Left/Right direction L/R Td : L : Lengths of tables Ts and Td
L : OW : Register to accept the shifted out data
OW : Ts, Td may combine with V, Z, P0~P9 to serve indirect
address application
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
IW ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~256
OW ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When shift control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, all the data from table Ts will
be taken out and shifted one position to the left (when "L/R" = 1) or to the right (when "L/R" = 0). The room
created by the shift operation will be filled by IW and the results will be written into table Td. The data shifted
out will be written into OW.
z In the program at left, Ts and Td is the same table.

108P.T_SHF
X0 Therefore, the table shifts itself and then writes back to
EN IW : R 10 itself (the table must be writ able). It first perform a shift left
X1 TS : R 0 operation (let X1 = 1, and X0 go from 0→1) then perform a
L/R Td : R 0 shift to right operation (let X1 = 0, and makes X0 go from 0
L : →1). The result are shown at right in the diagram below.
10
OW : R 11
Ts(Td) (Shift left) (Shift right)

Td(Ts) Td(Ts)
R0 0000 R0 1234 R0 0000
(Shift left) R1 1111 R1 0000 R1 1111
R2 2222 R2 1111 R2 2222
R3 3333 OW R3 2222 R3 3333
R10 1 2 3 4 R4 4444 R11 ×××× R4 3333 R4 4444
R5 5555 R5 4444 R5 5555
R6 6666 R6 5555 R6 6666
R7 7777 R7 6666 R7 7777
R8 8888 R8 7777 R8 8888
R9 9999 (Shift left) R9 8888 R9 1234
OW OW
Dotted line is the path for shift right R11 9999 R11 1234
Before execution cFirst time dSecond time
7-92
TABLE ROTATE
T_ROT T_ROT
Ts : Source table for rotate

Td : Destination table storing results of rotation
L : Lengths of table
Ts, Td may combine with V, Z, P0~P9 to serve indirect
address application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Td ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
z When rotation control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, the data from the table of
Ts will be rotated 1 position to the left (when "L/R" = 1)or 1 position to the right (when "L/R" = 0). The results of
the rotation will then be written onto table Td.
109P.T_ROT z In the program at left, Ts and Td is the same table. The

X0
EN TS : R 0 table after rotation will write back to itself. It first perform
one left rotation (let X1 = 1, and X0 go from 0→1), and
X1 Td : R 0
then performs one right rotation (let X1 = 0, and X0 go
L/R L : 10
from 0→1). The results are shown at right in the diagram
below.
Rotate left Rotate right (Rotate left) (Rotate right)

Ts(Td)
Td(Ts) Td(Ts)
R0 0 0 0 0 (right) R0 9999 R0 0000
R1 1111 R1 0000 R1 1111
R2 2222 R2 1111 R2 2222
R3 3333 R3 2222 R3 3333
R4 4444 R4 3333 R4 4444
R5 5555 R5 4444 R5 5555
R6 6666 R6 5555 R6 6666
R7 7777 R7 6666 R7 7777
R8 8888 R8 7777 R8 8888
R9 9 9 9 9 (left) R9 8888 R9 9999
Before execution cFirst time dSecond time
7-93
QUEUE
QUEUE QUEUE
IW : Data pushed into queue, can be a constant

or a register
QU : Starting register of queue
L : Size of queue
OW : Register accepting data popped out
from queue
QU may combine with V, Z, P0~P9 to serve
16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
+/- number
IW ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
QU ○ ○ ○ ○ ○ ○ ○ ○ ○* ○ ○
L ○ ○* ○ 2~256
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
OW ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z Queue is also a kind of table. It is different from ordinary table in that its queue register numbers go from 1 to L
and not from 0 to L-1. In other words QU1~QUL respectively correspond to pointers Pr = 1 to L, and Pr = 0 is
used to show that the queue is empty.
z Queue is a first in first out (FIFO) device, i.e. - the data that first pushed into the queue will be the first to pop
out from the queue. A queue is comprised of L consecutive 16 or 32 bit registers ( D instruction) starting from
the QU register, as in the diagram below:
Pr
4
IW QU
g5555 QU1 f4444
QU2 e3333 Push
push(I/O=1) QU3 d2222 down
QU4 c1111 OW
1.IW always push into QU5 ××××
QU1
……
2.Pr＋1→Pr Pop out(I/O=0)
c ～ gis the sequence number of 2. QUpr →OW

operation QUL 3. Pr－1→Pr
z When execution control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, the status of in/out
control "I/O" determines whether the IW data will be pushed into the queue (when "I/O" = 1) or be popped out
and transferred to OW (when "I/O" = 0). As shown in the diagram above, the IW data will always be pushed
into the first (QU1) register of the queue. After it has been pushed in, Pr will immediately be increased by 1, so
that the pointer can always point to the first data that was pushed into the queue. When it is popped out, the
data pointed by Pr will be transferred directly to OW. Pr will be reduced by 1, so that it still point to the first data
remained in the queue.
7-94
QUEUE
QUEUE QUEUE
z If no data has yet been pushed into the queue or the pushed in data has already been popped out (Pr = 0),
then the queue empty flag will be set to 1. In this case, even if there is further popping out action, this
instruction will not be executed. If data is only pushed in and not popped out, or pushed in is more than that
popped out, then the queue finally becomes full (pointer Pr indicates the QUL position), and the queue full flag
is changed to 1. In this case, if there is more pushing in action, this instruction will not execute. The pointer for
this instruction is used during access of the queue, to indicate the data that was pushed in the earliest. Other
programs should not be allowed to change it, or else an operation error will be created. If there is a specific
application, which requires the setting of a Pr value, then its permissible range is 0 to L (0 means empty, and 1
to L respectively correspond to QU1 to QUL). Beyond this range, the pointer error flag "ERR" will be set as 1,
z The program at left assumes the queue content is the

110P.QUEUE
X0 same with the queue at preceding page. It will first
EN IW : R 0 EPT perform queue push operation , and then perform pop
X1 QU : R 2 out action. The results are shown below. Under any
I/O L : 10 FUL circumstance, Pr always point to the first (oldest) data
Pr : R 1 that was remained in queue.
OW : R 20 ERR
Pr Pr
5 4
QU QU
QU1 5555 R2 QU1 5555 R2
QU2 4444 R3 QU2 4444 R3
QU3 3333 R4 QU3 3333 R4
QU4 2222 R5 OW QU4 2222 R5 OW
QU5 1111 R6 ×××× R20 QU5 R6 1 1 1 1 R20
QU6 R7 ↑ QU6 R7
QU7 R8 OW unchanged QU7 R8
QU8 R9 QU8 R9
QU9 R10 QU9 R10
QU10 R11 QU10 R11
After push in (X1=1，X0 from 0→1) After pop off (X1=0，X0 from 0→1)
7-95
STACK
STACK STACK
IW : Data pushed into stack, can be a constant

or a register
ST : Starting register of stack
L : Size of stack
OW : Register accepting data popped out from
stack
ST may combine with V, Z, P0~P9 to serve

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
IW ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
ST ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ 2~256
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
OW ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z Like queue, stack is also a kind of table. The nature of its pointer is exactly the same as with queue, i.e. Pr = 1
to L, which corresponds to ST1 to STL, and when Pr = 0 the stack is empty.
z Stack is the opposite of queue, being a last in first out (LIFO) device. This means that the data that was most
recently pushed into the stack will be the first to be popped out of the stack. The stack is comprised of L
consecutive 16 or 32-bit ( D instruction) registers starting from ST, as shown in the following diagram:
Pr
4
c～g is the sequence
number of operation ST
ST1 c1111 ← Bottom of stack
ST2 d2222
ST3 e3333
IW ST4 f4444 OW
g5555 ST5 ××××
push(I/O=1) push pop(I/O=0)

1.Pr＋1→Pr 1.STpr→OW
2.IW→STpr STL 2.Pr－1→Pr
z When execution control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, the status of in/out
control "I/O" determines whether the IW data will be pushed into the stack (when "I/O" = 1), or the data pointed
by Pr within the stack (the data most recently pushed into the stack) will be moved out and transferred to OW
(when "I/O" = 0). Note that the data pushed in is stacking, so before pushed in, Pr will increased by 1 to point
to the top of the stack then the data will be pushed in. When it is popped out, the data pointed by pointer Pr
(the most recently pushed in data) will be transferred to OW. After then Pr will decreased by 1. Under any
circumstances, the pointer Pr will always point to the data that was pushed into the stack most recently.
7-96
STACK
STACK STACK
z When no data has yet been pushed into the stack or the pushed in data has already been popped out (Pr = 0),
the stack empty flag "EPT" will set to 1. In this case any further pop up actions, will be ignored. If more data is
pushed than popped out, sooner or latter the stack will be full (pointer Pr points to STL position), and the stack
full flag "FUL" will set to 1. In this case any further push actions, will be ignored. As with queue, the stack
pointer in normal case should not be changed by other instructions. If there is a special application which
requires to set the Pr value, then its effective range is 0 to L (0 means empty, 1 to L respectively correspond to
ST1 to STL). Beyond this range, the pointer error flag "ERR" will set to 1, and the instruction will not be carried
out.
111P.STACK z The program at left assumes that the initial content of the
X0
EN IW : R 0 EPT stack is just as in the diagram of a stack on the
ST : R 2 preceding page. The operation illustrated in this example
X1
L : 10 FUL
is to push a data and than pop it from stack. The results
I/O
are shown below. Under any circumstances, Pr always
Pr : R 1
point to the data that was most recently pushed into the
OW : R 20 ERR
stack.
Pr Pr
5 R1 4
ST QU
ST1 1111 R2 ST1 1111 R2
ST2 2222 R3 ST2 2222 R3
ST3 3333 R4 ST3 3333 R4
ST4 4444 R5 OW ST4 4444 R5 OW
ST5 5555 R6 ×××× R20 ST5 R6 5 5 5 5 R20
ST6 R7 ↑ ST6 R7
ST7 R8 OW unchanged ST7 R8
ST8 R9 ST8 R9
ST9 R10 ST9 R10
ST10 R11 ST10 R11
After push(X1=1，X0 from 0→1) After pop up(X1=0，X0 from 0→1)
7-97
BLOCK COMPARE（DRUM）
BKCMP BKCMP
Rs : Data for compare, can be a constant or a

register
Ts : Starting register block storing upper and
lower limit
L : Number of pairs of upper and lower limits
D : Starting relay storing results of
comparison
Range Y M S WX WY WM WS TMR CTR HR IR OR SR ROR DR K

Y0 M0 S0 WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 16/32-bit
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ +/-
rand Y255 M999 S999 WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 number
Rs ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Ts ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ 1~256
D ○ ○ ○
z When comparison control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, comparisons will be
perform one by one between the contents of Rs and the upper and lower limits form by L pairs of 16 or 32-bit
( D modifier) registers starting from the Ts register (starting from T0 each adjoining 2 register units form a pair
of upper and lower limits). If the value of Rs falls within the range of the pair, then the bit within the comparison
results relay D which corresponds to that pair will be set to 1. Otherwise it will be set as 0 until comparison of
all the L pairs of upper and lower limits is completed.
z When M1975=0, if there is any pair where the upper limit value is less than the lower limit value, then the limit
error flag "ERR" will be set to 1, and the comparison output for that pair will be 0.
z When M1975=1, there is no restriction on the relation of upper limit and lower limit, this can apply for 360°rotary
electronic drum switch application.
Upper limit Lower limit Compare Compared Result

value
0 TS1 TS0 D0
1 TS3 TS2 D1
    Rs  
L−1 TS2L−1 TS2L−2 DL−1
z Actually this instruction is a drum switch, which can be used in interrupt program and when incorporate with
immediate I/O instruction (IMDIO) can achieve an accurate electronic drum.
X0 112.BKCMP
z In this program, C0 represents the rotation angle (Rs) of
EN RS : C 0 ERR
a drum shaft. The block compare instruction performs a
Ts : R 10 comparison between Rs and the 4 pairs (L = 4) of upper
L : 4 and lower limits, R10,R11, R12,R13, R14,R15 and
D : Y 5 R16,R17. The comparison results can be obtained from
X1 the four drum output points Y5 to Y8.
CK C 0 z The input point X1 is a rotation angle detector mounted
C0 PV : 360 on the drum shaft. With each one degree rotation of the
CLR drum shaft angle, X1 produces a pulse. When the drum
shaft rotates a full cycle, X1 produces 360 pulses.
7-98
BLOCK COMPARE（DRUM）
BKCMP BKCMP
z The program in the diagram above coordinates a rotary encoder or other rotating angle detection device
(directly connect to a rotating mechanism), which can form a mechanical device equivalent to the mechanical
structure of an actual drum (see mechanism shown within dotted line in diagram below). While the upper and
lower limits are being adjusted, you can change at will the range of the activated angle of the drum. This
cannot be done with the traditional drum mechanism.
Equivalent mechanical drum emulated by above program
Rotary encoder
Rotary encoder 200
200
180
180 180
180
Rotating
Rotating
140
140
220
220 mechanism
． mechanism
80
80
90
90 80
80
60
60
320
320 40
40 0
0
0
Limit
Limit swsw
X1
X1
Y7 Y8
Y5 Y6
Y6
40 140
Y5
80 180
Y6
60
Y7
80 200
Y8
C0
0° 40° 80° 120° 160° 200° 240° 280° 320° 360°
7-99
DATA SORTING
SO RT SO RT
S : Starting register of source registers to sort

D : Starting register of destination registers to store the
data after sorted
L : Total register for sorting
Range TMR CTR HR IR OR SR ROR DR K

T0 C0 R0 R3840 R3904 R3968 R5000 D0 2
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 127
S ○ ○ ○ ○ ○ ○ ○ ○
D ○ ○* ○
L ○ ○ ○ ○
● When sort control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, will sort the registers with
ascending order (if A/D = 1) or descending order (if A/D = 0) and put the sorted result to the registers starting
by D register.
● The valid data length of sort operation is between 2 and 127, other length will set the “ERR” to 1 and the sort
operation will not perform.
113DP.SORT
X0
EN S : R 0 ˙The example at left sorts the table comprised of R0~R9
D : R 10 and stores the sorted data to the table locate at
A/D L : 10 R10~R19.
S D
R0 1547 R10 0013
R1 2314 R11 1547
R2 7725 R12 1925
R3 0013 R13 2314
R4 5247 X0＝ R14 2796
R5 1925 Ö R15 5247
R6 6744 R16 5319
R7 5319 R17 6744
R8 9788 R18 7725
R9 2796 R19 9788
Before After
7-100
FUN114 P FUN114 P
ZONE WRITE
Z-W R Z -W R
D : Starting address of being set or reset

N : Quantity of being set oe reset, 1~511
D 、 N operand can combine V 、 Z 、 P0~P9 for index
addressing while word operation
Y M S WY WM WS TMR CTR HR IR OR SR ROR DR K XR

Range
Y0 M0 S0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0 V、Z
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Operand
Y255 M1911 S99 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095 P0～P9
D ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
N ○ ○ ○ 1-511 ○
● When operation control "EN"=1 or "EN↑" （ P instruction）changes from 0→1, it will perform the write
operation according to the input status of write selection, the specified area of registers or bits will all be reset
to 0 ("1/0"=0) or set to 1("1/0"=1).
114.Z-WR
X0
EN D : R0 ERR
N : 10
I/O
˙Above example, registers R0~R9 will be reset to 0 while X0=1.
114.Z-WR
X0
EN D : M5 ERR
N : 7
I/O
˙Above example, bits M5~M11 will be reset to 0 while X0=1.
7-101
Matrix Instructions
Fun No. Mnemonic Functionality Fun No. Mnemonic Functionality

120 MAND Matrix AND 126 MBRD Matrix Bit Read
121 MOR Matrix OR 127 MBWR Matrix Bit Write
122 MXOR Matrix XOR 128 MBSHF Matrix Bit Shift
123 MXNR Matrix XNOR 129 MBROT Matrix Bit Rotate
124 MINV Matrix Inverse 130 MBCNT Matrix Bit Count
125 MCMP Matrix Compare
● A matrix is comprised of 2 or more consecutive 16-bit registers. The number of registers comprising the
matrix is called the matrix length (L). One matrix altogether has L×16 bits (points), and the basic unit of the
object for each operation is bit.
● The matrix instructions treats the 16×L matrix bits as a set of series points( denoted by M0 to M16L-1).
Whether the matrix is formed by register or not, the operation object is the bit not numerical value.
● Matrix instructions are used mostly for discrete status processing such as moving, copying, comparing,
searching, etc, of single point to multipoint (matrix), or multipoint-to-multipoint. These instructions are
convenient, important for application.
● Among the matrix instructions, most instruction need to use a 16-bit register as a pointer to points a specific
point within the matrix. This register is known as the matrix pointer (Pr). Its effective range is 0 to 16L-1,
which corresponds respectively to the bits M0 to M16L-1 within the matrix.
● Among the matrix operations, there are shift left/right, rotate left/right operations. We define the movement
toward higher bit is left direction, while the movement toward lower bit is right direction, as shown in the
diagram below.
←─ Width is 16 bit ─→
Pr
40 M15 M M0 (right)
M40
↓ ↓
R0
R1 ↑
R2 1
R3
│
R4 │
Pr=40, point y
y
to M40, y
length
y
y
y L
y
y
y
y
y │
y
y y │
y
y ↓
RL−1
↑
M16L−1(left)
7-102
FUN120 P FUN120 P
MATRIX AND
MAND MAND
Ladder symbol
120P.MAND Ma : Starting register of source matrix a
Operation control EN Ma : Mb : Starting register of source matrix b
Mb : Md : Starting register of destination matrix
Md : L : Length of matrix (Ma, Mb and Md)
L : Ma, Mb, Md may combine with V, Z, P0~P9 to serve


Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) has a Ma Mb Md

transition from 0 to 1, this instruction will perform a logic AND (only
if 2 bits are 1 will the result be 1, otherwise it will be 0)operation
between two source matrixes with a length of L, Ma and Mb. The
result will then be stored in the destination matrix Md, which is also L
the same length (the AND operation is done by bits with the same
bit numbers). For example, if Ma0 = 0, Mb0 = 1, then Md0 = 0; if
Ma1 = 1, Mb1 = 1, then Md1 = 1; etc, right up until AND reaches
Ma16L-1 and Mb16L-1.
AND
z In the program at left, when X0 goes from 0→1, then

120P.MAND matrix Ma, comprised by R0 to R4, and matrix Mb,
X0
EN Ma : R 0 comprised by R10 to R14, will do an AND operation. The
Mb : R 10 results will be stored back in matrix Md, comprised by
Md : R 20
R20 to R24. The result is shown at right in the diagram
L : 5
below.
Ma15 Ma0 Mb15 Mb0 Md15 Md0

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ ↑ ↑
7-103
FUN121 P FUN121 P
MATRIX OR
MOR MOR
Ma : Starting register of source matrix a

Mb : Starting register of source matrix b
Md : Starting register of destination matrix
L : Length of matrix (Ma, Mb and Md)
Ma, Mb, Md may combine with V, Z, P0~P9 to serve

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
Ma Mb Md
z When operation control "EN" = 1 or "EN↑" ( P instruction) has a
transition from 0 to 1, this instruction will perform a logic OR(If any
2 of the bits are 1, then the result will be 1, and only if both are 0
will the result be 0) operation between 2 source matrixes with a
length of L, Ma and Mb. The result will then be stored in the L
destination matrix Md, which is also the same length (the OR
operation is done by bits with the same bit numbers). For example,
if Ma0 = 0, Mb0 = 1, then Md0 = 1; if Ma1 = 0, Mb1 = 0, then Md1 =
0; etc, right up until OR reaches Ma16L-1 and Mb16L-1.
OR
121P.MOR z In the program at left, when X0 goes from 0→1, then matrix
X0
EN Ma : R 0 Ma, comprised by R0 to R4, and matrix Mb, comprised by
R10 to R14, will do an OR operation. The results will then
Mb : R 10
be stored into the destination matrix Md, comprised by R10
Md : R 10
to R14. In this example, Mb and Md is the same matrix, so
L : 5
after operation the source matrix Mb will replaced by the
new value. The result is shown at right in the diagram
below.

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ ↑ ↑
7-104
FUN122 P FUN122 P
MATRIX EXCLUSIVE OR（XOR）
MXOR MXOR
Ladder symbol
122P.MXOR
Operation control EN Ma :
Mb :
Md :
Ma, Mb, Md may combine with V, Z, P0~P9 to serve
L :

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
Ma Mb Md

transition from 0 to 1, this instruction will performs a logic XOR (if
the 2 bits are different, then the result will be 1, otherwise it will be
0)between 2 source matrixes with a length of L, Ma and Mb. The L
result will then be stored back into the destination matrix Md, which
also has a length of L. For example the XOR operation is done by
bits with the same bit numbers - for example, if Ma0 = 0, Mb0 = 1,
then Md0 = 1; if Ma1 = 1, Mb1 = 1, then Md1 = 0; etc, right up until
XOR reaches Ma16L-1 and Mb16L-1.
XOR
122P.MXOR z In the program at left, when X0 goes from 0→1, will

X0
EN Ma : R 0 perform a XOR operation between matrix Ma, comprised
by R0 to R4, and matrix Mb, comprised by R10 to R14.
Mb : R 10
The results will then be stored in destination matrix Md,
Md : R 20
comprised by R20 to R24. The results are shown at right
L : 5
in the diagram below.

↓ Ma ↓ ↓ Mb ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
↑ ↑ ↑ ↑ ↑ ↑
7-105
FUN123 P FUN123 P
MATRIX EXCLUSIVE NOR（XNR）
MXNR MXNR
Ladder symbol
123P.MXNR
Operation control EN Ma :
Mb :
Md :
Ma, Mb, Md may combine with V, Z,P0~P9 to serve
L : indirect address application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
Ma Mb Md
transition from 0 to 1, will perform a logic XNR operation (if the 2
bits are the same, then the result will be 1, otherwise it will be
0)between 2 source matrixes with a length of L, Ma and Mb. The
results will then be stored into the destination matrix Md, which L
also has the same length (the XNR operation is done by bits with
the same bit numbers). For example, if Ma0 = 0, Mb0 = 1, then Md0
= 0; Ma1 = 0, Mb1 = 0, then Md1 = 1; etc, right up until XNR
reaches Ma16L-1 and Mb16L-1.
XNR
X0
123P.MXNR z When operation control "EN" = 1 or "EN↑" ( P instruction)
EN Ma : R 0 goes from 0 to 1, will perform a XNR operation between Ma
Mb : R 10 matrix comprised by R0~R9 and Mb matrix comprised by
Md : R 10 R10~R19. The results will then be stored into the
L : 5 destination matrix Md comprised by R10~R19. The results
are shown at right in the diagram below.
Ma15 Ma Mb15 Mb0 Md15 Md0

Ma Mb Md
0
↓ ↓ ↓ ↓ ↓ ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R23 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
↑ ↑ ↑ ↑ ↑ ↑
7-106
FUN124 P FUN124 P
MATRIX INVERSE
MINV MINV
Ms : Starting register of source matrix

Md : Starting register of destination
L : Length of matrix (Ms and Md)
Ma, Md may combine with V, Z, P0~P9 to serve indirect

address application

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○ ○* ○ ○
z When operation control "EN" = 1 or "EN↑" ( P instruction) has a Ms Md
transition from 0 to 1, source register Ms, which has a length of L,

will be completely inverted (all the bits with a value of 1 will change
to 0, and all those with a value of 0 will change to 1). The results
will then be stored into destination matrix Md.
L
Inverse
Ms
z In the program at left, when X0 goes from 0→1, the

124P.MINV matrix comprised by R0 to R4 will be inverted, and then
X0
EN Ma : R 0 store back into itself (because in this example Ms and
Md : R 0 Md are the same matrix). The results obtained are
L : 5 shown at right in the diagram below.
Ms15 Ms0 Md15 Md0

↓ Ms ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
R2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
↑ ↑ ↑ ↑
Ms79 Ms64 Md79 Md64
7-107
FUN125 P FUN125 P
MATRIX COMPARE
MCMP MCMP
Md : Starting register of matrix a

Mb : Starting register of matrix b
L : Length of matrix (Ma, Mb)
Ma, Mb may combine with V, Z, P0~P9 to

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ma ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Mb ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When comparison control "EN" = 1 or "EN↑" ( P instruction) has a

transition from 0 to 1, then beginning from the top pair of bits (Ma0 Pr
and Mb0) within the 2 matrixes Ma and Mb (when "FHD" = 1 or Pr
value is equal to 16L-1), or beginning from the next pair of bits (Mapr Ma Mb
+ 1 and Mbpr + 1) pointed by pointer Pr (when "FHD" = 0 and Pr
value is less than L-1), this instruction will compare and search for
pairs of bits with different value (when D/S = 1) or the same value
(when D/S = 0). Once match found, pointer Pr will point to the bit
number in the matrix met the search condition. The found objective
L Mapr : Mbpr
flag "FND" will be set to 1. When it has searched to the final pair of
bits in the matrix (Ma16L-1, Mb16L-1), this execution of the instruction
will finish, no matter it has found or not. If this happen then The
compare-to-end flag "END" will be set as 1, and the Pr value will set
to 16L-1 and the next time that this instruction is executed, Pr will
automatically return to the starting point of the matrix (Pr = 0) to begin
the comparison search.
z The range for the pointer value is 0 to 16L-1. The Pr value should not be changed by other instructions, as this will
affect the result of search. If the Pr value exceeds its range, then the pointer error flag "ERR" will be set to 1, and
this instruction will not be carried out.
125P.MCMP
X0 z In the program at left, the "FHD" input is 0, so starting from a
EN Ma : R 0 FND position 1 greater than the pointer value at that time (marked
Mb : R 10 by *), the instruction will do a search for bits with different
FHD L : 5 END status (because D/S = 1). When X0 has a transition from 0→
Pr : R 20 1 three times, the results are shown at right in the diagram
D/S ERR below.
Pr Pr FND END
4 R20
c R20 39 1 0
Ma15 Ma0 Mb15 Mb0
↓ Ma * ↓ ↓ Mb * ↓
R0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 R10 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 Pr FND END
R1
R2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R11
R12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
d R20 79 0 1
R3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Pr FND END
↑ ↑ ↑ ↑ e R20 2 1 0
Ma79 Ma64 Mb79 Mb64
Before execution Execution result
7-108
FUN126 P FUN126 P
MATRIX BIT READ
MBRD MBRD
Ladder symbol
Ms : Starting register of matrix
126P.MBRD
Readout control EN Ms : OTB Output bit L : Matrix length
L : Pr : Pointer register
Pointer increment INC Pr : END Read to end Ms may combine with V, Z, P0~P9 to serve
Pointer clear CLR ERR Pointer error

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
Pr
z When readout control "EN" = 1 or "EN↑" ( P instruction) has a
transition from 0 to 1, the status of the bit Mspr pointed by Ms
pointer Pr within matrix Ms will be read out and appear at the
output bit "OTB". Before the readout, this instruction will first Mspr
check the input -pointer clear "CLR". If "CLR" is 1, then the Pr
OTB
value will be cleared to 0 first before the readout action is carried
out. After the readout is completed, If the Pr value has already
reached 16L-1 (the final bit), then the read-to-end flag "END" will
L
be set to 1. If Pr is less than 16L-1, then the status of pointer
increment "INC" will be checked. If "INC" is 1, then Pr will be
increased by 1. Besides this, pointer clear "CLR" can execute
independently, and is not affected by other input.
z The effective range of the pointer is 0 to 16L-1. Beyond this range the pointer error flag "ERR" will be set to 1,
126P.MBRD z In the program at left, INC = 1, so every time there is

X0
Ms : R OTB
one readout the pointer will be increased by 1. With this
EN 0
way each bit in Ms may be read out successively, as
L : 5
shown at left in the diagram below. When X0 goes 3
INC Pr : R 20 END
times from 0→1, the results are shown at right in the
diagram below .
CLR ERR
Pr Pr OTB END
Ms15 Ms0
↓ Ms ↓ R20 77 c R20 78 1 0
R0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1
R1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OTB Pr OTB END
R2 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 0
R3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d R20 79 0 0
R4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
↑ ↑ ↑ Pr OTB END
Ms79 Ms77 Ms64
e R20 79 1 1
Before execution Execution result
7-109
FUN127 P FUN127 P
MATRIX BIT WRITE
MBWR MBWR
Ladder symbol
Md : Starting register of matrix
127P.MBWR
Write control EN Md : END Write to end L : Matrix length
L : Pr : Pointer register
Write-in bit INB
ERR Pointer error
Pr : Md may combine with V, Z, P0~P9 to serve
Pointer increment INC indirect address application
Pointer clear CLR
Range WY WM WS TMR CTR HR OR SR ROR DR K XR

WY0 WM0 WS0 T0 C0 R0 R3904 R3968 R5000 D0 2 V、Z
Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
rand WY240 WM1896 WS984 T255 C255 R3839 R3967 R4167 R8071 D4095 256 P0~P9
Md ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
Pr
z When write control "EN" = 1 or "EN↑" ( P instruction) has a
transition from 0 to 1, the status of the write-in bit "INB" will be Ms
written into the bit Mdpr pointed by pointer Pr within matrix Md. Mspr
Before the write-in takes place, the status of pointer clear "CLR"
will be checked. If "CLR" is 1, then Pr will be cleared to 0 before OTB
the write-in action. After the write-in action has been completed,
the Pr value will be checked again. If the Pr value has already L
reached 16L-1 (last bit), then the write-to-end flag will be set to
1. If the Pr value is less than 16L-1 and "INC" is 1, then the
pointer will increased by 1. Besides this, pointer clear "CLR" can
execute independently, and is not affected by other input.
z The effective range of Pr is 0 to 16L-1. Beyond this range, the pointer error flag "ERR" will be set to 1, and
this instruction will not be carried out.
127P.MBWR z In the program at left, pointer will be increased each time

X0
EN Ms : R END execution (because "INC" is 1). As shown in the diagram
0
X1 below, when X0 has a transition from 0→1, the status of
L : 5
INB INB (X1) will be written into the Mdpr (Md78) position, and
Pr : R 20 ERR
pointer Pr will increased by 1 (changing to 79). In this
INC case, although Pr is pointing to the end, it has not yet
been written into Md79, so "END" flag is still 0. Only the
CLR
next attempt to write to Md79 will set “END” to 1.
X1 Pr Pr EN
1 R20 78 R20 79 0
Md15 Md0 Md15 Md0
↓ Md ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0= R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1
R2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Ö R1
R2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
↑ ↑ ↑ ↑
Md79 Md64 Md79 Md64
7 - 11 0
FUN128 P FUN128 P
MATRIX BIT SHIFT
MBSHF MBSHF
Ladder symbol
128P.MBSHF Ms : Starting register of source matrix
Shift control EN Ms : OTB Shift out bit Md : Starting register of destination
Md : matrix
Fill-in bit INC L : L : Length of matrix (Ms and Md)
Ms, Md may combine with V, Z, P0~P9
to serve indirect address application
Left/Right direction CLR

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○* ○ ○
INB
z When shift control "EN" = 1 or "EN↑" ( P instruction) has a Ms Md
transition from 0 to 1, source matrix Ms will be retrieved
and completely shifted one position to the left (when L/R =
1) or one position to the right (when L/R = 0). The space
caused by the shift (with a left shift it will be M0, and with a
right shift it will be M16L-1), is replaced by the status of fill-in L
bit "INB". The status of the bits popped out (with a left shift
it will be M16L-1, and with a right shift it will be M0) will Shift
appear at the output bit "OTB". Then the results of this left
OTB 1 bit
shifted matrix will be filled into the destination matrix Md.
z The program at left is an example where Ms and Md are

the same matrix. When X0 goes from 0→1, Ms will be OTB
Ms Md
completely retrieved and moved to the left (because L/R =
1) by 1 bit. It will then be stored back to Md, and the results
are shown at right in the diagram below.
128P.MBSHF
X0 L
EN Ms : R 0 OTB
X0 Md : R 0 Shift
INB L : 5 right
INB 1 bit
L/R
Ms15 Ms0 Md15 Md0

↓ Ms ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X0= R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
R2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R2 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
R3
R4
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ö R3
R4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
↑ ↑ ↑ ↑
Ms79 Ms64 Md79 Md64
7 - 111
FUN129 P FUN129 P
MATRIX BIT ROTATE
MBROT MBROT
Ms : Starting register of source matrix

L : Length of matrix (Ms and Md)
Ms, Md may combine with V, Z, P0~P9 to

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Md ○ ○ ○ ○ ○ ○ ○ ○* ○* ○ ○
L ○* ○ ○
L/R=1
z When rotate control "EN" = 1 or "EN↑" ( P instruction) Ms Md
has a transition from 0 to 1, matrix Ms will be
completely retrieved and rotated by one bit towards
the left (when L/R = 1) or to the right (when L/R = 0).
The space created by the rotation (with a left rotation it
will be M0, and with a right rotation it will be M16L-1) will L
be replaced by the status of the rotated-out bit (with a
Rotate
left rotation it will be M16L-1, and with a right rotation it left
will be M0). The rotated-out bit will not only be used to OTB 1 bit
fill the above-mentioned space, it will also be
transferred to rotated-out bit "OTB".
L/R=0 OTB
Ms Md
L
Shift
right
1 bit
z In the program at left, Ms and Md are the same matrix.

129P.MBROT
X0 When X0 goes from 0 → 1, then the whole of Ms is
EN Ms : R 0 OTB retrieved and rotated right (because L/R = 0) by 1 bit. It is
Md : R 0 then stored back into Ms itself (because in this example
L/R L : 5 Ms and Md are the same matrix). The results are shown
at right in the diagram below.
Ms15 Ms0 Md15 Md0

↓ Ms ↓ ↓ Md ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X0= R1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R2 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 OTB
R3
R4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ö R3
R4
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
↑ ↑ ↑ ↑
Ms79 Ms64 Md79 Md64
7 - 11 2
FUN130 P FUN130 P
MATRIX BIT STATUS COUNT
MBCNT MBCNT
Ms : Starting register of matrix

L : Matrix length
D : Register storing count results
Ms may combine with V, Z, P0~P9 to serve

Ope- ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Ms ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
L ○ ○* ○ ○
D ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
z When count control "EN" = 1 or "EN↑" ( P instruction) has a transition from 0 to 1, then among the 16L bits
of the Ms matrix, this instruction will count the total amount of bits with a status of 1 (when input "1/0" = 1)
or the total amount of bits with a status of 0 (when input "1/0" = 0). The results of the counting will be stored
into the register specified by D. If the value of these amounts is 0, then the Result-is-0 flag "D = 0" will be set
to 1.
130P.MBCNT z The program at left sets X1 first as 0 (to count bits with
X0
EN Ms : R 0 D=0 status of 0) and then as 1 (to count bits with status of 1)
L : 5
and let the signal X0 has a transition from 0→1 for both
X1
case, the execution results are shown at right in the
1/0 D : R 0
diagram below .
Ms15
Ms
Ms0
D
d D
↓ ↓
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
R1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X0= R20 64 R20 16
R2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 c
R3
R4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Ö X1=0 X1=1
↑ ↑
Ms79 Ms64
Source matrix Count of ‘0’ bit Count of ‘1’ bit
7 - 11 3
FUN 139 FUN 139

HIGH SPEED PULSE WIDTH MODULATION OUTPUT
HS PW M HS PW M
PW : PWM output ( 0 = Y0、1 = Y2、2 = Y4、3 = Y6 )
OP : Output polarity ; 0 = Normal

1 = Inverse of output
RS : Resolution ; 0 = 1/100 (1%)
1 = 1/1000 (0.1%)
Pn : Setting of output frequency( 0~255 )
OR : Setting register of output pulse width ( 0~100 or
0~1000)
WR : Working register
Y WX WY WM WS TMR CTR HR IR OR SR ROR DR K

Range
Yn of WX0 WY0 WM0 WS0 T0 C0 R0 R3840 R3904 R3968 R5000 D0
main ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣
Operand
unit WX240 WY240 WM1896 WS984 T255 C255 R3839 R3903 R3967 R4167 R8071 D4095
Pw ○ 0～3
Op 0～1
Rs 0～1
Pn ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ 0～255
OR ○ ○ ○ 0～1000
WR ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Description
z When operation control “EN” = 1, the specified digital output will perform the PWM output, the expression for
output frequency as shown bellow:
184320
1. f pwm = while Rs(Resolution)=1/100
(Pn + 1)
18432
2. fpwm = while Rs(Resolution)=1/1000
(Pn + 1)
Example 1 : If Pn ( Setting of output frequency ) = 50, Rs = 0( 1/100 ), then
184320
f pwm = =3614.117‧‧‧≒3.6KHz
( 50 + 1)
1
T(Period)= ≒277uS
fpwm
For Rs = 1/100, if OR( Setting of output pulse width ) = 1, then T0 ≒ 2.7uS; if OR( Setting of output pulse width )
= 50, then To ≒ 140uS.
.Output waveform :
(1).Pn ( Output frequency ) = 50, Rs = 0 ( 1/100 ), OR ( Output pulse width ) = 1 :
7 - 11 4
FUN 139 FUN 139

HIGH SPEED PULSE WIDTH MODULATION OUTPUT
HS PW M HS PW M
Example 2 : If Pn ( Setting of output frequency ) = 200, Rs = 1( 1/1000 ), then
18432
f pwm = ≒91.7Hz
( 200 + 1)
1
T(Period)= ≒10.9mS
fpwm
For Rs = 1/1000, if OR( Setting of output pulse width ) = 10, then T0 ≒ 109uS; if OR( Setting of output pulse
width ) = 800, then To ≒ 8.72mS
.Output waveform :
7 - 11 5
FUN140 HIGH SPEED PULSE OUTPUT INSTRUCTION FUN140

HSPSO (Brief description on function) HSPSO
Ladder symbol Ps : The Pulse Output (0～3) selection

140.HSPSO 0:Y0 & Y1
Execution control EN Ps : ACT 1:Y2 & Y3
2:Y4 & Y5
SR :
3:Y6 & Y7
Pause INC WR : ERR SR : Positioning program starting register.
WR : Starting working register of instruction operation,
total 7 registers, can not used in any other part of
Abort ABT DN
program.
Range HR DR ROR K
R0 D0 R5000 2
Ope- ∣ ∣ ∣ ∣
rand R3839 D4095 R8071 256
Ps 0～3
SR ○ ○ ○
WR ○ ○ ○*
Command descriptions
z The NC positioning program of HSPSO (FUN140) instruction is a program written and edited with text. The
executing unit of program is divided by step (which includes output frequency, traveling distance, and
transferring conditions). For one FUN140 instruction, can program 250 steps of positioning points at the most.
Each step of positioning program requires 9 registers. For detailed application, please refer to chapter 13 “the
NC positioning control of FBs-PLC”.
z The benefits of storing the positioning program in the register is that, while in application which use the MMI
(man machine interface) as the operation console can save the positioning programs to MMI. Whenever the
change of the positioning programs is requested, the download of positioning program can be simply done by
a series of write register commands.
z The NC positioning of this instruction doesn’t provide the linear interpolation function.
z When execution control “EN”=1, if Ps0～3 is not controlled by other FUN140 instruction (the status of
Ps0=M1992, Ps1=M1993, Ps2=M1994, and Ps3=M1995 is ON respectively), it will start to execute from the
next step of positioning point (when goes to the last step, it will be restarted from the first step); if Ps0～3 is
controlled by other FUN140 instruction (the status of Ps0=M1992, Ps1=M1993, Ps2=M1994, and
Ps3=M1995 are OFF), this instruction will wait and acquires the control right of output point immediately right
after other FUN140 release the output.
z When execution control input “EN” =0, it stops the pulse output immediately.
z When output pause “PAU” =1 and execution control was 1, it will pause the pulse output. When output
pause “PAU” =0 and execution control is still 1, it will continue the unfinished pulse output.
z When output abort “ABT”=1, it will halt and stop pulse output immediately. (When the execution control
input “EN” becomes 1 next time, it will restart from the first step of positioning point to execute.)
z While send the output pulse, the output indication “ACT” is ON.
z When there is an execution error, the output indication “ERR” will be ON. (The error code is stored in the
error code register.)
z When the execution of each step of positioning program is completed, the output indication “DN” will be ON.
*** The working mode of Pulse Output must be configured (without setting, Y0～Y7 will be treated as normal
output) to any one of following modes, before the HSPSO instruction can be worked.
U/D Mode: Y0 (Y2, Y4, Y6), as up pulse.

Y1 (Y3, Y5, Y7), as down pulse.
K/R Mode: Y0 (Y2, Y4, Y6), as the pulse out..
Y1 (Y3, Y5, Y7), as the direction.
A/B Mode: Y0 (Y2, Y4, Y6), as A phase pulse.
Y1 (Y3, Y5, Y7), as B phase pulse.
hThe output polarity for Pulse Output can select to be Normally ON or Normally OFF.
hThe working mode of Pulse Output can be configured by WINPROLADDER in “Output Setup” setting page.
7 - 11 6
FUN141 NC POSITIONING PARAMETER VALUE SETTING FUN141

MPARA (Brief description on function) MPARA
Ps : The pulse output (0～3) selection
SR : Starting register for parameter table; it has 18

parameters totally, and occupy 24 registers.
Range HR DR ROR K
R0 D0 R5000 2
Ope- ∣ ∣ ∣ ∣
rand R3839 D4095 R8071 256
Ps 0～3
SR ○ ○ ○
Operation descriptions
hIt is not necessary to use this instruction. if the system default for parameter values is matching what user
demanded, then this instruction is not needed. However, if it needs to change the parameter value
dynamically, this instruction is required.
hThis instruction incorporates with FUN140 for positioning control purpose.
hWhether the execution control input “EN” = 0 or 1, this instruction will be performed.
hWhen there are any errors in parameter value, the output indication “ERR” will be ON. (The error code is
stored in the error code register.)
hFor detailed functional description and usage, please refer to chapter 13 “The NC positioning control of
FBs-PLC” for explanation.
7 - 11 7
FUN142 P STOP THE HSPSO PULSE OUTPUT FUN142 P

PSOFF (Brief description on function) PSOFF
Ps : 0～3
Enforce the Pulse Output PSOn (n= Ps) to stop.
z When execution control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, this instruction will enforce
the assigned number set of HSPSO (High Speed Pulse Output) to stop pulse output.
z While in the application for mechanical original point reset, as soon as reach the original point can use this
instruction to stop the pulse output immediately, so as to make the original point stop at the same position
every time when performing mechanical original point resetting.
z For detailed functional description and usage, please refer to chapter 13 “The NC positioning control of
7 - 11 8
FUN143 P CONVERT THE CURRENT PULSE VALUE TO DISPLAY VALUE FUN143 P

PSCNV (mm, Deg, Inch, PS) (Brief description on function) PSCNV
Ps : 0～3; it converts the number of the pulse position to be

the mm (Deg, Inch, PS) that has same unit as the set
value, so as to make current position displayed.
D : Register that stores the current position after

conversion. It uses 2 registers, e.g. if D = D10, which
means D10 is Low Word and D11 is High Word.
Range HR DR ROR K
R0 D0 R5000 2
Ope- ∣ ∣ ∣ ∣
rand R3839 D4095 R8071 256
Ps 0 ～3
D ○ ○ ○
z When execution control “En” =1 or “EN↑”( P instruction) changes from 0→1, this instruction will convert
the assigned current pulse position (PS) to be the mm (or Deg, Inch, or PS) that has same unit as the set
value, so as to make current position displaying.
z Only when the FUN140 instruction is executed, then it can get the correct conversion value by executing
this instruction.
z For detailed functional description and usage, please refer to chapter 13 “The NC positioning control of
7 - 11 9
FUN145 P FUN145 P
ENABLE CONTROL OF THE INTERRUPT AND PERIPHERAL
EN EN
LBL : External input or peripheral label name that to be

enabled.
z When enable control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, it allows the external input or
peripheral interrupt action which is assigned by LBL.
z The enabled interrupt label name is as follows:(Please refer the section 10.3 for details)
LBL name Description LBL name Description LBL name Description

HSTA High speed X4 positive edge X10 positive edge
HSTAI X4 + I X1 0 + I
counter interrupt interrupt interrupt
HSC0 High speed X5 negative edge X10 negative edge
HSC0I X4 − I X1 0 − I
HSC1 High speed X5 positive edge X11 positive edge
HSC1I X5 + I X1 1 + I
HSC2I X5 − I X1 1 − I
HSC3I X6 + I X1 2 + I
X0 positive edge X6 negative edge X12 negative edge
X0 + I X6 − I X1 2 − I
interrupt interrupt interrupt
X0 negative edge X7 positive edge X13 positive edge
X0 − I X7 + I X1 3 + I
X1 + I X7 − I X1 3 − I
X1 − I X8 + I X1 4 + I
X2 + I X8 − I X1 4 − I
X2 − I X9 + I X1 5 + I
X3 + I X9 − I X1 5 − I
X3 negative edge
X3 − I
interrupt
z In practical application, some interrupt signals should not be allowed to work at sometimes, however, it should
be allowed to work at some other times. Employing FUN146 (DIS) and FUN145 (EN) instructions could
attain the above mentioned demand.
Program example
M0 145.P z When M0 changes from 0→1, it allows X0 to send

EN EN X0+I interrupt when X0 changes from 0→1. CPU can rapidly
process the interrupt service program of X0+I.
7-120
FUN146 P FUN146 P
DISABLE CONTROL OF THE INTERRUPT AND PERIPHERAL
DIS DIS
LBL : Interrupt label intended to disable or peripheral name to

be disabled.
z When prohibit control “EN” =1 or “EN↑” ( P instruction) changes from 0→1, it disable the interrupt or
peripherial operation designated by LBL.
z The interrupt label name is as follows:
LBL name Description LBL name Description LBL name Description

HSTA High speed X4 positive edge X10 positive edge
HSTAI X4 + I X1 0 + I
HSC0I X4 − I X1 0 − I
HSC1I X5 + I X1 1 + I
HSC2I X5 − I X1 1 − I
HSC3I X6 + I X1 2 + I
X0 + I X6 − I X1 2 − I
X0 − I X7 + I X1 3 + I
X1 + I X7 − I X1 3 − I
X1 − I X8 + I X1 4 + I
X2 + I X8 − I X1 4 − I
X2 − I X9 + I X1 5 + I
X3 + I X9 − I X1 5 − I
X3 negative edge
X3 − I
interrupt
z In practical application, some interrupt signals should not be allowed to work at certain situation. To achive
this, this instruction may be used to disable the interrupt signal.
Program example
M0 146.P z When M0 changes from 0→1, it prohibits X2 from

EN DIS X2+I
sending interrupt when X2 changes from 0→1.
7-121
FUN150 MODBUS MASTER INSTRUCTION FUN150

M-BUS （WHICH MAKES PLC AS THE MODBUS MASTER THROUGH PORT 1~4） M-BUS
Pt ：1~4, specify the communication port being acted

as the Modbus master
SR：Starting register of communication program
WR :Starting register for instruction operation. It controls 8

registers, the other programs can not repeat in using.
Range HR ROR DR K
R0 R5000 D0
Ope-
∣ ∣ ∣
rand
R3839 R8071 D4095
Pt 1～4
SR ○ ○ ○
WR ○ ○* ○
Description
1. FUN150 (M-BUS) instruction makes PLC act as Modbus master through Port 1～4, thus it is very easy to
communicate with the intelligent peripheral with Modbus protocol.
2. The master PLC may connect with 247 slave stations through the RS-485 interface.
3. Only the master PLC needs to use M-BUS instruction.
4. It employs the program coding method or table filling method to plan for the data flow controls; i.e. from which
one of the slave station to get which type of data and save them to the master PLC, or from the master PLC
to write which type of data to the assigned slave station. It needs only seven registries to make definition;
every seven registers define one packet of data transaction.
5. When execution control 〝EN↑〞changes from 0→1 and both inputs Pause “PAU” and Abort “ABT” are 0, and
if Port 1/2/3/4 hasn’t been controlled by other communication instructions [i.e. M1960 (Port1) / M1962 (Port2) /
M1936 (Port3) / M1938 (Port4) = 1], this instruction will control the Port 1/2/3/4 immediately and set the
M1960/M1962/M1936/M1938 to be 0 (which means it is being occupied), then going on a packet of data
transaction immediately. If Port 1/2/3/4 has been controlled (M1960/M1962/M1936/M1938 = 0), then this
instruction will enter into the standby status until the controlling communication instruction completes its
transaction or pause/abort its operation to release the control right (M1960/M1962/M1936/M1938 =1), and
then this instruction will become enactive, set M1960/M1962/M1936/M1938 to be 0, and going on the data
transaction immediately.
6. While in transaction processing, if operation control “ABT” becomes 1, this instruction will abort this
transaction immediately and release the control right (M1960/M1962/M1936/M1938 = 1). Next time, when this
instruction takes over the transmission right again, it will restart from the first packet of data transaction.
7. While〝A/R〞=0，Modbus RTU protocol；〝A/R〞=1，Modbus ASCII protocol。
8. While it is in the data transaction, the output indication “ACT” will be ON.
9. If there is error occurred when it finishes a packet of data transaction, the output indication “DN” & “ERR” will
be ON.
10. If there is no error occurred when it finishes a packet of data transaction, the output indication “DN” will be
ON.
7-122
COMMUNICATION LINK INSTRUCTION

FUN 151 FUN 151
(WHICH MAKES PLC ACT AS THE MASTER STATION IN CPU LINK NETWORK
CLINK CLINK
THROUGH PORT 1~4)
Pt : Assign the port, 1～4

MD : Communication mode, MD0~MD3
SR : Starting register of communication table
(see example for its explanation)
WR : Starting register for instruction operation (see
example for its explanation). It controls 8 registers,
the other programs can not repeat in using.
Range HR ROR DR K
R0 R5000 D0
Ope-
∣ ∣ ∣
rand
R3839 R8071 D4095
Pt 1～4
ＭＤ 0～3
SR ○ ○ ○
WR ○ ○* ○
Description
● This instruction provides 4 instruction modes MD0～MD3. Of which, three instruction modes MD0～MD2, are
“regular link network”, and the MD3 is the “high speed link network”. The following are the function description of
respective modes. For the details, please refer to section 12.1.2 for explanation.
hMD0 : Master station mode for FATEK CPU LINK.
For any PLC, whose ladder program contains the FUN151:MD0 instruction, will become master
station of FATEK CPU LINK network. The master station PLC will base on the communication
program stored in data registers in which the target station, data type, data length, etc, were
specified to read or write slave station via “FATEK FB-PLC Communication Protocol” command.
With this approach up to 254 PLC stations can share the data each other
hMD1 : Active ASCII data transmission mode.
With this mode, the FUN151 instruction will parse the communication program stored in data
registers and base on the parsing result send the data from port2 to ASCII peripherals (such as
computer, other brand PLC, inverter, moving sign, etc, this kind of device can command by ASCII
message). The operation can set to be (1) transmit only, which ignores the response from
peripherals, (2) transmit and then to receive the response from peripherals. When operate with
mode (2) then the user must base on the communication protocol of peripheral to parsing and
prepare the response message by writing the ladder instructions.
hMD2 : Passive ASCII data receiving mode.
With this mode, the FUN151 will first wait to receive ASCII messages sent by external ASCII
peripherals (such as computer, other brand PLC, card reader, bar code reader, electronic weight,
etc. this kind of device can send ASCII message). Upon receiving the message, the user can base
on the communication protocol of peripheral to parsing and react accordingly. The operation can
set to (1) receive only without responding, or (2) receive then responding. For operation mode (2)
the user can use the table driver method to write a communication program and after received a
message this instruction can base on this communication program automatically reply the
message to peripheral.
hMD3 : Master station mode of FATEK high speed CPU LINK.
The most distinguished difference between this mode and MD0 is that the communication
response of MD3 is much faster than MD0. With The introduction of MD3 mode CPU LINK, The
FATEK PLC can easily to implement the application of distributed control and real time data
monitoring.
7-123
READ/WRITE FILE REGISTER
RW F R RW FR
Sa: Starting address of data register
Sb: Starting address of file register
Pr : Record pointer register
L : Quantity of register to form a record, 1~511

Sa operand can combine V、Z、P0~P9 for index
addressing.
WX WY WM WS TMR CTR HR IR OR SR ROR DR K XR FR

Range WX0 R384 R390 F0
WM0 R0
WY0 WS0 T0 C0 0 4 R3968 R5000 D0 V、Z ∣
∣ ∣ ∣
∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ ∣ F8191
Operand WX2 WM18 R383
WY240 WS984 T255 C255 R390 R396 R4167 R8071 D4095 P0～P9
40 96 9
3 7
Sa ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○
Sb ○
Pr ○ ○ ○ ○ ○ ○ ○ ○* ○* ○
L ○ ○* ○ 1~511
Description
● When operation control "EN"=1 or "EN↑"( P instruction) changes from 0→1,it will perform the read ("R/W"=1)
or write ("R/W"=0) file register operation. While reading, the content of data registers starting from Sa will be
overwritten by the content of file registers addressed by the base file register Sb and record pointer Pr; while
writing, the content of file registers addressed by the base file register Sb and record pointer Pr will be
overwritten by the content of data registers starting from Sa; L is the operation quantity or record size. The
access of file register adopts the concept of RECORD data structure to implement. For example, Sa=R0,
Sb=F0, L=10, the read/write details shown as below
Sb
F0 ~ F9
(L=10) Pr = 0
F10 ~ F19
Sa (L=10) Pr = 1
R0 ~ R9 F20 ~ F29
(L=10) (L=10)
Pr = 2
F30 ~ F39
(L=10) Pr = 3
7-124
READ/WRITE FILE REGISTER
RW F R RW F R
● For ladder program application, only this instruction can access the file registers.
● The record pointer will be increased by 1 after execution while pointer control input "INC"=1.
● This instruction will not be executed and error indicator ”ERR" will be 1 while incorrect record size (L=0 or >
511) or the operation out of the file register's range (F0～F8191).
160.RWFR M10
M0 When M0 changes from 0Æ1, if D0 =2, the contents
EN Sa : R0 ERR
of file registers F200~F249 will be overwritten by the
Sb : F100
content of data registers R0~R49. the record length is
R/W Pr : D0
50.
L : 50
.Pointer will be increased by 1 after operation.
INC
160.RWFR M10
M0 .When M0 changes from 0Æ1, if D0 = 1, the content
EN Sa : R0 ERR
of data registers R0~R49 will be overwritten by the file
Sb : F100
registers F150~F199.
R/W Pr : D0
.The record pointer will be increased by 1 after
L : 50
operation.
INC
7-125
CONVERSION OF INTEGER TO FLOATING POINT NUMBER
IÆ F IÆ F
Ladder symbol
200DP.I F S : Starting register of Integer to be converted
Conversion control EN S : D : Starting register to store the result of conversion
D :
Range HR ROR DR K XR
R0
R5000 D0 16/32 V、Z
∣
∣ ∣ bit
R383
Operand R8071 D4095 Integer P0～P9
9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of
the format please refer to 5.3 (Numbering System)…page 5 - 9 .
integer data from S register into D~D+1 32-bits register( floating point number data)
200P.I F
X0
EN S : R0
D : D0
7-126
CONVERSION OF FLOATING POINT NUMBER TO INTEGER
FÆ I FÆ I
Ladder symbol
201DP.F I
S : Starting register of Integer to be converted
Conversion control EN S : ERR Range Error
D : Starting register to store the result of conversion
D :
R0
R5000 D0 16 bit V、Z
∣
∣ ∣ OR
R383
Operand R8071 D4095 32 bit P0～P9
9
S ○ ○ ○ ○
D ○ ○* ○ ○
Description
floating point data from S~S+1 32bits register into D register( integer data ).
z If the value exceeds the valid range of destination, then do not carry out this instruction, and set the
range-error flag “ERR” as 1 and the D register will be intact.
201P.F I
X2
EN S : R20 ERR
D : D10
7-127
FUN202 P FUN202 P
FLOATING POINT NUMBER ADDITION
FAD D FAD D
Sa: Augend
Sb: Addend
of the addition
R0
R5000 D0 Floating V、Z
∣
∣ ∣ point
R383
Operand R8071 D4095 number P0～P9
9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
z Performs the addition of the data specified at Sa and Sb and writes the results to a specified register D when
the add control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the result exceed the range that the
38
floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1 and the D
register will be intact.
202P.FADD
X0
Sa : R0 ERR
Sb : R10
D : R20
7-128
FUN 203 P FUN 203 P

FLOATING POINT NUMBER SUBTRACTION
FSUB FSUB
Sa: Minuend
Sb: Subtrahend
of the subtraction
R0
∣
∣ ∣ point
R383
9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
z Performs the subtraction of the data specified at Sa and Sb and writes the results to a specified register D
when the subtract control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the result exceed the range
38
that the floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1 and
the D register will be intact.
203P.FSUB
X0
EN Sa : R0 ERR
Sb : R4
D : R10
7-129
FUN 204 P FUN 204 P

FLOATING POINT NUMBER MULTIPLICATION
FMUL FMUL
Sa: Multiplicand
Sb: Multiplier
of the multiplication
R0
∣
∣ ∣ point
R383
9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
z Performs the multiplication of the data specified at Sa and Sb and writes the results to a specified register D
when the multiplication control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the result exceed the
38
range that the floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set to 1
and the D register will be intact.
204P.FMUL
M10
EN Sa : R10 ERR
Sb : R12
D : R14
DR10 1 2 3 . 4 5 Floating Point Number : DR10 42F6E666H
DR12 6 7 8 . 5 4 Floating Point Number : DR12 4429A28FH

×
DR14 47A39AE2H
7-130
FUN 205 P FUN 205 P

FLOATING POINT NUMBER DIVISION
FDIV FDIV
Sa: Dividend
Sb: Divisor
of the division
R0
∣
∣ ∣ point
R383
9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
the format please refer to 5.3 (Numbering System) page 5 - 9 .
z Performs the division of the data specified at Sa and Sb and writes the result to the registers specified by
register D when the division control input "EN" =1 or "EN↑" ( P instruction) from 0 to 1. If the result exceed
38
the range that the floating point number can be expressed(± 3 . 4 * 1 0 ) then the error flag FO0 will be set
to 1 and the D register will be intact.
205P.FDIV
X5
EN Sa : R0 ERR
Sb : R2
D : R4
7-131
FUN 206 P FUN 206 P

FLOATING POINT NUMBER COMPARE
FCMP FCMP
Sa: The register to be compared
Sb: The register to be compared
Sa, Sb may combine with V, Z, P0~P9 to serve

indirect addressing.
R0
∣
∣ ∣ point
R383
9
Sa ○ ○ ○ ○ ○
Sb ○ ○ ○ ○ ○
Description
z Compares the data of Sa and Sb when the compare control input "EN" =1 or "EN↑" ( P instruction) from 0
to 1. If the data of Sa is equal to Sb, then set FO0 to 1. If the data of Sa>Sb, then set FO1 to 1. If the data
of Sa<Sb, then set FO2 to 1. If the data of Sa < Sb, then set the FO2 to 1.
X0 206P.FCMP
EN Sa : R0 a=b
Sb : R2 a>b
Y0
a<b
z From the above example, we first assume the data of DR0 is 200.1 and DR2 is 200.2, and then compare the
data by executing the CMP instruction. The FO0 and FO1 are set to 0 and FO2 (a<b) is set to 1 since a<b.
z If you want to have the compound results, such as≧、≦、< > etc., please send =、< and > results to relay first
and then combine the result from the relays.
7-132
FUN 207 P FUN 207 P

FLOATING POINT NUMBER ZONE COMPARE
FZCP FZCP
S : Register for zone comparison
SU: The upper limit value
SL: The lower limit value

S, SU, SL may combine with V, Z, P0~P9 to
R0
∣
∣ ∣ point
R383
9
S ○ ○ ○ ○ ○
Su ○ ○ ○ ○ ○
SL ○ ○ ○ ○ ○
Description
z When compare control "EN" = 1 or "EN↑" ( P instruction) changes from 0 to 1, compares S with upper limit
SU and lower limit SL. If S is between the upper limit and the lower limit (SL≦S≦SU), then set the inside
zone flag "INZ" to 1. If the value of S is greater than the upper limit SU, then set the higher than upper limit
flag "S>U" to 1. If the value of S is smaller then the lower limit SL, then set the lower than lower limit flag
"S<L" as 1.
z The upper limit SU should be greater than the lower limit SL. If SU<SL, then the limit value error flag "ERR"
will set to 1, and this instruction will not carry out.
z The instruction at left compares the value of
X0 207P.FZCP Y0 DR10 with the upper and lower limit zones

EN S : R10 INZ formed by DR12 and DR14. If the values of
S>U DR10~DR14 are as shown in the diagram at

Su : R12
bottom left, then the result can then be
SL : R14 S<L
obtained as at the right of this diagram.
ERR
z If want to get the status of out side the zone,
then OUT NOT Y0 may be used, or an OR
operation between the two outputs S>U and
S<L may be carried out, and move the result
to Y0.
7-133
FUN 207 P FUN 207 P

FLOATING POINT NUMBER ZONE COMPARE
FZCP FZCP
X0＝ Æ FLOATING ZONE COMPARE Æ Y0 = 1
Results of execution
7-134
Advance Function Instruction
FUN 208 P FUN 208 P

FLOATING POINT NUMBER SQUARE ROOT
FSQR FSQR
S : Source register to be taken square root

(square root value)

HR ROR DR K XR
Range R0
∣
∣ ∣ point
Operand R383
R8071 D4095 number P0～P9
9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, take the square root of the data
specified by the S value or S~S+1 register, and store the result into the register specified by D~D+1.
z If the value of S is negative, then the error flag "ERR" will be set to 1, and do not execute the operation.
208P.FSQR
X0
EN S : 2520.04 ERR
D : D0
7-135
FUN 209 P FUN 209 P

SIN TRIGONOMETRIC INSTRUCTION
FSIN FSIN
S : Source register to be taken SIN

(SIN value)

indirect address application.
HR ROR DR K XR
Range R0
R5000 D0 Integer V、Z
∣
∣ ∣ 16 Bit
Operand R383
9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
z The format of floating point number of Fatek-PLC follows the IEEE-754 standard. For detail explanation of the
format please refer to 5.3 (Numbering System) page 5 - 9 .
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, take the SIN value of the angle data
specified by the S register and store the result into the register D~D+1 in floating point number format. The
valid range of the angle is from –18000 to +18000, unit in 0.01 degree.
z If the S value is not within the valid range, then the S value error flag "ERR" will be set to 1, and do not
execute the operation.
209P.FSIN
X0
EN S : 3000 ERR z At left, the example program gets the SIN value of 30,
D : R100 and stores the results the register DR100.
7-136
FUN 210 P FUN 210 P

COS TRIGONOMETRIC INSTRUCTION
FCOS FCOS
S : Source register to be taken COS

(COS value)

HR ROR DR K XR
Range R0
∣
∣ ∣ 16 Bit
Operand R383
9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
format please refer to 5.3 (Numbering System) page 5-9.
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, take the COS value of the angle data
210P.FCOS
X0 z At left, the example program gets the COS value of 60,
EN S : R0 ERR
and stores the results the register DR200.
D : R200
7-137
FUN 211 P FUN 211 P

TAN TRIGONOMETRIC INSTRUCTION
FTAN FTAN
S : Source register to be taken TAN

(TAN value)

HR ROR DR K XR
Range R0
∣
∣ ∣ 16 Bit
Operand R383
9
S ○ ○ ○ ○ ○
D ○ ○* ○ ○
Description
format please refer to 5.3 (Numbering System) page 5-9.
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, take the COS value of the angle data
211P.FTAN
M0 z At left, the example program gets the TAN value of 45,
EN S : R0 ERR
and stores the results the register DD50.
D : D50
7-138
FUN 212 P FUN 212 P

CHANGE SIGN OF THE FLOATING POINT NUMBER
FNEG FNEG
D : Register to be changed sign

D may combine with V, Z, P0~P9 to serve indirect
address application
HR ROR DR K XR
Range R0
∣
∣ ∣ 16 Bit
Operand R383
9
D ○ ○* ○ ○
Description
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, the sign of the floating point number
register specified by D will be toogled.
X0 212P. z The instruction at left negates the value of the

EN FNEG R0
DR0 register, and stores it back to DR0.
7-139
FUN 213 P FUN 213 P

FLOATING POINT NUMBER ABSOLUTE VALUE
FABS FABS
D : Register to be taken absolute value

D may combine with V, Z, P0~P9 to serve indirect
address application
HR ROR DR K XR
Range R0
∣
∣ ∣ 16 Bit
Operand R383
9
D ○ ○* ○ ○
Description
z When operation control "EN" = 1 or "EN↑" ( P instruction) from 0 to 1, calculate the absolute value of the
floating point number register specified by D, and write it back into the original D register.
X0 213P.
z The instruction at left calculates the absolute
EN FABS R0
value of the DR0 register, and stores it back in
DR0.
7-140
MEMO
Chapter 8 Step Instruction Description
Structured programming design is a major trend in software design. The benefits are high readability, easy
maintenance, convenient updating and high quality and reliability. For the control applications, consisted of many
sequential tasks, designed by conventional ladder program design methodology usually makes others hard to maintain.
Therefore, it is necessary to combine the current widely used ladder diagrams with the sequential controls made
especially for machine working flow. With help from step instructions, the design work will become more efficient, time
saving and controlled. This kind of design method that combines process control and ladder diagram together is called
the step ladder language.
The basic unit of step ladder diagram is a step. A step is equivalent to a movement (stop) in the machine operation
where each movement has an output. The complete machine or the overall sequential control process is the combination
of steps in serial or parallel. Its step-by-step sequential execution procedure allows others to be able to understand the
machine operations thoroughly, so that design, operation, and maintenance will become more effective and simpler.
8.1 The Operation Principle of Step Ladder Diagram
【Example】【Description】
1. STP Sxxx is the symbol representing a step

M1924 Sxxx that can be one of S0 ～ S999. When
Y0 executing the step (status ON), the ladder diagram
STP S0 on the right will be executed and the previous step
and output will become OFF.
X1 Y1 X2 Y2 2. M1924 is on for a scan time after program start.
STP S20 STP S21 Hence, as soon as ON, the stop of the initial step
S0 is entered (S0 ON) while the other steps are
X3
Y3 kept inactive, i.e. Y1～Y5 are all OFF. This means
STP S22 M1924 ONÆS0 ONÆY0 ON and Y0 will remain
X4 X5 ON until one of the contacts X1 or X2 is ON.
Y4 3. Assume that X2 is ON first; the path to S21 will
STP S23 then be executed.
X10 Y5 S21 ON Y2 ON
X6 X2 ON⇒ ⇒
S0 OFF Y0 OFF
Y2 will remain ON until X5 is ON.
4. Assume that X5 is ON, the process will move

forward to step S23.
S23 ON Y4 ON
i.e. X5 ON⇒ ⇒
S21 OFF Y2 OFF
Y4 and Y5 will remain ON until X6 is ON.
※If X10 is ON, then Y5 will be ON.
5. Assume that X6 is ON, the process will move

forward to S0.
S0 ON Y0 ON
i.e. X6 ON⇒ ⇒
S23 OFF Y4、Y5 OFF
Then, a control process cycle is completed and the
next control process cycle is entered.
8-1
8.2 Basic Formation of Step Ladder Diagram
c Single path
z Step S20 alone moves to step S21 through X0.
z X0 can be changed to other serial or parallel

STP S20 combination of contacts.
X0
STP S21
d Selective divergence/convergence
STP S20 z Step S20 selects an only one path which divergent
Selective divergence condition first met. E.g. X2 is ON first, then only the path
of step S23 will be executed.
X0 X1 X2 z A divergence may have up to 8 paths maximum.
STP S21 STP S22 STP S23
z X1, X2, ….., X22 can all be replaced by the serial or
parallel combination of other contacts.
X20 X21 X22
Selective convergence
STP S40
e Simultaneous divergence/convergence
STP S20 z After X0 is ON, step S20 will simultaneously execute all
Simultaneous divergence paths below it, i.e. all S21, S22, S23, and so on, are in
X0
action.
z All divergent paths at a convergent point will be executed

STP S21 STP S22 STP S23 to the last step (e.g. S30, S31 and S32). When X1 is ON,
they can then transfer to S40 for execution.
z The number of divergent paths must be the same as the

number of convergent paths. The maximum number of
divergence/convergence path is 8.
X1 Simultaneous convergence
STP S40
8-2
f Jump
a. The same step loop
z There are 3 paths below step S20 as shown on the left.

STP S20 Assume that X2 is ON, then the process can jump directly
3-divergence to step S23 to execute without going through the process
of selective convergence.
X0 X1 X2
z The execution of simultaneous divergent paths can not be
STP S21 STP S22 S23 skipped.
X3 X4
2-convergence
STP S23
b. Different step loop
M1924 X10
STP S0 STP S7
X0 X4 X11 X12
STP S20 S30 STP S30 S21
X2 X1
STP S21 STP S31

X3 X3
gClosed Loop and Single Cycle
a. Closed Loop
z The initial step S1 is ON, endless cycle will be continued

M1924 afterwards.
STP S1 S20
S1Æ ÆS22
S21
X0
STP S20 STP S21
X1
STP S22
X2
8-3
b. Single Cycle
z When step S20 is ON, if X2 is also ON, then “RST S21”

M1924 X0 instruction will let S21 OFF which will stop the whole step
process.
STP S0
X1
STP S20
X2
STP S21 RST S21
c. Mixed Process
M1924
STP S0
X0 X1 X2
X3 X4 X7
X5 STP S25 RST S25
STP S22 STP S23
X6
h Combined Application
A branch can have up to 8 branch loops
1 2 3 4 5 6 7 8 16
The maximum number of downward horizontal branch loops of an initial step is 16
8-4
8.3 Introduction of Step Instructions: STP, FROM, TO and STPEND
● STP Sx : S0≦Sx≦S7 (Displayed in WinProladder)
or
STP Sx ：S0≦Sx≦S7 (Displayed in FP-07)
This instruction is the initial step instruction from where the step control of each machine process can be derived. Up to 8
initial steps can be used in the FBs series, i.e. a PLC can make up to 8 process controls simultaneously. Each step
process can operate independently or generate results for the reference of other processes.
【Example 1】 Go to the initial step S0 after each start (ON)
WinProladder FP-07
M1924
TO S0 ORG M1924
M1924 TO S0
STP S0 STP S0
STP S0
【Example 2】 Each time the device is start to run or the manual button is pressed or the device is malfunction, then the
device automatically enters the initial step S0 to standby.
WinProladder FP-07
ORG M1924
M1924 OR X0
X0 M0 TO S0
M1924
OR M0
X0
TO S0
STP S0 STP S0
M0
Standby process program
Standby
STP S0 Process
Program
【Description】X0: Manual Button, M0: Abnormal Contact.
8-5
● STP Sxxx : S20≦Sxxx≦S999（Displayed in WinProladder）
or
STP Sxxx : S20≦Sxxx≦S999（Displayed in FP-07）
This instruction is a step instruction, each step in a process represents a step of sequence. If the status of step is
ON then the step is active and will execute the ladder program associate to the step.
【Example】
WinProladder FP-07
M1924 ORG M1924

M1924 TO S0 TO S0
Y0 Y0 STP S0
STP S0 STP S0
OUT Y0
FROM S0
X10 X10
Y1 TO S20 AND X10
X1
STP S20 TO S20
X1 Y1 STP S20
X2 Y2 STP S20
X11 OUT TR0
X2 Y2 AND X1
OUT Y1
X11
TO S0 LD TR0
AND X2
STPEND OUT Y2
FROM S20
AND X11
TO S0
STPEND
【Description】1. When ON, the initial step S0 is ON and Y0 is ON.
2. When transfer condition X10 is ON (in actual application, the transferring condition may be formed by
the serial or parallel combination of the contacts X, Y, M, T and C), the step S20 is activated. The
system will automatically turn S0 OFF in the current scan cycle and Y0 will be reset automatically to
OFF.
X1 ON ÆY1 ON
S20 ON
i.e. X10 ON⇒ ⇒ X2 ON ÆY2 ON
S0 OFF
Y0 OFF
3. When the transfer condition X11 is ON, the step S0 is ON, Y0 is ON and S20, Y1 and Y2 will turn OFF
at the same time.
Y0 ON
S0 ON
i.e. X11 ON⇒ ⇒ Y1 OFF
S20 OFF
Y2 OFF
8-6
● FROM Sxxx : S0≦Sxxx≦S999（Displayed in WinProladder）
or
FROM Sxxx : S0≦Sxxx≦S999（Displayed in FP-07）
The instruction describes the source step of the transfer, i.e. moving from step Sxxx to the next step in coordination
with transfer condition.
【Example】
WinProladder FP-07
M1924 ORG M1924

TO S0
M1924 TO S0
X0 Y0 X0 Y0 STP S0
STP S0 STP S0 AND X0
X1 OUT Y0
TO S20 FROM S0
X1 X2 X3
Y1 Y2 Y3 X2 OUT TR 0
STP S20 STP S21 STP S22 TO S21
AND X1
X5 X4 X6 X3 TO S20
TO S22
LD TR 0
S0
Y1 AND X2
X7 STP S20 TO S21
Y4 Y2 LD TR 0
STP S23 STP S21 AND X3
X4 TO S22
X8 TO S0
STP S20
Y3 OUT Y1
STP S22 STP S21
X5 X7 OUT Y2
FROM S20 TO S23 FROM S21
X6 AND X4
FROM S22
TO S0
Y4
STP S22
STP S23
OUT Y3
X8
TO S0 FROM S20
AND X5
STPEND FROM S22
AND X6
ORLD
AND X7
TO S23
STP S23
OUT Y4
FROM S23
AND X8
TO S0
STPEND
8-7
【Description】: 1. When ON, the initial step S0 is ON. If X0 is ON, then Y0 will be ON.
2. When S0 is ON: a. if X1 is ON, then step S20 will be ON and Y1 will be ON.
b. if X2 is ON, then step S21 will be ON and Y2 will be ON.
c. if X3 is ON, then step S22 will be ON and Y3 will be ON.
d. if X1, X2 and X3 are all ON simultaneous, then step S20 will have the priority to be
ON first and either S21 or S22 will not be ON.
e. if X2 and X3 are ON at the same time, then step S21 will have the priority to be
ON first and S22 will not be ON.
3. When S20 is ON, if X5 and X7 are ON at the same time, then step S23 will be ON, Y4 will be ON and
S20 and Y1 will be OFF.
4. When S21 is ON, if X4 is ON, then step S0 will be ON and S21 and Y2 will be OFF.
5. When S22 is ON, if X6 and X7 are ON at the same time, then step S23 will be ON, Y4 will be ON and
S22 and Y3 will be OFF.
6. When S23 is ON, if X8 is ON, then step S0 will be ON and S23 and Y4 will be OFF.
8-8
● TO Sxxx : S0≦Sxxx≦S999（Displayed in WinProladder）
or
TO Sxxx : S0≦Sxxx≦S999（Displayed in FP-07）
This instruction describes the step to be transferred to.
【Example】
WinProladder FP-07
M1924 ORG M1924

M1924 TO S0 TO S0
Y0 Y0 STP S0
X0 X0
STP S0 AND X0
STP S0
OUT Y0
X1 X1 FROM S0
TO S20
AND X1
Y1 Y2 TO S20
STP S20 STP S21 TO S21
TO S21
Y1 STP S20
X2
Y3 STP S20 OUT Y1
STP S22 Y2 STP S21
STP S21 OUT Y2
FROM S21
X2
TO S22 AND X2
X3 TO S22
X4 Y4 Y3 STP S22
STP S23 STP S22 OUT Y3
X3 FROM S20
X5 FROM S20 TO S23 FROM S22
AND X3
FROM S22 TO S23
X4 Y4 STP S23
STP S23 AND X4
X5 OUT Y4
TO S0 FROM S23
AND X5
STPEND TO S0
STPEND
【Description】: 1. When ON, the initial step S0 is ON. If X0 is ON, then Y0 will be ON.
2. When S0 is ON: if X1 is ON, then steps S20 and S21 will be ON simultaneously and Y1 and Y2 will
also be ON.
3. When S21 is ON: if X2 is ON, then step S22 will be ON, Y3 will be ON and S21 and Y2 will be OFF.
4. When S20 and S22 are ON at the same time and the transferring condition X3 is ON, then step S23
will be ON (if X4 is ON, then Y4 will be ON) and S20 and S22 will automatically turn OFF and Y1 and
Y3 will also turn OFF.
5. When S23 is ON: if X5 is ON, then the process will transfer back to the initial step, i.e. So will be ON
and S23 and Y4 will be OFF.
8-9
● STPEND :（Displayed in WinProladder）
or
STPEND :（Displayed in FP-07）
This instruction represents the end of a process. It is necessary to include this instruction so all processes can be
operated correctly.
A PLC can have up to 8 step processes (S0～S7) and is able to control them simultaneously. Therefore, up to 8
STPEND instructions can be obtained.
【Example】
WinProladder FP-07
M1924 ORG M1924

M1924 TO S0 TO S0
STP S0
STP S0 STP S0 ˙
˙
˙
STPEND STPEND STPEND
M1924 ORG M1924

TO S1 TO S1
M1924 STP S1
STP S1 ˙
STP S1 ˙
˙
STPEND
STPEND STPEND
ORG M1924
M1924 TO S7
TO S7
STP S7
M1924
˙
STP S7
STP S7
˙
˙
STPEND
STPEND
STPEND
【Description】 When ON, the 8 step processes will be active simultaneously.
8 - 10
8.4 Notes for Writing a Step Ladder Diagram
【Notes】
● In actual applications, the ladder diagram can be used together with the step ladder.
● There are 8 steps, S0～S7, that can be used as the starting point and are called the “initial steps”.
● When PLC starts operating, it is necessary to activate the initial step. The M1924 (the first scan ON signal) provided
by the system may be used to activate the initial step.
● Except the initial step, the start of any other steps must be driven by other step.
● It is necessary to have an initial step and the final STPEND instruction in a step ladder diagram to complete a step
process program.
● There are 980 steps, S20～S999, available that can be used freely. However, used numbers cannot be repeated.
S500～S999 are retentive(The range can be modified by users), can be used if it is required to continue the machine
process after power is off.
● Basically a step must consists of three parts which are control output, transition conditions and transition targets.
● MC and SKP instructions cannot be used in a step program and the sub-programs. It’s recommended that JMP
instruction should be avoided as much as possible.
● If the output point is required to stay ON after the step is divergent to other step, it is necessary to use the SET
instruction to control the output point and use RST instruction to clear the output point to OFF.
● Looking down from an initial step, the maximum number of horizontal paths is 16. However, a step is only allowed to
have up to 8 branch paths.
● When M1918=0（default）, if a PULSE type function instruction is used in master control loop (FUN 0) or a step
program, it is necessary to connect a TU instruction before the function instruction. For example,
S20
STP S20 C0
PV : 5
When M1918=1, the TU instruction is not required, e.g.:
STP S20 C0
PV : 5
8 - 11
Example 1
WinProladder FP-07
M1924 ORG M1924

M1924 TO S0 Net0 TO S0
X0 Y0
X0 Y0 STP S0
STP S0
STP S0 AND X0
X1 X1 X2 OUT Y0
TO S20 FROM S0
X2 X3 X4
Y1 Y2 X3 AND X1
STP S20 STP S21 TO S0 OUT TR 0
S0
X4 AND X2
X5 X6 Net1
TO S21 TO S20
LD TR 0
X7 Y1 AND X3
X11 Y3 STP S20 TO S0
STP S22 Y2 LD TR 0
STP S21 AND X4
X8
TO S21
X5 X7
FROM S20 TO S22
STP S20
X6 Net2
OUT Y1
FROM S21
X11 Y3 STP S21

Net3
STP S22 OUT Y2
X8 FROM S20
TO S0
AND X5
FROM S21
STPEND
Net4 AND X6
ORLD
AND X7
TO S22
STP S22
AND X11
OUT Y3
Net5
FROM S22
AND X8
TO S0
Net6 STPEND
Description 1. Input the condition to initial step S0
2. Input the S0 and the divergent conditions of S20, S0 and S21
3. Input the S20
4. Input the S21
5. Input the convergence of S20 and S21
6. Input the S22
8 - 12
Example 2
WinProladder FP-07
M1924 ORG M1924

TO S0 Net0
M1924 TO S0
X0 Y0 X0 Y0 STP S0
STP S0 STP S0
AND X0
X1 X1 X2 OUT Y0
TO S20
FROM S0
X2 X3 X3 AND X1
Y1 Y3 TO S22 Net1 OUT TR 0
STP S20 STP S22
Y1 AND X2
X4 X6 STP S20 TO S20
Y2
X4 LD TR 0
STP S21
TO S21 AND X3
X5 Y2 TO S22
STP S21 STP S20
OUT Y1
X7 Y3
X11 Y4 Net2 FROM S20
STP S22
STP S23 AND X4
X5 X7 TO S21
X8 FROM S21 TO S23
X6 STP S21
Net3
FROM S22 OUT Y2
X11 Y4
STP S22
STP S23 Net4
OUT Y3
X8
TO S0 FROM S21
AND X5
STPEND
FROM S22
Net5 AND X6
ORLD
AND X7
TO S23
STP S23
AND X11
OUT Y4
Net6
FROM S23
AND X8
TO S0
Net7 STPEND
2. Input the S0 and the divergent condition of S20 and S22
3. Input the S20
4. Input the S21
5. Input the S22
6. Input the convergence of S21 and S22
7. Input the S23
8 - 13
Example 3
WinProladder FP-07
M1924 ORG M1924
M1924 TO S0 Net0
TO S0
Y0
Y0
STP S0 STP S0
STP S0
OUT Y0
X1
TO S20 FROM S0
X1 X4 OUT TR 0
Y1 Y5 X4
TO S24 Net1 AND X1
STP S20 STP S24
TO S20
Y1
X2 X6 LD TR 0
STP S20
AND X4
Y2 Y3 X2
TO S21
TO S24
STP S21 STP S22
STP S20
TO S22 OUT Y1
X3 FROM S20
Y2 Net2
Y4 STP S21 AND X2
STP S23 TO S21
Y3
TO S22
X5 STP S22
X3 STP S21
TO S23 Net3
X7 FROM S21 OUT Y2
FROM S22 STP S22

Net4
Y4 OUT Y3
STP S23
FROM S21
Y5 FROM S22
STP S24 Net5
AND X3
X5 X7 TO S23
FROM S23 TO S0
X6 STP S23
FROM S24 Net6
OUT Y4
STPEND STP S24

Net7
OUT Y5
FROM S23
AND X5
FROM S24
Net8 AND X6
ORLD
AND X7
TO S0
Net9 STPEND
2. Input the S0 and the divergences of S20 and S24
3. Input the S20
4. Input the S20 and the divergences of S21 and S22
5. Input the S21
6. Input the S22
7. Input the convergences of S21 and S22
8. Input the S23
9. Input the S24
10. Input the convergences of S23 and S24
8 - 14
8.5 Application Examples
Example 1 Grasp an object from tank A and put it in Tank B
X0 : Start X1 : Left Limit X4 : Right Limit
LS LS
Y0 : Move Left
Motor Leadscrew
Y1 : Move Right
Y2 : Lift Up X2 : Upper Limit

Y3 : Stretch Down X3 : Lower Limit
Arm
Claw (Y4)
Tank A Tank B
M1924
STP S0 Return to the origin (claw released

at the left limit and the upper limit)
X0 Start
STP S20 Arm stretches downward
X3 Lower Limit
Stop stretching downward 1S delay to ensure the object is firmly grasped
STP S21
Claw grasps (after 1S) before being lifted up
T0 1S Delaly
STP S22 Arm lifts up

Upper Limit
X2
Stop lifting up
STP S23
Move arm to the right
X4 Right Limit
STP S24 Stop moving to the right

Arm stretches downwards
X3 Lower Limit
Stop stretching downwards 1S delay to ensure the object has been
STP S25 completely released before lifting the arm up
Release claw (after 1S)
T1 1S Delay
STP S26 Arm lifts up
X2 Upper Limit
Stop lift up
STP S27
Move arm to the left
X1 Left Limit
8 - 15
WinProladder FP-07
M1924 ORG M1924

TO S0 TO S0
STP S0
Y4 OUT TR 0
STP S0 Release claw OUT NOT Y4
X1 Y0 AND NOT X1
Return to the left limit OUT Y0
X2 Y2 LD TR 0
Return to the upper limit AND NOT X2
X0 OUT Y2
Turn the switch ON before moving to S20 FROM S0
TO S20
AND X0
Y3 TO S20
Stretch arm downward
STP S20 STP S20
Move to S21 after stretching to the lower OUT Y3
X3
TO S21 limit FROM S20
AND X3
Claw grasps (since the SET instruction is
TO S21
STP S21 EN SET Y4 used, Y4 should remain ON after departing
STP S21
from STP S21) SET Y4
EN T0 100 T0 PV: 100
T0 Divergent into S22 after 1S FROM S21
TO S22 AND T0
Lift the arm up TO S22
Y2 STP S22
STP S22 Divergent into S23 after reaching the upper OUT Y2
X2 limit FROM S22
TO S23 AND X2
Move arm to the right TO S23
Y1 STP S23
STP S23 Divergent into S24 after moving to the right
OUT Y1
limit FROM S23
X4
TO S24 AND X4
Stretch the arm downward
TO S24
Y3 Divergent into S25 after stretching to the STP S24
STP S24 lower limit OUT Y3
X3 FROM S24
TO S25 Release claw AND X3
TO S25
STP S25 EN RST Y4 Delay for 1S STP S25
RST Y4
EN T1 100 Transfer into S26 after 1S T1 PV: 100
FROM S25
T1
TO S26 Lift the arm up AND T1
TO S26
Y2 Divergent into S27 after reaching the upper STP S26
STP S26 limit OUT Y2
X2 FROM S26
TO S27 Move the arm to the left AND X2
TO S27
Y0 Divergent into S0 after moving to the left
STP S27
STP S27 limit (a complete cycle)
OUT Y0
X1 FROM S27
TO S0 AND X1
TO S0
STPEND STPEND
8 - 16
Example 2 Liquid Stirring Process
Empty Limit No Liquid Limit

Dried Liquid
Switch Switch
material
X1 X2
Value 1 Y5 Value Y7
CH0 : R3840
Weighing
Value 1 Y6 Clear
CleanWater
Water
Value Y9
Stirring Unit
Value 4 Y10
Finished Product
Outlet
Y8 Stirring X4
Electromagnetic Switch Motor Overload Switch
Input Points: Empty limit switch X1

No liquid limit switch X2
Empty limit switch X3
Over-load switch X4
Warning clear button X5
Start button X6
Water washing button X7
Warning Indicators: Empty dried material Y1

Insufficient liquid Y2
Empty stirring unit Y3
Motor over-load Y4
Output Points: Dried material inlet valve Y5

Dried material inlet valve Y6
Liquid inlet valve Y7
Motor start electromagnetic valve Y8
Clean water inlet valve Y9
Finished product outlet valve Y10
Weighing Output: CH0（R3840）
M1918=0
8 - 17
WinProladder FP-07
M1924 ORG M1924 STP S22
TO S0
TO S0 OUT Y7
X1
STP S0 SET Y1 STP S0 T1 PV: 800
X2
SET Y2 OUT TR 0 FROM S21
X3 AND NOT X1 FROM S22
SET Y3 Warning indicators
X4 SET Y1 AND T0
SET Y4
LD TR 0 AND T1
X5
RST Y1 AND NOT X2 TO S23
RST Y2 SET Y2 STP S23
LD TR 0 OUT TR 0
RST Y3
Reset warning AND X3 OUT Y8
RST Y4
SET Y3 LD TR 0
X6 Y1 Y2 Y3 Y4
TO S20 LD TR 0 T2 PV: 4500
X7 Y3 Y4 Production start AND X4 LD TR 0
TO S24
SET Y4 AND X4
Y5 Water washing start
LD TR 0 OUT Y4
STP S20
M0 AND X5 STP S24
17CMP
Sa : R3840 RST Y1 OUT TR 0
M1 Input weighing
Sb : R0 RST Y2 T3 PV: 500
M0 RST Y3 LD TR 0
TO S21 RST Y4 AND NOT T3
Status after weighing
M1
TO S22 FROM S0 OUT Y9
Divergent into S21 and S22
Y6 OUT TR 1 LD TR 0
STP S21
Input material to stirring AND X6 T4 PV: 1500
unit AND NOT Y1 LD TR 0

EN T0 500
AND NOT Y2 AND NOT T4
Y7
STP S22 AND NOT Y3 OUT Y10
AND NOT Y4 FROM S23
EN T1 800 TO S20 AND T2
T0 T1 Add liquid to stirring unit LD TR 1 FROM S24
FROM S21 TO S23
Complete dried material AND X7 AND T4
FROM S22 and liquid input, transfer AND NOT Y3 ORLD
Y8
the status to S23 AND NOT Y4 TO S25
STP S23
TO S24 STP S25
EN T2 4500 Stirring timer STP S20 OUT TR 0
X4 Y4 OUT Y5 AND X3
FUN 17 OUT Y10
STP S24 EN T3 500
Wash stirring unit Sa:R3840 LD TR 0
T3 Y9 Sb:R0 AND TU S25
Input clean water FO 0 FUN 15DP
EN T4 1500 OUT M0 D:R10
T4 Y10 FO 1 FROM S25
Drain water out
OUT M1 AND NOT X3
T2
FROM S23 TO S25 FROM S20 TO S0
T4 LD M0 STPEND
FROM S24
Y10 OR M1
X3 Output finished product
STP S25 ANDLD
S25 15DP and accumulate the cycle TO S21
+1 R10
TO S22
X3
TO S0 STP S21
STPEND OUT Y6
T0 PV: 500
8 - 18
Example 3 Pedestrian Crossing Lights
Y0
Y0(Red)
(Red) Y3
Y3(Red)
(Red)
Y1
Y1(Amber)
(Amber)
Y2 (Green)
Y2 (Green)
Y4
Y4(Green)
(Green)
X1
X1
Y4
Y4
(Green)
(Green)
X0
X0
Input Points: Pedestrian Push Button X0 Output Points: Road Red Light Y0
Pedestrian Push Button X1 Road Amber light Y1
Road Green Light Y2
Pedestrian Crossing Red Light Y3
Pedestrian Crossing Green Light Y4
M1918=0
8 - 19
● Pedestrian Crossing Lights Control Process Diagram
M1924
Y2
STP S0 Road Green Light
Y3
Pedestrian Crossing Light
X0 X1 Pedestrian Push Button
Y2 Y3
Pedestrian Crossing
STP S20 STP S30 Red Light
Road Green Light
T0 T0 3000 T2
Y1 Y4
Pedestrian Crossing
STP S21 Road Amber Light
STP S31 Green Light
T1 T1 500 T3 T3 2000
Y0
STP S22 STP S32 T4 100
Road Red Light
T2 500 T4
Y4
Pedestrian Crossing
STP S33 Green Light BLink
S33
C1
PV : 6
T5 100
C1 C1
T5 T5
Y3 S32
STP S34 Pedestrian Crossing
Red Light
RST C1
T6 100
T6
8 - 20
● Pedestrian Crossing Lights Control Program
WinProladder FP-07
M1924 ORG M1924 STP S32
TO S0
TO S0 T4 PV: 100
Y2
STP S0 STP S0 FROM S32
Y3
OUT Y2 AND T4
X0 OUT Y3 TO S33
TO S20
X1 FROM S0 STP S33
TO S30
LD X0 OUT TR 0
Y2
STP S20 OR X1 OUT Y4
ANDLD LD TR 0
EN T0 3000
TO S20 AND TU S33
T0
TO S21 TO S30 LD OPEN
Y1 STP S20 C1 PV: 6
STP S21
OUT Y2 LD TR 0
EN T1 500 T0 PV: 3000 T5 PV: 100
T1
TO S22 FROM S20 FROM S33
Y0 AND T0 OUT TR 1
STP S22
TO S21 AND NOT C1
EN T2 500 STP S21 AND T5

Y3 OUT Y1 TO S32
STP S30
T1 PV: 500 LD TR 1
T2
TO S31 FROM S21 AND C1
Y4 AND T1 AND T5
STP S31 TO S22 TO S34
EN T3 2000 STP S22 STP S34

T3 OUT Y0 OUT Y3
TO S32
T2 PV: 500 RST C1
STP S32 EN T4 100 STP S30 T6 PV: 100
T4
TO S33 OUT Y3 FROM S22
Y4 FROM S30 FROM S34
STP S33 AND T2 AND T6
S33 TO S31 TO S0
C1
PV : 6
STP S31 STPEND
OUT Y4
EN T5 100 T3 PV: 2000
C1 T5
TO S32 FROM S31
C1 T5 AND T3
TO S34
TO S32
Y3
STP S34
RST C1
EN T6 100
T6
FROM S22 TO S0
FROM S34
STPEND
8 - 21
8.6 Syntax Check Error Codes for Step Instruction
The error codes for the usage of step instruction are as follows:
E51 : TO(S0-S7) must begin with ORG instruction.
E52 : TO(S20-S999) can't begin with ORG instruction.
E53 : TO instruction without matched FROM instruction.
E54 : To instruction must comes after TO, AND, OR, ANDLD or ORLD instruction.
E56 : The instructions before FROM must be AND, OR, ANDLD or ORLD
E57 : The instruction after FROM can't be a coil or a function
E58 : Coil or function must before FROM while in STEP network.
E59 : More than 8 TO# at same network.
E60 : More than 8 FROM# at same network.
E61 : TO(S0-S7) must locate at first row of the network.
E62 : A contact occupies the location for TO instruction.
E72 : Duplicated TO Sxx instruction.
E73 : Duplicated STP sxx instruction.
E74 : Duplicated FROM sxx instruction.
E76 : STP(S0~S7) without a matched STPEND or STPEND without a matched STP(S0~S7).
E78 : TO(S20~S999), STP (S20~S999) or FROM instructions comes before or without STP(S0~S19).
E79 : STP Sxx or FROM Sxx instructions comes before or without TO Sxx.
E80 : FROM Sxx instruction comes before or without STP Sxx.
E81 : The max. level of branches must <=16.
E82 : The max. no. of branches with same level must <=16.
E83 : Not place the step instruction with TO->STP->FROM sequence.
E84 : The definition of STP# sequence not follow the TO# sequence.
E85 : Convergence do not match the corresponding divergence.
E86 : Illegal usage of STP or FROM before convergent with TO instruction.
E87 : STP# or FROM# comes before corresponding TO#.
E88 : During this branch, STP# or FROM# comes before the corresponding TO#.
E89 : FROM# comes before corresponding TO# or STP#.
E90 : Invalid To# usage in the simultaneous branch.
E91 : Flow control function can not be used in the step ladder region.
8-22
Appendix 2： FBs BDAP User’s Manual
T he f unc t io n o f th e d ata ac c es s boa r d ( F Bs- BD AP ) is ma in ly u s ed f or d is p la y in g a nd
se ttin g o f th e ca le ndar time a nd d iscre te and re gister d ata o f PLC . For the d iscre te
e le men ts , us er can per form the d isa ble or e nab le func tion als o ca n se t or res e t its s ta te.
F or th e r eg is ters , t he c on te nts c a n be s et a nd d is p la y ed in u ns ign ed or s ign ed d ec i ma l
for ma t a nd he xadec imal forma t. T his u nit sh ou ld be moun ted on th e PLC main un it wh ile
i n s ta ll .
1.1 FBs BDAP Function Description

T her e are so me n ota tions w ere re ferre d in fo llow ing s ec tions and d escribed a t be low :
【 T】 : C ur r e n t va lue a nd o n /o ff s ta tus o f tim er
【 C】 : C u r r e n t va lue a nd o n /o ff s ta tus o f c o un ter
【 D】 : D a ta r eg is ter ( D t yp e)
【 R】 : D a ta r eg is ter ( R t yp e)
【 F】 : F ile re gis ter
【 X】 : D is c r e t e Inp u t ( D I)
【 Y】 : D is c r e t e Ou t pu t( D O)
【 M】 : In ter na l re la y
【 S】 : Step r el a y
F ea ture Descr ip tio n

Ca le ndar Fu nc tion* 1
D is p la y D is p la y c ur r e n t Year, M on th , D a te , H our a nd mi nu te da ta
Se tting Se t Year, Mon th , D a te , H our a nd minu te da ta
Sta tus D isp la y Func tio n
D is p la y the s ta t e an d en ab le /d isa bl e s ta t us o f X,Y,M,S
D is c r e te E le men t
e le men t
D is p la y the c ur r e n t va lu e o f T, C , D , R , F r e gis t er. Thr ee
1 6 b i t R eg is ter d isp la y for ma ts (u ns ign ed /s ign ed /h e xadec imal) can be
ch osen .
D is p la y the c ur r e n t v a lu e o f C , D , R , F r e gis t er. Thr ee
3 2 b i t R eg is ter d isp la y for ma ts (u ns ign ed /s ign ed /h e xadec imal) can be
ch osen .
F or c e On /O ff Func t ion F or c e t he s ta te o f X , Y, M , S t o be On or O ff
D is ab le / Ena bl e Fu nc tio n C o n tr o l the s ta te o f X , Y, M , S t o b e en ab led or dis ab led
Register Content Modification
Function
Mod i fy the curr en t value o f T, C, D , R , F re gis ter. Thre e
1 6 b i t R eg is ter
d isp la y for ma ts (u ns ign ed /s ign ed /h e xadec imal) can be
ch osen .
M od i f y t he c ur r e n t va lu e o f C , D , R , F r e gis t er. Thr ee
3 2 b i t R eg is ter
d isp la y for ma ts (u ns ign ed /s ign ed /h e xadec imal) can be
ch osen .
Se tting and D isp la y o f PLC
D is p la y a nd s e t the PLC s ta t io n n umb er.
Sta tion Number Func tion
F or c e PLC R u n /Stop F orce the PLC to ru n o r s top log ic solving and I/O
F unc tion ser vice.
Appendix 2 -1
1.2 FBs BDAP Display Legend
① “RUN” indicator. When the PL C is in running s tate, this s ymbol w i ll be appeared.

② “ STO P” ind ic a t or. W h en th e P LC is i n s t o p s ta te , th is s ym bo l w il l b e ap pe ared .
③ “ ON ” ind ic a t or. W he n the s el ec te d e lem en t is Tim er or C oun t er, t h is s ym bo l w il l b e
a ppe ared w h en th e c or r esp ond in g s ta te is o n .
④ “ O FF” in dic a tor. W h en th e s e lec t ed e le me n t is Ti mer o r C ou n ter, th is s ymb ol w i ll be
a ppe ared wh en th e cor resp ond in g sta te is o ff.
⑤ “ D ” indi c a tor s . W he n the s el ec te d e lem en t is 3 2 b i t r e gis t er, the “ D ” s ymbo l w il l b e
a ppe ared .
⑥ Ele men t s ymbo ls for s elec tio n . Th ere ar e n ine ele men t types ca n be ch osen , those
ar e T , C , D, R , F , X, Y, M and S.
⑦ Re fer enc e nu mber o r year disp la y, The se que nce n umb er o f th e se lec ted eleme n t or
th e year par t o f the calen dar .
⑧ Value d isp la y or h our a nd minu te d isp la y. For 16 b i t re gis ter, it rep resen ts the
c ur r en t v alu e o f 1 6 b it c o n ten t . F or 3 2 b i t r e gis t er , i t r e prese n ts th e por t io n o f t he
n umb er a bo v e 5 t h d ig it ( million) in dec ima l or M SB word in he xa dec imal format. It
a ls o r epr ese n ts the s ta t e o f d is c r e t e e lem ent or hou r an d m inu t e p ar t o f th e
ca le ndar .
⑨ V al ue d is p la y or m on th and d a y d is p la y. F or 3 2 b i t r e gis t er , i t r e pres en ts t h e l ow er 5
d ig i t p or tion o f the number in dec ima l o r L SB wor d in he xadec imal for ma t. It a lso
r e pres en ts t h e en ab le /d isa bl e s tate o f d is c r ete el eme n t or mo n th an d da y par t o f t he
ca le ndar .
Appendix 2-2
1.3 FBs BDAP Operation Procedure
O pera t io n K e ypa ds : Th ere a r e s ix k e ypads in t otal f or o pera t io n .
ESC : Escape key
OK : OK key
－ : “－ ” k e y
＋ : “＋ ” k e y
Æ : “Æ” k e y ( s h i ft r ig h t)
Å : “Å” key(shift left)
Default display mode: Calendar Display
○
1 Select the field to be changed, selected field will be blinked
○
2 En te r the n ew va lue
○
3 E n t e r s ta t u s m o n i t o r i n g d i s p l a y s c r e e n
○
4 U s e Å key、 Æ k e y s e lec t t h e e le me n t t y p e t o b e m o n it o r in g . T h e s e lec t e d typ e w i l l b e
b l ink e d .
○
5 U n d e r c a l e n d a r d i s p l a y m o d e , p r e s s ＋ k ey t o f or c e P LC s to p or r un
Appendix 2 -3
⑥ U n d e r c a l e n d a r d i s p l a y m o d e , p r e s s － k e y t o dis p la y a nd m od i f y t h e P L C s t a ti o n
n umb er
⑦ U n d e r c a l e n d a r d i s p l a y m o d e , p r e s s Å key, can display the fi rmw are vers ion of PLC
a nd BD AP.
No te : No ma tter a t wh ich d ispla y scr een, p ress < ESC> w i th 2 seco nds w i ll lead th e
scre en to ca le ndar disp la y.
Discrete Element Monitoring:
○
1 D i s c r e t e e l e m e n t ( X、Y、M、S) display screen show five consecutive points of status at one time. The
u pper row is o n /o ff s tatus w hile th e lower r ow is d isab le /ena ble s ta tus .
○
2 Element reference number adjust
＋ key: I n c r e a s e t h e r e f e r e n c e n u m b e r b y 5
－ key: D e c r e a s e t h e r e f e r e n c e n u m b e r b y 5
○
3 E n t e r t h e e l e m e n t s ta t u s e d i t i n g s ta t e . T h e s e l e c t e d p o i n t w i l l b e b l i n k e d .
○
4 M o d i f i c a t i o n o f e l e me n t ON /O FF、 Enab le /D isab le s tatus
＋ key: Ch ang e the ON /OF F sta tus( tog gle o pera tio n)
－ key: C h ang e the E na bl e /Disa bl e s ta tus( to gg le o pera t io n)
Æ key: M o v e c u r s o r t o t h e l o w e r p o i n t t o b e e d i t e d ( d e c r e a s e t h e r e f e r e n c e n u m b e r )
Å key: M o v e c u r s o r t o t h e h i g h e r p o i n t t o b e e d i t e d ( i n c r e a s e t h e r e f e r e n c e n u m b e r )
○
5 Finish the editing.
Appendix 2-4
Timer/Counter Status Monitoring:
○
1 T h e c u r r e n t v a l u e o f T, C e le me n t i f r e a c h t h e p r e s e t v a l u e w i l l s h o w ” ON” , o therw ise
w il l s h o w ” O FF”
○
2 Reference number adjust
＋ key: Re ferenc e nu mbe r decre ased b y on e
－ key: R e f er enc e nu mbe r i nc r e as ed b y on e
○
3 Enter editing mode. The digit to be changed will be blinked.
○
4 M od i f y va lu e
＋ key: I n c r e a s e d b y o n e
－ key: D ec r ease d by o ne
Æ key: Move to the right digit
Å key: Move to the left digit.
○
5 Finish the editing and increase the reference number by one and back to ○
1
※ Wh en mon itor in g the co un ter ele men t, if th e re fer ence n umber is grea t th an 200
th en th e d isp la y value w ill b e in 3 2 b i t for ma t(C 200~C2 55 ar e 32b it co un ter)
※ W h e n mon it o r in g th e ti me r e le me n t , t h e d e ci ma l p o in t o f c u r r e n t v a lu e w i l l b e s e t
acc ord ing l y.
Appendix 2 -5
Register Status Monitoring:
○
1 Default unsigned 16 bit decimal value display
○
2 A d jus t th e r e f er e nce n umb er a nd s el ec t the dis pl a y for ma t
＋ key: I n c r e a s e t h e r e f e r e n c e n u m b e r b y o n e w h e n 1 6 b i t d i s p l a y f o r m a t , b y t w o
when in 32 bit display format.
－ key: D e c r e a s e t h e r e f e r e n c e n u m b e r b y o n e w h e n 1 6 b i t d i s p l a y f o r m a t , b y t w o
when in 32 bit display format.
Æ key: Display format selection. There are signed decimal, unsigned decimal and hexadecimal display format can
be selected. Each depression of Æ k e y can ch ange the for mat once.
<1 6 b i t he x ad ec i ma l d is p la y>
<1 6 b i t s i gne d dec im al d is p la y>
Å key: 1 6 bi t / 32 b i t d is p la y f or ma t s el ec t ion , Each depression of Å k e y will togg le the

d isp la y forma t b e tw een th es e two mo d es .
<3 2 b i t uns ig ned dec imal>
< 3 2 b i t he x ad ec i ma l d is p la y>
Appendix 2-6
< 3 2 b i t s i gne d dec im al d is p la y>
○
3 E n te r ed i ti ng mod e . T he d ig i t to be e di t ed w il l b e b link ed .
○
4 M od i f y d ig i t va lu e
＋ key: Increased by one
－ key: Decreased by one
Æ key: Move cursor to the right digit
Å key: Move cursor to the left digit
○
5 F in is h t he e d i tin g a nd au to ma t ic a l l y po in t t o t he ne x t a v a ila bl e r e f er enc e nu mbe r the n
b ac k to ○ 1
Appendix 2 -7
Appendix FB-DAP Simple Human Machine Interface
In addition to timer, counter, register, and contact data access function, the date setter of FB-DAP can connect to
many others for alarm message display, self-defined buttons, wireless card reading, and the like simple human-machine
(HM) functions.
FB-DAP Simple HM
Model
FB-DAP-A(R) FB-DAP-B(R)
Spec.
Display LCD (English version), 2-line×16-character, LED backlight
Button 20-key (4×5)
Wireless Card reading −AR and−BR only，distance 12～18cm
Power supply 5V 24V
Current consumption 100mA (120mA) 41mA (48mA)
Com. Interface HCMOS RS-485
Service points
Single set Max. 16-set connected
connected
PLC Com. Port port 0,1,2 (In which port 0 and 1
port 0
connected needed to be converted as RS-485)
General feature Timing/counting、register、contact access(write protected for each)
Special feature Alarm、message display、self-definition of special speed keys
Card writing feature Order for machine types with special numbers to us is required
※ PLC’s MA、MU type machines can be connected to FB-DAP-B(R) only through FB-485 switch.
Wireless sensing card
Model
CARD-1 CARD-2
Spec.
Memory 64bits with Cyclic Redundancy Check (CRC) on data
Operation temp. −25°C～50°C (conforming to ISO7810)
Battery not required (power supplied from wireless electric waves released by an
Power supply
−AR/−BR card-reading module)
Sensing distance 12cm～18cm(from FB-DAP front)
Number of writing unwritable(uncopiable，exclusively) 10000 times at least
Size (mm) 86×54×13
Weight (Gram) 12
Appendix -1
1.1 Profile
112
7 98 7 16 外徑 4ψ×4 埋螺帽
6.5 8
14.8
FB-DAP DATA ACCESS PANEL 30
FATEK
1.5
Lateral
Front
Back
X + ON / OFF FUN
148 148
118.45
T 7 8 9 CLEAR
Y E F ADR / DOC
C 4 5 6
M A B DEC / HEX
D 1 2 3
S W CV / PV 22.43
R 0 SHIFT ENTER
14.75
102.5 12 17.6
4.75 9.9
1.2 Important points before operation
1、 FB-DAP possesses a function to return to the operation mode (general data setter and self-definition 8/16
speed keys) before power failure and each DAP can be place in a different mode when connecting many sets.
2、 When operating FB-DAP，D2944～D3071 register of PLC will be used as the systematic architecture zone (in
which data set by all the FUN functions can be stored except item 11) , the user shall avoid this zone.
3、 Any communication port, once converted to a RS-485 interface (port 2 is itself a RS-485 interface), can be
connected to a maximum of 16 FB-DAP-B(R) sets.
PLC port0 B FB-485P0 switch head B RS-485 interface

Only thus so the FB-DAPB (R) can
(HCMOS)
be connected to.
B FB-485 switch B RS-485 interface
PLC port1
(RS-232)
4、 When PLC is connected with FB-DAP-B(R)，the service point numbers of PLC are limited to a range of 1~32.
5、 Parameters for the connection between PLC and FB-DAP-B(R)(DAP automatic detection Baud Rate 9600 /
19200 / 38400)
port0、1、2：9600 / 19200 / 38400、Even、7Data bits、1Stop bit
ex：R4158=5521H, i.e. port2 being 9600；R4158=5523H, i.e. port2 being 38400.
6、 When many sets of DAP are connected, if any two or more have the same service point number, then DAP will
request for number change, which can be done by only entering〝 new DAP 〞即可。
7、 The transmission line of the RS-485 interface must use a twisted pair with a shielded cover on the outer layer.
Please refer to chapter 12-5 in the Operation Manual II for other important points.
8、 The scanning time of PLC will affect the update time of DAP.
9、 The OS of FB-DAPB(R) shall be new V2.00 above PCB so that multiple sets can be connected. Press
then the OS version is displayed.
10、 When PROLADDER(or FP07) and DAP are connected to the same set of PLC, to change the program
through PROLADDER is not allowed; if so, the timer information displayed by DAP won’t be correct (In this
Appendix -2
case, the DAP shall be reset).
11、Versions after the OS V3.15 (including) of FP-07 can be aimed for DOCs in 16 words of contacts, registers.
1.3 The Main Functions of FB-DAP

The main functions of FB-DAP can be categorized as： setter functions of general information, FUN functions of
parameter setting, wireless card reading, and message display function. The details of the functions will be introduced in
the following sections.
1.4 Setter Functions of General Information
FB-DAP can be used as a 〝TC setter〞as well as the access to registers (R、D、W) and contacts (X、Y、M、
S). In the FUN functions in the following sections, it can also be used as write-protect with T、C、R、D、X、Y、M、S. There
are two measures to monitor information: ADR (general addresses) and DOC monitoring. The latter shall make DOC
compilation (16 words in English, symbols, numbers) in advance through Proladder or FP07 for T, C, register R/D and
contacts so the DOC can be displayed.
1、 ADR Monitoring
A. Timer and Counter Monitoring
【Pressing Keys】： or number
T or C number Cursor position

↓
    ← Set value

   ← Current value
↑ ↑
Status FB-DAP automatic detecting a decimal point position
B. Registers (R、D、DR、DD、WX、WY、WM、WS) and contacts (X、Y、M、S) monitoring
【Monitored range】
Type T C D R DD DR WX WY WM WS X Y M S
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Range | | | | | | | | | | | | | |
255 255 2943 8071 2492 8070 240 240 1984 984 255 255 2001 999
【Pressing keys】： or
+( or )
number +
+ ( or or or )
( or or or )
Cursor position Value

↓ ↓
  ← Item 1

  ← Item 2
↑
Status
Appendix -3
〝H〞 indicates hexadecimal
↓
    ※ WX、WY、WM、WS can display one item only but each
 pressing status is available.
↑ ↑
Y15 Y0
Note：1、Pressing can move the cursor up and down or switch between CV or PV.
2、Pressing or can decrease or increase the monitored item number.
3、For a monitored item value, input a new value directly and then press . The status of the
contacts can be changed by pressing + .
4、Pressing + can change the means to display a value (either with decimal or hexadecimal
system).
2、 DOC monitoring
  ← DOC of T10

   ← Current value
↑
Contact status
  ← Register DOC

  ← Value
Note：1、Pressing + can switch the monitoring of ADR and DOC.
2、The display switch between CV (current value) and PV of the timer (counter) can use .
3、 or can be moved up or down to next monitored item with DOC.
3、 Speed monitoring FUN keys(FUN KEY 0～9, totaling 10 keys)
【Pressing keys】： + ( ～ ) B Direct display of a monitored item set by the client.
Note：1、Items to be monitored can be set from the following “FUN functions”.

2、Items to be monitored can be displayed with general or DOC means.
Appendix -4
1.5 FUN Functions
1.5.1 In and out of FUN functions

■ Enter FUN functions
Press + + 1、 PASSWORD OPEN (Password open)
2、 PASSWORD CLOSE (Password blocked)
3 、 PASSWORD SET (Password setting)
4、 DEFINE FUN KEY (Self-define speed monitoring function key FUN KEY 0-9)
Press 5 、 DEFINE ALARM (Self-define start address of content for display at an alarm)
ADDRESS
6、 DEFINE SOFTKEY
(Self-define 8 special keys)
(8-KEY)
＊ 7、 DEFINE SOFTKEY
(Enter into the modes of the 8 special keys)
MODE (8-KEY)
8、 DEFINE SOFTKEY
(Self-define 16 special keys)
(16-KEY)
＊ 9、 ENTER SOFTKEY
(Enter into the modes of the 16 special keys)
MODE(16-KEY)
○
10、 VOLUME (Adjust volume)
11、 SET DAP NO. (Set DAP number (s) at multi-link)
○ 12、 MAX. DAP NO.

(Set the max. DAP numbers on network (1-16) at multi-link)
ON NETWORK(1~16)
○
13 、 WRITE PROTECT (Data write-in protection)
○
14、 RF CARD MODE (RF card mode selection)
○ 15 、 RF CARD (Start address of a RF card number storage)

START ADDR.
＊ 16、 ENABLE (Corresponding special contacts of ENABLE keys)

KEYS MAPPING
＊： Indicates when multiple DAPs are connected, each DAP can be set respectively.
○ ： Indicates when multiple DAPs are connected, the information set by one of them is not available for use until PLC is reset.
■ Exit of FUN functions to general information setter functions. Press ＋＋ Monitored items ＋
Note：1、When several DAPs are connected, information can be stored to PLC (D2944～D3071) if one of the DAP is set in
all the FUN functions (except item 11).
2、After entering FUN 4~15, without password protection, all the FUN functions can be executed by only pressing
. With password protection, it is required to pass it first before executing FUN functions.
3、If it is password-protected, FB-DAP will be set in a password protection status at each beginning of operation.
4、FUN items 1~9 can be entered with numeric keys directly and then go straight to that function.
5、 After executing a item of FUN functions, if execution of other items is required, press the three keys
+ + again.
Appendix -5
1.5.2 FUN function description
z FUN 1～3（password）
1、 Password contains up to 4 digits（unrelated to LADDER program’s password）.
2、 After the password is set, it will enter a password-locked status once it is started.
3、 After the password is locked, all the FUN functions are not available.
z FUN 4（DEFINE FUN KEY）：Self-setting speed monitoring function keys
4、 DEFINE FUN KEY FUN KEY 0

> T 10 〈 ADR〉
、
…
FUN KEY 9
> R1000 〈 DOC〉
1、 There are ten self-setting speed monitoring function keys in total.

2、 All items available for monitoring can be defined in the ten function keys.
3、 Pressing + can select ADR or DOC.
z FUN 5（DEFINE ALARM ADDRESS）：The address for display at self-setting an alarm.
1. There are ten start addresses, that is, ten levels of alarm signals.
2. All items available for monitoring can be defined in the said ten start addresses.
3. Pressing + can select ADR or DOC for display.
4. Control measures of alarm signals for display are shown as follows：
【Corresponding list for control】
Alarm level
Control contact Indication register Start address of the content displayed
（priority sequence）
ALARM 0 M1900 R3820 Client-defined
……
……
……
……

【Example】Assume the start address of ALARM 0 displayed content to be R100,
If M1900=1 then the alarm address for display is R100 +（R3820）
If R3820=0 Ö Display address or DOC of R100

R3820=1 Ö Display address or DOC of R101
R3820=2 Ö Display address or DOC of R102
Note 1：When a multi-level alarm occurs, only the address or DOC with priority can be displayed. The
address or DOC of a sub level alarm will not be displayed until this alarm with priority is released.
Note 2：To display a DOC (message) with 16 digits above, the corresponding indication register (R3820～
R3829) content can be changed anytime to reach this purpose.
Note 3：M1911 can control whether to sound the alarm buzzer. If M1911=0 (preset), it shall be activated.
Appendix -6
z FUN 6（DEFINE SOFTKEY－8 KEYS）：Self-defining 8 soft keys
FUN 7（ENTER SOFTKEY MODE－8 KEYS）：Enter 8 soft key mode
1. Can self-define 8 soft keys：、、、、、、、
2. Definable range：R0～R3839、D0～D2943、M0～M1899.
3. In defining M0～M1899, this key can be defined as one of the 5 modes.
Mode Definition Description

0 Set （S） Set this contact to 1
1 Reset （R） Set this contact to 0
2 Moment （M） 1 in pressing, 0 in being released
3 Inverse （I） Pressing once will have one inverse phase.
4 Monitor （V） Monitor this contact
【Example】 Assume definition as R0, definition as M0 mode 0(Set). Once enter the 8 soft key
mode in function 7,
Then pressing Ö display address or DOC of R0.
Ö display address or DOC of M0 and force M0 ON
Note 1：After defining the 8 soft keys, once function 7 is executed, it will enter 8 soft key operation mode.
And then the 8 soft keys will be executed according to function 6 definitions.
Note 2：、 both are allowed out of definition, but the other keys will not be effected without
definition.
Note 3：To return to normal operation mode, press〝 +（D2972 content）+ 〞, among which
D2972 content is from 0000～9999（4 digits required）.
z FUN 8（DEFINE SOFTKEY－16 KEYS）：Self-define 16 soft keys

FUN 9（ENTER SOFTKEY MODE－16 KEYS）：Enter 16 soft key mode
1. Available for defining 16 soft keys：、、、、、、～
2. Definable range：T0～T255、C0～C199、R0～R3839、D0～D2943、M0～M1899。
3. In defining M0～M1899, this key can be defined as one of the 5 modes and when a message is being
displayed, if the key is pressed, the display will not be changed.
Mode Definition Description

0 Set （S） Set this contact to 1
1 Reset （R） Set this contact to 0
2 Moment （M） 1 in pressing, 0 in being released
3 Inverse （I） Pressing once will have one inverse phase.
4 Monitor （V） Monitor this contact
4. When defined as T, C, R or D, the value change is by pressing or to make the corresponding

M1840～M1871 ON (the client is required to write a plus/minus 1 program in the LADDER program) to achieve
this purpose.
Soft
key 0 1 2 3 4 5 6 7 8 9 T C D R SHIFT
× M1840 M1841 M1842 M1843 M1844 M1845 M1846 M1847 M1848 M1849 M1850 M1851 M1852 M1853 M1854 M1855
Ø M1856 M1857 M1858 M1859 M1860 M1861 M1862 M1863 M1864 M1865 M1866 M1867 M1868 M1869 M1870 M1871
Appendix -7
【Example】Assume definition as R0, defined as M0 mode 1 (Reset).
After entering 16 soft key mode in function 9,
Press Ö Display the address or DOC of R0, and then pressing , its corresponding
M1850 will be ON; OFF after it is released.
Ö Display the address or DOC of M0 and force M0 OFF.
Note 1：After the 16 soft keys are defined, once function 9 is executed, it will enter 16 soft key operation mode
and then the 16 soft keys will be executed according to function 8 definition.
Note 2：to return to normal operation mode, press〝 +( + + + )+ 〞。
z FUN 11（SET DAP NO.）：When several sets are connected, set DAP number.
After any communication of FB-PLC is converted to RS-485 interface (Among which port2 as such is a
RS-485 interface), the FB-DAP-B(R) of the 16 sets can be connected. Each DAP shall need a unique number,
1~16 (but one of them must be number 1). This DAP is not related to PLC numbers, meaning the number can have
the same PLC number.
z FUN 12（MAX. DAP NO. ON NETWORK）

：when several sets are connected, set the biggest DAP number on the Web.
（Max. 16 DAPs, preset 7）
In a connection of several sets, FB-PLC can be joined with new DAPs. But the more the DAP number, the
longer the time to update information of each DAP. As a result, set the DAP number (the DAP number can not be
bigger than this number) on the Web appropriately will decrease time for information to update.
z FUN 13（WRITE PROTECT）：Information write in
Aimed for monitored items (T, C, R, D, Y, M, S), set the information in write-in protection separately. Just fill
in the corresponding place with 1, and then the item is write-in protected and can be read values only.
z FUN 14（RF CARD MODE）：Wireless card reading options
z MODE=〝0〞 Ö When reading a RF card, it will display whether this card is OK or Error. When the RF card is out of
sensing distance, it will pop up 〝NEXT〞, indicating another RF card is available now.
MODE=〝1〞 Ö once a RF card is read, it will beep once and will not display any information so the
sensing speed can be faster. But when many DAPs are connected, this mode will increase
by about 60mS to each set for monitored item information.
z FUN 15（RF CARD START ADDR.）：Start addresses storing the wireless RF card numbers
Store a card number’s address can be set through the function, ranging from D0~D2860 (preset to D2860).
Please refer to the Wireless Card Reading Functions in 1.6 for detailed description.
z FUN 16（ENABLE KEYS MAPPING）：Corresponding special contact of Enable key
After this function is set to 〝Enable〞 and enter SOFTKEY MODE（8KEYS and 16KEYS）, pressing a
definable soft key will force ON some contact of a corresponding contact under its number and the other contacts
become OFF. When set to “Disable”, the corresponding special contact of this DAP will not be effected.
Appendix -8
The following is corresponding special contacts to different DAP keys when in 16 KEYS MODE:
KEY 7 4
T C D R 1 0 8 5 2 SHIFT 9 6 3
No. （↑）（↓）
1 M1784 M1785 M1786 M1787 M1788 M1789 M1790 M1791 M1792 M1793 M1794 M1795 M1796 M1797 M1798 M1799
In 8KEYS MODE, only 8 keys 、、、、、、、 are effective, i.e.
number keys ineffective. And 、 take the positions of and , but it must be when both
keys are defined as soft keys so that the corresponding special contacts are effective.
〈Example〉 No.2：Pressing , Ｍ1768 is ON and M1769～M1783 OFF.
No. 5：Pressing , Ｍ1722 is ON and other contacts M1720～M1735 OFF.
1.6 Wireless card reading functions
z An applicable RF card is an exclusive read-only card (RF-CARD-1) or readable/writable card （RF-CARD-2）,

in which the card number of the read-only card is unique ( with 16 0~F digits), not repeatable and copyable.
And card numbers read by FB-DAP-AR(BR) shall be encoded with high security.
z The sensing distance of a RF card generally is 12～18cm, but shall be kept away from electromagnetic
wave interference source or high voltage power line.
z Readable/Writable cards （RF-CARD-2）can use Fatek’s FB-DAP-W in special sequence numbers to write in
card numbers. The card numbers are all encoded and relate to machine sequence numbers (the first 4
codes are the machine’s sequence number, the last 12 codes defined by the client). Only through Fatek’s
FB-DAP-A(B)R can a correct numbers be read. Under FUN function 17, FB-DAP-W can be input 12 0~F
digits or use 、 to change the card number. Finally, only place the distance of RF-CARD-2
within FB-DAP-W 12cm and then press , so that the card number can be written into RF-CARD-2.
Appendix -9
z Locations and application of the card number storage
FB-DAP saves RF card numbers within sensing distance into two places in PLC. The places and application are
described as follows:
4、Fixed in R3835～R3839（totaling 5 registers）：During operation, M1910 shall be controlled.
Card number
format
R3835 N1 N2 N1：DAP number 1～16（i.e. 1H～10H）
R3836 ×××× N2：52H（R：read-only card） or 57H（W：readable/writable card）
R3837 ×××× R3836～R3839 store 16 0~F card numbers
R3838 ××××
R3839 ××××
Application：
Only in monitoring (or8/16 soft keys) mode (non-FUN functions) and the RF card in sensing distance,
FB-DAP（−AR or −BR）will send the RF card number together with DAP number to PLC R3835～R3839. In
mode 0 of function 14 （RF CARD MODE）, all the client needs to do is compare the card number. If it is
OK, only set M1910 to 1 and then DAP will indicate “OK”, or “ERROR”. When the RF card is out of sensing
distance, DAP will pop up “NEXT” and clear the content of PLC R3838～R3839 to 0, which means
available for another RF card. In mode 1 of function 14, as soon as DAP reads a card number, it will save
it to R3835～R3839 with a beep. After the RF card exits, the 5 registers remain unchanged.
Applicable occasions：
Where one set or multiple sets are connected but RF cards are not used frequently, the program to be
applied will be a lot easier. But in the event of a card number read from different DAPs at the same time, it
will be difficult for PLC to identify the information correctly.
5、Preset D2860～D2939 (16 differently-located DAP take on 5 registers individually, i.e. 80 registers in all, but the
locations can be changed through function 15) control one point of M1880～M1895 separately when in use.
Card number Card number Card number Card number

format format format format
D2860 N1 N2 D2865 N1 N2 D2870 N1 N2 D2935 N1 N2
D2861 ×××× D2866 ×××× D2871 ×××× D2936 ××××
D2862 ×××× D2867 ×××× D2872 ×××× ……….. D2937 ××××
D2863 ×××× D2868 ×××× D2873 ×××× D2938 ××××
D2864 ×××× D2869 ×××× D3974 ×××× D2939 ××××
No. 1 No. 2 No. 3 No. 16
⇓ ⇓ ⇓ ⇓
M1880 M1881 M1882 M1895
Application measures：
The application measures are all described as the above-mentioned but that the storage places of card
numbers and corresponding contacts for control are different. For example, in mode 0 of function 14, from
No. 2 DAP sensing to the RF card, now no. 2 will send same card numbers to two different places in
R3835～R3839 and D2865～D2869 (the content of the other registers remains unchanged), and all the
client needs to do is control M1881 for the DAP to display “OK” or “ERROR”. After the RF card exits, the
content of the 10 registers R3835 ～ R3839 and D2865～ D2869 will be cleared to 0 (but remains
unchanged in mode 1).
Applicable occasions：
When several DAPs are connected, the RF card can be read in from different DAPs and each DAP has its
independent card numbers storage places and control points so that no PLC misjudgment case occurs, but
the programming will be more troublesome.
※ If you do not want R3835～R3839 to display a card number value, you can use the Ladder program to fill in
these registers with other fixed values.
Appendix -10
1.7 Special message display function
In general monitoring mode and soft key mode (16 KEYS or 8 KEYS), the user can configure the DAP to display
every kind of message under some circumstances, and the two-line display on the LCD can be controlled
separately to simultaneously display different messages. Every message is 1~511 words and numbers (ASCII code)
long, in which a maximum of 16 variables (if variables with 32-digit are not used, then it can use up to 25) can be
included. When a message has more than 16 words, the message will be displaced left for display, in which the
moving speed or pause time can be configured flexibly.
1.7.1 Message display application

The FB-DAPB(R) can be connected up to 16 sets (Number 1~16). Each DAP not only can display different
messages individually but make all the DAPs connected display the same message simultaneously. If you go to a
special contact (R3780~M3813) set by Enable, the DAP will display the message ASCII Code) indicated by the
corresponding indication register （R3780～M3813）. The content of the indication register is the start register of
messages, i.e. start of ASCII Code. The indication register content can be changed anytime in order to change and
display different messages.
The following is a list of corresponding special contacts and indication registers when each DAP is
displaying a message for control.
Number of LCD line 1 LCD line 2

a message
Special Indication Special Indication
displayed contact register contact register
1～16 M1800 R3780 M1801 R3781
1 M1802 R3782 M1803 R3783
2 M1804 R3784 M1805 R3785

※ The start register of a message
3 M1806 R3786 M1807 R3787 indicated by an indication register
4 M1808 R3788 M1809 R3789 means：
5 M1810 R3790 M1811 R3791
0～8070：indicating R0～R8070
10000～13070：indicating D0～D3070
6 M1812 R3792 M1813 R3793
7 M1814 R3794 M1815 R3795 ※ Special contacts M1800 and M1801

8 M1816 R3796 M1817 R3797 have a priority display function.
9 M1818 R3798 M1819 R3799 ※ M1911 can control an alarm buzzer
10 M1820 R3800 M1821 R3801 whether to sound or not. If M1911=0
（preset）, it shall be activated.
11 M1822 R3802 M1823 R3803
12 M1824 R3804 M1825 R3805
13 M1826 R3806 M1827 R3807
14 M1828 R3808 M1829 R3809
15 M1830 R3810 M1831 R3811
16 M1832 R3812 M1833 R3813
〈Example〉Assume M1803 from 0→1, R3783=100

Result：Line 2 of No. 1 of the LCD will display messages in ASCII Code with R100 start.
〈Example〉 Assume M1828 from 0→1, R3808=10000

Result：Line 1 of No. 14 of the LCD will display messages in ASCII Code with D0 start.
〈Example〉 Assume M1801 from 0→1, R3781=0

Result：Line 2 of all the DAPs will display messages in ASCII Code with R0 start.
Appendix -11
1.7.2 The Information formats of messages（ASCII Table）
The information formats of messages are very similar to the file information in ASCII in chapter 15 in the Advanced
Manual that are all categorized as fixed background information and dynamic variable information. The first can be
words in English, numbers, or signs, and the second binary, decimal or hexadecimal system.
Length of a message is 1~511 digits (including blank spaces), but because there are only 16 digits a line in a DAP
LCD, if a message has more than 16 digits, it will be displayed automatically toward the left (preset moving one
time a second); if less than 16 digits, the tail will be filled in with blank digits and no moving occurs.
To edit a message, the WinProladder ASCII Editor can be applied. The editing command formats are as follows:
1 Background information format

Any ASCII Code digits quoted with ' ' can be background information. To display a single quotation mark as
such, two continuous quotation marks are a must. Example:
' I ' 'M A BOY' will be displayed I'M A BOY
2 Variable information format
，"８．２Ｒ０Ｄ"，
↗ ↑ ↑ ↖
Total Decimal Variable Carry
variable point Register code
count count displayed
displayed
Description information in a pair of dual quotation marks 〝〞is used to indicate the register address (number)
storing the variable information and in what format and carry code to display.
z Total variable count displayed：In this case, the value (including minus) of the variable R0 is displayed in a field
with 8 digits. If the variable value is bigger than the total variable count
displayed, the digits further from the point will be cut. If not enough, blank
spaces will fill in.
z Decimal point count：the decimal point count in the total digits. In this case, with a total count of 8 digits, the
decimal point count is 2. The decimal point sign 〝．〞 as such possesses one digit and
there are 5 digits left in the integral part.
z Variable register：can be used as 16 digit register’s R、D、WX、WY、………, or 32 digit register’s DR、DD、
DWX、DWY、………etc. The content value in the register will be retrieved and displayed with
the format and carry code described in the 〝〞.
z Contacts：generally displayed as ON or OFF (total digit count displayed is set to a fixed 3), but if added with
binary system B in the tail, 0/1 will be displayed (total digit count fixed 1)
z Carry code：can be hexadecimal H, decimal D (the carry code will use decimal if without indication, so D can be
omitted.), or binary B, etc., but a 32 digit variable can not be displayed with binary system.
In this case, R0’s content value is −32768. In 8.2 format the result is displayed as:
− 3 2 7 . 6 8
If the format is changed from 8.2 to 5.1, then the result becomes:
2 7 6 . 8
Appendix -12
3 Basic command signs
z nS Left move speed (repeatable)

Message displayed at a left LCD move per n（1～255）× 0.1s。
z nP Stop move (repeatable)

Message stop in（1～255）× 0.1s，and then move left at a configured speed.
z ， Comma
Used as a statement to divide the file information. Information between two neighboring commas is a
complete and executable statement (unnecessary for the start and end of a file).
z END End of a file

※ nS and nP commands will not be activated until after the information following them moves to the left
first place on the LCD display. They can have a repeatable arrangement of any place in ASCII, but the
same command cannot be connected together.
〈Example〉 Information edited with WinProladder ASCII file editor. R0 is a start register of an ASCII file
and the file information is shown as follows：
5S，20P，’A=’，〝6.2R3840〞，’B=’，〝6.2R3841〞，30P，’C： ’，〝1M0B〞，
’ D： ’，〝1M1B〞，’ E： ’，〝1M2B〞， ’ ’，END
If M1800 from 0→1 and R3780=0（i.e. R0）, Line 1 of the LCD of DAPs of all numbers is shown as follows：
 
Move a place left after stopping 2 seconds

   ︵
Always displayed in a cycle
when
M1800
Move a place left per 0.5s
And
R3780
   
Are
Not
changed
︶
     
After stopping 3s and then move a place left

      
Return to display again after reaching the end of the ASCII
※ Variable information is renewable anytime.

※ To display another message, just change R3780 value and not for M1800.
Appendix -13
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【Instruction】

Chapter 1 PLC Ladder Diagram and the Coding Rules of Mnemonic

1.1 The Operation Principle of Ladder Diagram

1.1.1 Combination Logic

Actual wiring diagram

1.1.2 Sequential Logic

Actual wiring diagram

c Released Released OFF

1.2 Differences Between Conventional and PLC Ladder Diagram

Output processing (Output the resulting

Reverse flow of conventional Ladder diagram

Sample Ladder Diagram

(Remark：The maximum size of FBs-PLC network is 16 rows×22 columns)

Relay coil COIL Relay contacts

Element type Symbol Mnemonic instructions Remark

Open Circuit Contact (ORG、LD、AND、OR) OPEN

Short Circuit Contact (ORG、LD、AND、OR) SHORT

h Block: a circuit consists of two or more elements.

Branch line Merge line

Parallel block 1 Parallel block 2

Block 1 merge line Block 2 branch line

OUT TR0 Y0 Ö AND

z Using AND instruction for serial connection of a single element.

z Using OR instruction for parallel connection of a single element.

z If the parallel element is a serial block, ORLD instruction must be used.

Example: ANDLD instruction ORG X 0

Must use ANDLD instruction

3 ORLD( 1 2 ) 6 ORLD( 4 5 ) 12 OR( 10 11 )

ORLD Forming the parallel i

ORLD Forming the parallel

ANDLD Forming the serial block ○

OUT Y0 Send the ○

Although this branch has merge lines

Example： Merge line

z TR instruction is not necessary because the（*）point is the origin line.

1.7 Program Simplification Techniques

This network structure is not X1

2.1 FBS-PLC Memory Allocation

the corresponding R5000～R8071.

IR , OR R3840 R3840 ROR can be configured up to 3072

Memory Buffer in PLC PP/Winproladder

Special Relay M1912～M2001 (90)

Step Non-Retentive S0～S499 (500)* S20～ S499 configurable as Retentive

T Timer contact status T0～T255 (256)

0.01STime Base T0～ T49 (50)*

Non-Retentive C240～C255 (16) Configurable as Retentive

DR R0～R2999 (3000)* R0～R3839 configurable as

IR Input Registers R3840～R3903 (64) Map to external AI Register input

OR Output Registers R3904～R3967 (64) Map to external AO /Register output

R3968～ R4167 (200)

High-Spped Timer Register R4152～R4154 (3)

HSC Hardware (4sets) DR4096～ DR4110

Calendar Day Hour R4131 R4130

XR Index Registers V,Z (2)、 P0～ P9 (10)

2.3 Special Relay Details

Relay No. Function Description

1. Stop, Prohibited Control

◤M1925 Scan clock pulses e

Single Operand Function Instructions

Mathematical Operation Instructions

Logical Operation Instructions

Code Conversion Instruction