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LATCHES

BY:-ANIL KUMAR MANDAL(1NT19EE013)

DIGITAL ELECTRONIC

Latches in Digital Electronics


In digital electronics, a Latch is one kind of a logic circuit, and it is also known as
a bistable-multivibrator. Because it has two stable states namely active high as well as
active low. It works like a storage device by holding the data through a feedback lane. It
stores 1-bit of data as long as the apparatus is activated. Once enable is declared then
instantly latch can change the stored data. It constantly trials the inputs once enable
signal is activated. The working of these circuits can be done in 2-states based on the
enable signal being high or else low. When the latch circuit is the in an active high state,
then both the i/ps are low. Similarly, when the latch circuit is then an active low state,
then both the i/ps are high.

Different Types of Latches


The latches can be classified into different types which include SR Latch, Gated S-R
Latch, D latch, Gated D Latch, JK Latch, and T Latch.

SR Latch using NOR GATE


An SR (Set/Reset) latch is an asynchronous apparatus, and it works separately for
control signals by depending on the S-state & R-inputs. The SR-latch using 2-NOR
gates with a cross loop connection is exhibited below. These latches can be built
with NAND gates also; however, the two inputs are exchanged as well as canceled. So it
is called as SR’-latch.
The truth table of S-R latch using NOR gates is given below:

When input S = 0, R = 1, Output Q = 0, Q̅ = 1.

This input resets the output state Q to 0.

When input S = 1, R = 0, Output Q = 1, Q̅ = 0.


This input sets the output state Q to 1.

When input S = 0, R = 0, the output state remains unchanged thus it is known as “Hold
state”.

When input S = 1, R = 1, the output Q & Q̅ = 0. Which violates the condition Q & Q̅ are
inverse of each other, they should not be equal.

That is why this state is known as “Invalid / prohibited input state”.

S-R Latch NAND Gate:-


Schematic design of S-R latch using NAND is given in the figure below:
The truth table of S-R latch using NAND gate is given below:

The S-R latch using NAND gate is active low. That is why its truth table is completely
opposite of S-R latch using NOR gate.

When input S = 0, R = 1, Output Q = 1, Q̅ = 0.

This input sets the output state Q to 1.

When input S = 1, R = 0, Output Q = 0, Q̅ = 1.

This input resets the output state Q to 0.


When input S = 1, R = 1, the output state remains unchanged thus it is known as “Hold
state”.

When input S = 0, R = 0, the output Q & Q̅ = 0. Which violates the condition Q & Q̅ are
inverse of each other, they should not be equal.
That is why this state is known as “Invalid / prohibited input state”.

Invalid or prohibited state can be avoided by converting it into any of the other 3 states.

Advantages & Disadvantages of Latches


Advantages:

 Latch circuits designs are more flexible as compared to flip-flop circuits.


 Digital latches are used in high speed circuit designs as they are faster and it has no
need to wait for a clock input signal due to higher clock speeds as they are
asynchronous in design and clock is not used over there
 They are small and acquire less size of area as latches based circuits have small die
size and they are more successful in high speed circuits designs.
 They consume less power.
 Latch is time borrowing and sharing i.e. if a circuit operation is not completed in the
given time frame, they borrow the required time to execute the operation from other
operational time.
 They provide aggressive clocking as compared to flip-flops based circuits.
Disadvantages:
 There is a chance to affect the race condition, hence, Latches are less predictable.
 As latches are level sensitive, there are also some chances of meta-stability.
 As they are level sensitive devices, they are complicated to analyze the latch circuits
and additional CAD program should be used to test the circuit.

Application of Sr LATCHES

SWITCH DEBOUNCER
We use switch in our day to day life to switch ON/OFF a bulb or a fan or any electrical
devices. But when we use switches in digital circuits, we observe a phenomenon called
bouncing. This occurs because, when we turn the switch, the mechanical parts vibrate. i.e It
toggles between ON and OFF state for some time until the mechanical contact attain
equilibrium. this vibrations are minute and are not at all noticeable in electrical circuit. where
as in digital circuits, these vibrations create pulses. which are detected by circuits which
results in an error.
In the above circuit, there is a switch connected to VCC. You can toggle it between terminal 'a' and
terminal 'b'. which as a voltage drop of 'Va' and 'Vb' respectively. In digital circuits if you can observe,
it takes a finite amount of time to toggle between terminal 'a' and 'b'. which might approximately
take 15ns. Now let us consider the terminal is at 'a'. we will switch it to 'b'. what we can observe are...

It takes finite time (approximately 15ns) to make contact with terminal 'b'.

Once the metal contact touches the terminal 'b'. It bounces several times before it reaches
equilibrium.

From the timing diagram it is evident that there are several unwanted pulses which are
present due to bouncing. This can be eliminated by using SR latch using NOR gates.
SWITCH DEBOUNCER
Other applications are:-
 As latch is single bit storage element, they may be used as storage device in power
gating circuits and clock
 They may be used as pulse latches where they perform the same behavior like flip-
flops by pulsing the clock very quickly.
 In Asynchronous systems, D latch are used as input / output ports.
 To reduce the transit count in synchronous two phase systems, data latches may be
used.
 They are widely used in data storage and computing. In short, no latches & Flip-flops,
= no digital electronics and computers.

THANK YOU

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