FLIP FLOPS

 Flip flop is a memory element.

 Flip flop is a bistable logic element with one or more inputs and 2 outputs.
 flip flops are actually an application of logic gates. With the help of Boolean logic you can
create memory with them. Flip flops can also be considered as the most basic idea of a
Random Access Memory [RAM].
 When a certain input value is given to them, they will be remembered and executed, if the
logic gates are designed correctly.
 A higher application of flip flops is helpful in designing better electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback
circuit. As a memory relies on the feedback concept, flip flops can be used to design it.
There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop

2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop
5.

What is SR Flip Flop?

1. S-R Flip Flop

 The SR Flip Flop is a bistable device built with a sequential logic circuit that can
store a minimum of 1-bit memory data.
 The SR Flip Flop Stands for Set Reset Flip Flop. It is also known as SR latch. It is
the most basic sequential logic circuit.
 It is built with two logic gates. The output of each gate is connected to the input of
the other gate so a feedback signal can go from the output to the input.
  The SR flip flop has two inputs named as Set(S) and Reset(R), that is why it is
called SR Flip Flop. The rest input is used to get back the flip flop to its old
original state from the current state.
 The output of the flip flop depends upon its inputs such as the input SET(S) makes
the output 1 while the input RESET(R) make the output 0.

 The SR Flip Flop can be built with either NAND gates or NOR gates. A basic SR
flip Flop constructed with NAND gates and it has four terminals - Two Active
Low input Terminals(S, R) and two output terminals Q and Q'.
 This is also called as Flip Flop because during the operation it fliped to a logic set
state ad flopped back to the opposite logic reset state.

SR Flip Flop Circuit Diagram

Basic SR Flip Flop Circuit using two NAND gates.

Prescribed book diagram:

S-R Flip Flop using NAND Gate
Like the NOR Gate S-R flip flop, this one also has four states. They are

1. SET State:

S=1, R=0—Q=0, Q’=1

This state is also called the SET state.

2. RESET State:

S=0, R=1—Q=1, Q’=0

This state is known as the RESET state. In both the states can see the outputs are just
compliments of each other and that the value of Q follows the compliment value of S.

3. Invalid
S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the values of both Q
and Q’ are 1. They are supposed to be compliments of each other. Normally, this state must be
avoided.
4. No Change
S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the value of S and
R in their previous state.

The circuit of the S-R flip flop using NAND Gate and its truth table is shown
below.

2. Gated SR Flip Flop

 A gated SR latch (or clocked SR Latch) can only change its output state when
there is an enabling signal along with required inputs. For this reason it is
also known as a synchronous SR latch.
 Conversely, latches that can change its state instantaneously on the
application of its required inputs conditions are known as asynchronous
latches.
 That means the inputs can only act upon when the latch is enabled otherwise
there will be no change in output state even required inputs are applied. In
other words, the latch is active when ENABLE signal is HIGH and it is
 inactive when ENABLE signal is LOW. This HIGH LOW enable signal is
applied to the gated latch in the form of clocked pulses.
 A gated SR latch (or clocked SR Latch) can only change its output state
when there is an enabling signal along with required inputs. For this
reason it is also known as a synchronous SR latch. Conversely, latches
that can change its state instantaneously on the application of its
required inputs conditions are known as asynchronous latches.
 That means the inputs can only act upon when the latch is enabled
otherwise there will be no change in output state even required inputs
are applied.
 In other words, the latch is active when ENABLE signal is HIGH and it
is inactive when ENABLE signal is LOW. This HIGH LOW enable
signal is applied to the gated latch in the form of clocked pulses.

The Clocked SR flip-flop consists of 4 NAND gates, two inputs(S and R) and two outputs(Q
and Q’). The clock pulse (also one input) is given at the inputs of gate A and B.

If the clock pulse input is replaced by an enable input, then it is said to be SR latch. Let us
assume that this flip flop works under positive edge triggering. The following figure shows
the block diagram and the logic circuit of a clocked SR flip flop.
Case 1: No Change state[S = 0, R = 0]
When the clock pulse is applied, the output of NAND gates A and B will be S’ = 1, R’ = 1.

For this case, if Q = 0, Q’ = 1, then both the inputs for NAND gate C are 1 and the output
thus produced by gate C is Q +1 =0. The present state output is Q = 0 and the next state
output is Q’ = 0. Thus the state has no change.

For the same SR inputs, if Q = 1, Q’ = 0, the inputs for NAND gate C will be 0 and 1. For
these inputs, the output produced by the NAND gate is Q +1 = 1, hence there is no change in
the state.

Case 2: RESET state[S = 0, R = 1]

Upon the application of the clock pulse, the output of NAND gate A and B are S’ = 1, R’ = 0.
Let the present state output be Q = 0 or Q = 1. For any of these inputs at the NAND gate D,
the next state output produced is Q’+1 = 1. Now, the tw0 inputs for NAND gate C are S’ = 1, Q’
= 1, which produces an output at next state as Q+1 = 0.

For this case, whether the present state is either 0 or 1, it will produce an output 0, which
will RESET the flip flop.

Truth table for clocked SR flip flop

Case 3: SET state[S = 1, R = 0]

When the clock pulse is applied, the output from the NAND gate A and B are S’ = 0, R’ = 1.

For this condition, irrespective of the present state input Q’, the next state output produced
by the NAND gate C is Q+1 = 1. Thus the two inputs of NAND gate D are R’ = 1 and Q = 1,
which produces an output Q’+1 = 0.

So, in this case, whether the present state output is either 0 or 1, the next state output is
logic 1, which will SET the flip flop.

Case 4: Indeterminate or Invalid state[S = 1, R = 1]

For the inputs S = 1 and R = 1, the NAND gates A and B produces the output S’ = 0, R’ = 0.

Now, if Q = 0 and Q’ = 1, the inputs for NAND gate C will be S’ = 0 and Q’ = 1. The output
produced from NAND gate C is Q+1 = 1. Similarly, the two inputs for NAND gate D will be R’
= 0 and Q = 0. The output produced from the NAND gate D is Q’+1 = 1.

If Q = 1 and Q’ = 0, the output produced from the NAND gate C is Q +1 = 1 for the inputs S’ =
0 and Q’ = 0. For the same value of Q and Q’, output produced from NAND gate D is Q’ +1 = 1,
where the inputs are R’ = 0 and Q = 1.

For this case, it is observed that the next state output Q +1 = 1 and Q’+1 = 1. This is an
impossible output because Q and Q’ should be complement with each other. So it is an
indeterminate or invalid state.

SR Flip Flop Applications

1. As we know the SR Flip Flop can store 1-bit data. So we can use it in digital memory
circuits.

2. SR Flip Flop is used in frequency divider circuits.

3. They are also used in digital counter circuits.

2. D Flip Flop

In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and RESET = "0" is
forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

 2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input remains "0" by which the
resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter between the Set and Reset
inputs for producing another type of flip flop circuit called D flip flop, Delay flip flop, D-type Bistable, D-
type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures that at the same time,
both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed using a gated SR flip-
flop with an inverter connected between the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the complementary
"Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop is constructed from a
level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram

Circuit Diagram
We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and another to
"RESET" the output. By using an inverter, we can set and reset the outputs with only one input as
now the two input signals complement each other. In SR flip flop, when both the inputs are 0,
that state is no longer possible. It is an ambiguity that is removed by the complement in D-flip
flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set to
1, the flip flop would be set, and when it is set to 0, the flip flop would change and become
reset. However, this would be pointless since the output of the flip flop would always change on
every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip
flop's latching circuitry. When the clock input is set to true, the D input condition is only copied
to the output Q. This forms the basis of another sequential device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set to 1. So
it will not change the state and store the data present on its output before the clock transition
occurred. In simple words, the output is "latched" at either 0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed these
symbols as edge-triggers.

So, here S=D and R= ~D(complement of D)

Block Diagram

Circuit Diagram
We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and
another to "RESET" the output. By using an inverter, we can set and reset the outputs
with only one input as now the two input signals complement each other. In SR flip flop,
when both the inputs are 0, that state is no longer possible. It is an ambiguity that is
removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input
is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would change
and become reset. However, this would be pointless since the output of the flip flop
would always change on every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from
the flip flop's latching circuitry. When the clock input is set to true, the D input condition
is only copied to the output Q. This forms the basis of another sequential device
referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set
to 1. So it will not change the state and store the data present on its output before the
clock transition occurred. In simple words, the output is "latched" at either 0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed
these symbols as edge-triggers.

T Flip Flop
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop , provide only a single input
called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. This flip-flop work
as a Toggle switch. The next output state is changed with the complement of the present state
output. This process is known as "Toggling"'.

"T Flip Flop" construct by making changes in the "JK Flip Flop". The "T Flip Flop" has only
one input, which is constructed by connecting the input of JK flip flop. This single input is
called T. In simple words, we can construct the "T Flip Flop" by converting a "JK Flip Flop".
Sometimes the "T Flip Flop" is referred to as single input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK defines
the clock signal input.

There are the following two methods which are used to form the "T Flip Flop":

32.7M

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o By connecting the output feedback to the input in "SR Flips Flop".

o We pass the output that we get after performing the XOR operation of T and
QPREV output as the D input in D Flip Flop.

T Flip Flop Circuit

 This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected

together and thus are also called a single input J-K flip flop. When clock pulse is given to the

flip flop, the output begins to toggle. Here also the restriction on the pulse width can be

eliminated with a master-slave or edge-triggered construction. Take a look at the circuit and

truth table below.

Construction
The "T Flip Flop" is designed by passing the AND gate's output as input to the Nor gate of the
"SR Flip Flop". The inputs of the "AND" gates, the present output state Q, and its complement
Q' are sent back to each AND gate. The toggle input is passed to the AND gates as input. These
gates are connected to the Clock (CLK) signal. In the "T Flip Flop", a pulse train of narrow
triggers are passed as the toggle input, which changes the flip flop's output state. The circuit
diagram of the "T Flip Flop" using "SR Flip Flop" is given below:

The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the output after
performing the XOR operation of the T input with the output "Q PREV" is passed as the D input.
The logical circuit of the "T-Flip Flop" using the "D Flip Flop" is given below:
The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the "JK Flip
Flop" are connected as a single input T. Below is the logical circuit of the T Flip Flop" which is
formed from the "JK Flip Flop":

Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND is disabled when the output Q To is set
to 0. make the flip flop in "set state(Q=1)", the trigger passes the S input in the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when the output Q is
set to 1. The trigger passes the R input in the flip flop to make the flip flop in the reset
state(Q=0).

Operations of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T input is set to false or 0.

o If toggle input is set to 0 and the present state is also 0, the next state will be 0.
o If toggle input is set to 0 and the present state is 1, the next state will be 1.

The next state of the flip flop is opposite to the current state when the toggle input is set to 1.

o If toggle input is set to 1 and the present state is 0, the next state will be 1.
o If toggle input is set to 1 and the present state is 1, the next state will be 0.

The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by the incoming
trigger. The "T Flip Flop" requires two triggers to complete a full cycle of the output waveform.
The frequency of the output produced by the "T Flip Flop" is half of the input frequency. The "T
Flip Flop" works as the "Frequency Divider Circuit."

In "T Flip Flop", the state at an applied trigger pulse is defined only when the previous state is
defined. It is the main drawback of the "T Flip Flop".

The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip Flop" because
the "T Flip Flop" is not available as ICs. The block diagram of "T Flip Flop" using "JK Flip Flop" is
given below: