SUBJECT NAME: Computer Organization &

Architecture
SUBJECT CODE: 203105253

UNIT 2

Trilok Suthar
Asst. Prof. IT Dept

1
DATA REPRESENTATION:
Signed number representation, fixed and floating point
representations, Character representation.
Computer arithmetic -integer addition and Subtraction,
ripple carry adder, carry look-ahead adder, etc.
multiplication shift-and add, Booth multiplier, carry save
multiplier, etc.
Division restoring and non-restoring techniques, floating
point arithmetic

2
Signed number representation

Binary numbers can be represented in signed and unsigned

way. Unsigned binary numbers do not have sign bit, whereas
signed binary numbers uses signed bit as well or these can
be distinguishable between positive and negative numbers. A
signed binary is a specific data type of a signed variable.

3
4
Signed Magnitude Representation

• The left most bit (Sign bit) in the binary number represents sign of
the number
B7 B6 B5 B4 B3 B2 B1 B0

SIGN MAGNITUDE
Fig shows the Sign Magnitude format for 8 bit
signed Number
The Most Significant bit (MSB) represents sign
of the number.
If MSB is 1, Number is Negative
If MSB is 0, Number is Positive
5
• Example

• +6 = 0000 0110
• -14 = 1000 1110
• +24 = 0001 1000
• -64 = 1100 0000

6
• For unsigned 8 bit binary number the decimal range is 0 to 255
• For signed magnitude 8 bit binary numbers the largest magnitude is
reduced from 255 to 127.

• Max positive num

• 0 1 1 1 1 1 1 1 =+127

• Max Negative num

1 1 1 1 1 1 1 1 =-127

7
There are several problems in fact:
• Addition and subtraction operations require:
•Considering both signs and the magnitudes of each number;
• There are two representations of 0:

•We need to test for two cases representing zero;

•This operation is frequently used in computers...
• Because of these drawbacks sign-magnitude representation is rarely use...
Like the sign magnitude system:
•uses the most significant bit as a sign bit;
•Easy to test whether an integer is positive or negative
However, it differs from the use of the sign-magnitude
representation:
•in the way that the other bits are interpreted.
8
1’s Complement Representation

• The 1’s complement of a binary number is the number that results

when we change all 1’s to zero and zero to ones.
• 1’s complement of (11010100)2

1 1 0 1 0 1 0 0

0 0 1 0 1 0 1 1

9
2’s Complement Representation

• The 2’s complement is the binary number that results when we add 1
to the 1’s complement
• 2’s complement = 1’s complement +1
• 2’s complement form is used to represent negative numbers
• Eg 2’s complement (11000100)

• 1 1 0 0 0 1 0 0 ( number )
• 1 1 (Carry)
• 0 0 1 1 1 0 1 1 ( 1’s Complement)
•+ 1 (Add 1)

• 0 0 1 1 1 1 0 0

10
Sign Extension

• When we add two binary numbers the result may extend by 1 bit i.e
the resulted binary number may need one more bit if there is a carry
after addition of Most significant bit.
• To represent such result in correct format we have to allocate the
additional bit for representing the magnitude of the numbers

1 0 0 0
0 1 0 0 0
0 0 1 0 0 0

11
• In case of negative binary number can extend the bit by appending bit
1 to the left of the Most Significant bit of the Number.

• Eg. +20
•
1 0 1 0 0

1 0 1 0 0

Original number represented using 6 bits

SIGN-BIT

12
represented using 7 bit
1 0 1 0 0

SIGN- Extension
represented using 8 bit
1 0 1 0 0

SIGN- Extension

13
NEGATIVE NUMBER

• EG -20
• 6 BITS IN 2’S COMPLEMENT

1 0 1 1 0 0

SIGN-BIT

14
7 BITS REPRESENATION

1 1 0 1 1 0 0

SIGN-Extension
8 BITS REPRESENATION

1 1 1 0 1 1 0 0

SIGN-Extension
15
FLOATING POINT REPRESENTATION

• To accommodate very large integer and very fractions, a computer

must be able to represent numbers and operate on them in such a
way that the position of the binary point is variable and is automatically
adjusted as computation proceeds.
• In this case the binary point is said to float and the numbers are called
floating point numbers
• Has three fields
• sign
• significant digit
• exponent

16
• E.g

• 111101.1000110
• normalized form
EXPONENT
•1.111011000110 X 𝟐 𝟓

Sign
Significant digit Scaling factor

17
• We can say that
• Sign = 0
• Mantissa= 11101100110
• Exponent =5

18
IEEE STANDARD FOR FLOATING POINT NUMBER

• The stds for representing floating point numbers in 32 bits and 64 bits
have been developed by
• INSTITUTE OF ELECTRICAL AND ELECTRONIC ENGINEERS(IEEE)
• Referred to as IEEE 754 standards
32 bit
31 30 23 22 0

S E’ M
Sign

8 bit signed
23 bit Mantissa
exponent in excess-
fraction
127 representation 19
• Sign of number
• 0 signifies +ve number
• 1 signifies –ve number
• Instead of the signed exponent E the value actually
stored in the exponent field is E’=E + bias
• For 32 bit bias is 127
• Hence E’= E+127
• For 32 bit representation the actual exponent E is in the
range -126 <=E<=127

20
Double Precision representation

64 bits
63 62 52 51 0

S E’ M
Sign

11 bit signed
52 bit Mantissa
exponent in excess-
fraction
1023 representation

21
• In double precision format value actually stored in the exponent field
is given as
• E’ = E + 1023

• Bia value is 1023 and hence it is also called excess-1023 format

• Range of E’ for 64 bit representation is
• 0<E’<2047 and
• -1022<= E<= 1023

22
Example

• 1259.125 Represent in single & Double Precision Format.

• Step 1 Convert given number into Binary
• Integer Part
Q R LSD
16 1259 11 B
16 78 14 E
16 4 4 4
MSD
(1259)10 =(4𝐸𝐵)16
4 E B HEX
0 1 0 0 1 1 1 0 1 0 1 1 Binary

23
• FRACTION PART

Fraction Base Product OUTPUT

0.125 X 2 0.25 0

0.25 X 2 0.50 0

0.50 X 2 1.00 1

(0.125)10 =(0.001)2

24
• Binary Number
• 10011101011 + 0.001= 10011101011.001

• STEP 2: Normalize the number

• 10011101011.001
• = 1.0011101011001 X 210

25
• STEP 3 Single Precision Representation (IEEE 754 32 bit format)
• For a given number S=0, E =10 and M = 0011101011001
• Bias=127 so E’= E+127 = 10+127 = 13710
• E’= 10001001

S EXPONENT MANTISSA

0 1 0 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0

26
• STEP 4 Double Precision Representation (IEEE 754 64 bit format)
• For a given number S=0, E =10 and M = 0011101011001
• Bias=1023 so E’= E+1023 = 10+1023 = 103310
• E’= 10000001001

SIGN EXPONENT
0 1 0 0 0 0 0 0 1 0 0 1

MANTISSA
0 0 1 1 1 0 1 1 0 0 1 --- 0 0

27
CHAR REPRESENTATION

• Character data is composed of letters, symbols, and numerals that are not
used in calculations. • Examples of character data include your name,
address, and hair colour.
• Character data is commonly referred to as “text.”
• Digital devices employ several types of codes to represent character data,
including ASCII, Unicode, and their variants. • ASCII (American Standard
Code for Information Interchange, pronounced “ASK ee”) requires seven
bits for each character. • The ASCII
• Extended ASCII is a superset of ASCII that uses eight bits for each
character. • For example, Extended ASCII represents the uppercase letter
A as 01000001. • Using eight bits instead of seven bits allows Extended
ASCII to provide codes for 256 characters.

28
• Unicode (pronounced “YOU ni code”) uses sixteen bits and provides
codes or 65,000 characters. • This is a bonus for representing the
alphabets of multiple languages.
• UTF-8(8-bit Unicode Transformation Format) is a variable-length
coding scheme that uses seven bits for common ASCII characters but
uses sixteen-bit Unicode as necessary.

29
ADDITION AND SUBTRACTION

Addition
Addition proceeds as if the two numbers were unsigned integers:

•Carry bit beyond (indicated by shading) is ignored;

30
But what happens with this case?

• Two numbers of the same sign produce a different sign...

•Overflow:
•Result is larger that what can be stored with the word;
•Solution: Increase word size;
•When overflow occurs:
•ALU must signal this fact so that no attempt is made to use
the result.
31
 To subtract the subtrahend from the minuend:

•Take the twos complement of the subtrahend (S) and add it to the
minuend (M).
•M + (−S)
•I.e.: subtraction is achieved using addition;

•Carry bit beyond (indicated by shading) is ignored

32
 Subtraction is achieved using addition: M + (−S)

•Carry bit beyond (indicated by shading) is ignored;

•Overflow: two numbers of the same sign produce
a different sign;
33
Hardware Block Diagram for Adder

Block diagram of hardware for addition and

subtraction
34
From the previous figure:
•Central element is a binary adder:
•Presented with two inputs;
•Produces a sum and an overflow indication;
•Adder treats the two numbers as unsigned integers
•For the addition operation:
•The two numbers are presented in two registers;
•Result may be stored in one of these registers or in a
third;
•For the subtraction operation:
•Subtrahend (B register) is passed through a twos
complementor;
•Overflow indication is stored in a 1-bit overflow flag.

35
Ripple carry adder
• A ripple carry adder is a logic circuit in which the carry-out of each full
adder is the carry in of the succeeding next most significant full adder.
It is called a ripple carry adder because each carry bit gets rippled into
the next stage.

36
• In ripple carry adders, for each adder block, the two bits that are to
be added are available instantly. However, each adder block waits
for the carry to arrive from its previous block. So, it is not possible to
generate the sum and carry of any block until the input carry is
known. The Ith block waits for the i-1th block to produce its carry. So
there will be a considerable time delay which is carry propagation
delay.
• Consider the above 4-bit ripple carry adder. The sum S_{4} is
produced by the corresponding full adder as soon as the input
signals are applied to it. But the carry input C_{4} is not available on
its final steady state value until carry C_{3} is available at its steady
state value. Similarly C_{3} depends on C_{2} and C_{2} on C_{1}.
Therefore, though the carry must propagate to all the stages in order
that output S_{3} and carry C_{4} settle their final steady-state value

37
• The propagation time is equal to the propagation delay of
each adder block, multiplied by the number of adder blocks
in the circuit. For example, if each full adder stage has a
propagation delay of 20 nanoseconds, then S_{3} will reach
its final correct value after 60 (20 × 3) nanoseconds. The
situation gets worse, if we extend the number of stages for
adding more number of bits.

38
carry look-ahead adder

39
• In this adder, the carry input at any stage of the adder is
independent of the carry bits generated at the independent
stages. Here the output of any stage is dependent only on
the bits which are added in the previous stages and the
carry input provided at the beginning stage. Hence, the
circuit at any stage does not have to wait for the generation
of carry-bit from the previous stage and carry bit can be
evaluated at any instant of time.

40
• Advantages of Carry Look-ahead Adder
• In this adder, the propagation delay is reduced. The carry output at
any stage is dependent only on the initial carry bit of the beginning
stage. Using this adder it is possible to calculate the intermediate
results. This adder is the fastest adder used for computation.
• Applications
• High-speed Carry Look-ahead Adders are used as implemented as
IC’s. Hence, it is easy to embed the adder in circuits.

41
Multiplication
Multiplication is a complex operation:
•Compared with addition and subtraction;
•Again lets consider multiplying for the following cases:
•Two unsigned numbers;
•Two signed (twos complement) numbers;

Unsigned multiplication
42
• Several important observations:
• 1 Multiplication involves the generation of partial products:
•One for each digit in the multiplier;
•These partial products are then summed to produce the
final product.
• 2 The partial products are easily defined.
•When the multiplier bit is 0,the partial product is 0;
•When the multiplier is 1, the partial product is the
multiplicand;
• 3 Total product is produced by summing the partial products:
•each successive partial product is shifted one position to
the left relative
• 4 Multiplication of two n-bit binary integers produces up to 2n
bits;
43
SHIFT-ADD MULTIPLIER

Hardware Implementation
44
• 4 Control logic then reads the bits of the multiplier one at a time:
•If Q0 is 1, then:
•the multiplicand is added to the A register...
•and the result is stored in the A register...
•with the C bit used for overflow.
•Then all of the bits of the C, A, and Q registers are shifted to
the right one bit:
•So that the C bit goes into An−1 , A0 goes into Qn−1 and Q0 is lost.
•If Q0 is 0, then:
•Then no addition is performed, just the shift;
•Process is repeated for each bit of the original multiplier;
•Resulting 2n-bit product is contained in the A and Q
registers
45
Arithmetic Shift

• Arithmetic shift left

• Multiplies a signed binary number by 2

• Arithmetic shift Right

46
MULTIPLICATION ALGORITHMS

47
Example

C A Q M
0 0000 1101 1011 Initial Values

48
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add

49
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add
0 0101 1110 1011 Shift Right

50
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add
0 0101 1110 1011 Shift Right
0 0010 1111 1011 Shift

51
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add
0 0101 1110 1011 Shift Right
0 0010 1111 1011 Shift
0 1101 1111 1011 Add

52
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add
0 0101 1110 1011 Shift Right
0 0010 1111 1011 Shift
0 1101 1111 1011 Add
0 0110 1111 1011 Shift

53
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add
0 0101 1110 1011 Shift Right
0 0010 1111 1011 Shift
0 1101 1111 1011 Add
0 0110 1111 1011 Shift
1 0001 1111 1011 Add

54
Example

C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add
0 0101 1110 1011 Shift Right
0 0010 1111 1011 Shift
0 1101 1111 1011 Add
0 0110 1111 1011 Shift
1 0001 1111 1011 Add
0 1000 1111 1011 Shift

55
BOOTH ALGORITHM (for Sign Bit Number)

56
BOOTH ALGORITHM

• STEP1 : Load A=0, Q−1 =0

M= Multiplicand
Q= Multiplier
SC=0
STEP 2
Check the status of 𝑄0 𝑄−1
If 𝑄0 𝑄−1 =10 --> A=A-M
𝑄0 𝑄−1 =01 → A=A+M
STEP 3
Arithmetic Shift Right: A, Q, 𝑄−1

STEP 4 Decrement SC if not zero , Repeat Step 2 to 4

STEP 5 STOP

57
EG both positive (5X4)

• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4)

SC A Q OPERATI
ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial

58
EG both positive (5X4)

• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4)

SC A Q OPERATI
ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith.
Shift R

59
EG both positive (5X4)

• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4)

SC A Q OPERATI
ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith. Shift
R
0 1 0 0 0 0 0 0 0 0 1 0 Arith.
Shift R

60
EG both positive (5X4)

• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4)

SC A Q OPERATI
ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith. Shift
R
0 1 0 0 0 0 0 0 0 0 1 0 Arith. Shift
R
0 0 0 0 A Q0 Q-
+ 1 0 1 1 2’s complement of M 1=10
A<-A-M
1 0 1 1 0 0 0 1 0

61
EG both positive (5X4)
• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4)
SC A Q OPERATI
ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith. Shift
R
0 1 0 0 0 0 0 0 0 0 1 0 Arith. Shift
R
0 0 0 0 A Q0 Q-
+ 1 0 1 1 2’s complement of M 1=10
A<-A-M
1 0 1 1 0 0 0 1 0
0 0 1 1 1 0 1 1 0 0 0 1 A.S.R

62
EG both positive (5X4)
• Multiplicand
SC (M)=0101
A (5), MultiplierQ(Q)= 0100 (4) OPERATI
ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith. Shift
R
0 1 0 0 0 0 0 0 0 0 1 0 Arith. Shift
R
0 0 0 0 A Q0 Q-
+ 1 0 1 1 2’s complement of M 1=10
A<-A-M
1 0 1 1 0 0 0 1 0
0 0 1 1 1 0 1 1 0 0 0 1 A.S.R
1 1 0 1 A Q0 Q-
+ 0 1 0 1 M 1=01
A<-A+M
0 0 1 0 1 0 0 0 1

63
EG SC
both positive (5X4)
A Q OPERATI
• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4) ON
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith. Shift
R
0 1 0 0 0 0 0 0 0 0 1 0 Arith. Shift
R
0 0 0 0 A Q0 Q-
+ 1 0 1 1 2’s complement of M 1=10
A<-A-M
1 0 1 1 0 0 0 1 0
0 0 1 1 1 0 1 1 0 0 0 1 A.S.R
1 1 0 1 A Q0 Q-
+ 0 1 0 1 M 1=01
A<-A+M
0 0 1 0 1 0 0 0 1
0 0 0 0 0 0 1 0 1 0 0 0 A.S.R

64
 SC A Q OPERATI
EG both positive (5X4) ON
• Multiplicand (M)=0101 (5), Multiplier (Q)= 0100 (4)
A3 A2 A1 A0 Q3 Q2 Q Q Q-1
1 0
1 0 0 0 0 0 0 0 1 0 0 0 Initial
0 1 1 0 0 0 0 0 0 1 0 0 Arith. Shift
R
0 1 0 0 0 0 0 0 0 0 1 0 Arith. Shift
R
0 0 0 0 A Q0 Q-
+ 1 0 1 1 2’s complement of M 1=10
A<-A-M
1 0 1 1 0 0 0 1 0
0 0 1 1 1 0 1 1 0 0 0 1 A.S.R
1 1 0 1 A Q0 Q-
+ 0 1 0 1 M 1=01
A<-A+M
0 0 1 0 1 0 0 0 1
0 0 0 0 0 0 1 0 1 0 0 0 A.S.R
RESULT 0 0 0 1 0 1 0 0 0
65
CARRY SAVE MULTIPLIER

• The carry-save array multiplier uses an array of carry-save adders

for the accumulation of partial product. It uses a carry-propagate
adder for the generation of the final product. This reduces the critical
path delay of the multiplier since the carry-save adders pass the
carry to the next level of adders rather than the adjacent ones.

66
EXAMPLE OF CARRY SAVE MULTIPLIER

1 0 1 1
X 1 1 0 1
1 0 1 1 A
0 0 0 0 X B
1 0 1 1 x X C
1 0 1 1 x x X D
CD BA

𝑆2 𝐶2 𝑆1 𝐶1

𝑆3 𝐶3

𝑆4 𝐶4
RESULT 67
 EXAMPLE OF CARRY SAVE MULTIPLIER

STEP 1 STEP 2
1 0 1 1 A 1 0 1 1 x x C
+ 0 0 0 0 x B 1 0 1 1 x x x D
0 1 0 1 1 S1 1 1 1 0 1 x x S2
0 0 0 0 x C1 0 0 1 0 0 x x C2

STEP 3 STEP 4
0 1 0 1 1 S1 1 1 1 1 1 1 1 S3
0 0 0 0 x C1 0 0 0 0 0 0 X C3
1 1 1 0 1 x x S2 0 0 1 0 0 x X C2
1 1 1 1 1 1 1 S3 1 1 0 1 1 1 1 S4
0 0 0 0 0 0 x C3 0 1 0 0 0 0 x C4

68
EXAMPLE OF CARRY SAVE MULTIPLIER

STEP 5
1 1 0 1 1 1 1 S4
0 1 0 0 0 x x C4
1 0 0 0 1 1 1 1

RESULT

69
RESTORING DIVISION ALGORITHM

70
• STEP 1: Shift A and Q left one binary position.
• STEP 2: Subtract divisor (M) from A and place answer back in A
(A=A-M)
STEP 3: If Sign Bit of A is 1 Set Q0 to 0 and ADD Divisor back to A.
otherwise Set Q0 to 1.
STEP 4: Decrement Count By 1 and Repeat steps 1,2 & 3 N times.

71
Example

• Dividend=1010 (Q)
• Divisor= 0011 (M) 2’s complement 1 1 1 0 1

A Register Q Register SC
Initially 0 0 0 0 0 1 0 1 0 1 0 0 (4)
Shift left A, Q 0 0 0 0 1 0 1 0
Subtract M 1 1 1 0 1
First
Set Q0 1 1 1 1 0 0 1 1 (3) cycle
Restore (A+B 0 0 0 1 1 0 1 0 0
0 0 0 0 1

72
Example

• Dividend=1010 (Q)
• Divisor= 0011 (M) 2’s complement 1 1 1 0 1

A Register Q Register SC
Aft 1st cycle 0 0 0 0 1 0 1 0 0
Shift left A, Q 0 0 0 1 0 1 0 0
Subtract M 1 1 1 0 1
second
Set Q0 1 1 1 1 1 0 1 0 (2) cycle
Restore (A+B 0 0 0 1 1
0 0 0 1 0 1 0 0 0

73
Example

• Dividend=1010 (Q)
• Divisor= 0011 (M) 2’s complement 1 1 1 0 1

A Register Q Register SC
Aft 2nd cycle 0 0 0 1 0 1 0 0 0
Shift left A, Q 0 0 1 0 1 0 0 0
Subtract M 1 1 1 0 1
third
Set Q0 0 0 0 1 0 0 0 1 (1) cycle

0 0 0 1 0 0 0 0 1

74
Example

• Dividend=1010 (Q)
• Divisor= 0011 (M) 2’s complement 1 1 1 0 1

A Register Q Register SC
Aft 3rd cycle 0 0 0 1 0 0 0 0 1
Shift left A, Q 0 0 1 0 0 0 0 1
Subtract M 1 1 1 0 1
4th
Set Q0 0 0 0 0 1 0 0 0 (0) cycle

ANS 0 0 0 0 1 0 0 1 1

REMAINDER QUOTIENT
75
NON RESTORING DIVISION

76
NON RESTORING DIVISION

77
• STEP 1:
• If the sign of A is 0, shift A and Q left. And subtract Divisor (M) from
A. otherwise Shift A & Q Left and ADD Divisor to A.
• If Sign of A is 0, Set Q0 =1 other wise set Q0=0

• Step 2 Repeat Steps 1 and 2 n Times.

• Step 3 if the Sign of A is 1, ADD M to A.

78
EXAMPLE

• Dividend (Q)= 1010

• Divisor (M)= 0011

A Register Q Register SC
Initially 0 0 0 0 0 1 0 1 0 100 (4)
Shift left A,Q 0 0 0 0 1 0 1 0
1st
Subtract M 1 1 1 0 1 011(3) cycle
SET Q0 1 1 1 1 0 0 1 0 0

79
EXAMPLE

• Dividend (Q)= 1010

• Divisor (M)= 0011

A Register Q Register SC
Aft 1st cycle 1 1 1 1 0 0 1 0 0
Shift left A,Q 1 1 1 0 0 1 0 0 0
2nd
ADD M 0 0 0 1 1 101(2) cycle
SET Q0 1 1 1 1 1 1 0 0 0

80
EXAMPLE

• Dividend (Q)= 1010

• Divisor (M)= 0011

A Register Q Register SC
Aft 2nd cycle 1 1 1 1 1 1 0 0 0
Shift left A,Q 1 1 1 1 1 0 0 0 0
3rd
ADD M 0 0 0 1 1 001(1) cycle
SET Q0 0 0 0 1 0 0 0 0 1

81
EXAMPLE

• Dividend (Q)= 1010

• Divisor (M)= 0011
A Register Q Register SC
Aft 3rd cycle 0 0 0 1 0 0 0 0 1
Shift left A,Q 0 0 1 0 0 0 0 1 0
4th
Subtract M 1 1 1 0 1 001(1) cycle
SET Q0 0 0 0 0 1 0 0 1 1

Result 0 0 0 0 1 0 0 1 1

REMAINDER QUOTIENT 82
FLOATING POINT ARTHMETIC

83
FLOATING POINT ARTHMETIC EXAMPLE

84
85