VLSI Testing
Fault Simulation F lt Si l ti
Virendra Singh
Indian I tit t f S i I di Institute of Science Bangalore virendra@computer.org E0 286: Test & Verification of SoC Design Lecture - 7
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Fault Simulation
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Simulation Defined
Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification:
Validate assumptions Verify logic Verify performance (timing) Logic or switch level Timing Circuit Fault
Types of simulation:
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Simulation for Verification
Specification Synthesis Response analysis y Design changes g Design ( (netlist) )
Computed responses
True-value simulation
Input stimuli
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Modeling Levels
Modeling level Function, behavior, RTL Logic Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Signal values 0, 1 0, 1, 0 1 X and Z Timing Clock boundary Zero delay Zero-delay unit-delay, multipledelay Zero-delay Application Architectural and functional verification Logic verification and test Logic verification g Timing verification Digital timing and analog g circuit verification
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Switch S it h
0, 0 1 and X
Timing Circuit
g gy Transistor technology Analog voltage data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Analog voltage, voltage current
Fine-grain g timing Continuous time
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True-Value Simulation Algorithms Al ith
Compiled-code simulation p
Applicable to zero-delay combinational logic Also used for cycle-accurate synchronous sequential g circuits for logic verification Efficient for highly active circuits, but inefficient for low-activity circuits High-level (e.g., C language) models can be used Only gates or modules with input events are g g evaluated (event means a signal change) Delays can be accurately simulated for timing verification Efficient for low-activity circuits Can be extended for fault simulation
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Event-driven simulation
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Compiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flipp ( p flops) Step 3: For each input vector Set i S t primary i input variables t i bl Repeat (until steady-state or max. iterations)
Execute compiled code
Report or save computed variables
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Event-Driven Algorithm
Scheduled events Activity list
a =1 c =1
0 2
e =1 g =1
T Time sta ack
t=0 1 2 3 4 5 6 7 8
c=0
d, e
d=0 b =1 g
0 4 8
d = 1, e = 0
f, g
f =0 0
g=0
f=1
Time, t
g=1
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Time Wheel (Circular Stack)
Current time pointer max t=0 1 2 3 4 5 6 7 Event link-list
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Efficiency of Eventdriven Simulator
Simulates events (value changes) only Speed up over compiled-code can be ten times or more; in large logic circuits about g g 0.1 to 10% gates become active for an input change
Steady 0 0 to 1 event Large logic block without activity
Steady 0 (no event) ( t)
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Problem and Motivation
Fault simulation Problem: Given
A circuit A sequence of test vectors A fault model
Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors y Set of undetected faults
Motivation
Determine test quality and in turn product quality Find undetected fault targets to improve tests
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Fault simulator in a VLSI Design Process
Verified design netlist Fault simulator Modeled Remove fault fa lt list t t d faults tested f lt Fault coverage ? Verification input stimuli Test vectors
Test Delete compactor vectors
Low
Test generator
Add vectors
Adequate q Stop
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Fault Simulation Scenario
Circuit model: mixed-level
switch-level highMostly logic with some switch level for high impedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults
Signal states: l i Si l t t logic
Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits
Timing
Zero-delay Zero delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback
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Fault Simulation Scenario
Faults
Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault dropping fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large
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Fault Simulation Algorithms
Serial Parallel Deductive Concurrent
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Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. responses Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated
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Serial Algorithm
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together
Test vectors Fault-free circuit Circuit with fault f1 Comparator Circuit with fault f2 Comparator Circuit with fault fn fn detected? f2 detected? Comparator f1 detected?
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Parallel Fault Simulation
Compiled-code method; best with twostates (0 1) (0,1) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates p p w-1 new faults, where w is the machine word length Speed up over serial method ~ w-1 Not suitable for circuits with timing-critical and non-Boolean logic
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Parallel Fault Simulation
Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1
1 1 1 1 0 1 1 1 1 0 1 1
a b
c s-a-0 detected
1 0 1
e
0 0 0 s-a-1 0 0 1
s-a-0
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Deductive Fault Simulation
One-pass simulation Each line k contains a list Lk of faults detectable on k Following true-value simulation of each vector, fault lists of all gate output li t f lt li t f ll t t t lines are updated using set-theoretic rules, signal values, and gate input fault lists PO fault lists provide detection data Limitations:
Set theoretic Set-theoretic rules difficult to derive for nonnon Boolean gates Gate delays are difficult to use
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Deductive Fault Simulation
Notation: Lk is fault list for line k kn is s-a-n fault on line k
a b
1 1 {b0}
{a0} {b0 , c0}
Le = La U Lc U {e0} = {a0 , b0 , c0 , e0}
c d
e f
{b0 , d0}
{b0 , d0 , f1}
Faults detected by the input vector
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U U
Lg = (Le Lf ) U {g0} = {a0 , c0 , e0 , g0}
Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault free circuit fault-free circuit. A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains f fault ID, gate input and output values and internal states, if any. All events of fault-free and all faulty circuits are y implicitly simulated. Faults can be simulated in any modeling style or detail supported in true-value simulation (offers true value most flexibility.) Faster than other methods, but uses most memory. memory
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Conc. Fault Simulation
0 1 1 1 1
a0
1 0
b0
0 1
c0
0
1 1
e0
0
a b
c d
1 1 0
e
0
1 0
0 0
a0
0 1 0
b 0 0
1 0 1 1 1
0 0 1
c0
0 1 1
0 0 1
e0
0
0 1
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b0
0 1
d0
1 1
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f1
g
0
f1
d0
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Thank You
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