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Fault Simulation
Problem and Motivation
Fault Simulation Problem:
Given A circuit A sequence of test vectors A fault model Determine Fault coverage
Fraction (or percentage) of modeled faults detected by test vectors
Set of undetected faults
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Netlist Fault list Test set Fault Simulator Fault Coverage Statistics
Motivation:
Determine the quality of a given set of test vectors (test quality). Find undetected faults with respect to a given test set.
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Usages of Fault Simulators
a) Test grading
Determine the quality of a given test set.
b) Test Generation
Generate set of vectors to detect a set of faults.
c) Fault diagnosis
Identify the location of a fault.
d) Design for test (DFT)
Identification of points that may help improve test quality.
A typical use
F is empty STOP Generate Test for some fault in F
Select Target Fault Set F
Fault Simulation
Remove Detected Faults from F
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How to simulate faults?
A simple fault simulation algorithm can be obtained by repeated use of any logic simulation algorithm.
For each vector, simulation of the fault-free version of the circuit can be followed by simulation of each of the faulty versions of the circuit. If n k number of input vectors number of faults
Then, number of simulation runs = nk
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Some Basic Concepts
Fault Masking:
A single-fault test can fail to detect the target fault if another fault is also present.
0 0 0 0 y/1
x/0
The fault y/1 prevents the fault x/0 from being detected by the vector 0000.
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Redundant Faults:
For some faults, no tests may exist. Such faults are untestable. Arise due to some redundancy present in the circuit.
a f x/1 b
Untestable
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Fault Collapsing:
The number of faults that need to be simulated can be decreased by exploiting two relations between a pair of faults fi and fj : a) Fault equivalence b) Fault dominance Used to reduce the fault simulation time.
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Fault Dropping:
It is the practice in which faults detected by a vector are deleted from the fault list prior to the simulation of any subsequent vector. Decreases complexity of fault simulation. Cannot be used for all fault simulation algorithms.
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Fault Equivalence
Definition:
Two faults fi and fj in a circuit are said to be equivalent if the corresponding faulty versions of the circuit are identical. All tests that detect fi also detect fj . Example: An input s-a-0 and output s-a-0 in an AND gate.
A point to note:
Number of fault sites in a gate-level circuit = #PI + #gates + # (fanout branches)
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Equivalence Rules
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1
AND
sa0 sa1
sa0 sa1 sa0 sa1
WIRE OR
sa0 sa1
sa0 sa1 sa0 sa1 sa0 sa1
NOT
sa1 sa0
NAND
sa0 sa1
sa0 sa1 sa0 sa1
NOR
sa0 sa1 sa0 sa1
sa0 sa1 sa0 sa1
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FANOUT
Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32
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sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
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Number of lines = 16 Number of single stuck-at faults = 32 Number of faults removed by equivalence collapsing = 12 Thus, collapse ratio = 20 / 32 = 62.5 %
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Contd.
Fault collapsing using equivalence relation:
All single faults of a logic circuit can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset.
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Fault Dominance
Definition:
If all tests for some fault fi also detect another fault fj, then fj is said to dominate fi . If two faults fi and fj dominate each other, then they are equivalent.
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Example:
fi
fj
A 3-input AND gate. fi s-a-1 fault in one input of the gate fj s-a-1 in the gate output Tests for fi Tests for fj 011 000, 001, 010, 011, 100, 101, 110
Thus, fj dominates fi .
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Fault collapsing using dominance relation:
If a fault fj dominates another fault fi, then fj can be removed from the fault list. In a tree circuit (without fanouts), the primary input faults form a dominance collapsed fault set. Proof straightforward
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Observation
In general, the complexity of identifying all fault dominance and equivalence relations is high. Hence, in practice, the equivalence and dominance relations identified between single stuck-at faults associated with inputs and outputs of gates are used in an iterative fashion to achieve significant fault collapsing.
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An example:
A B f2 : s-a-0 f
f1 : s-a-1 f1 dominates f2 though not obvious from the characteristic of the gate alone
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Checkpoints
Definition:
Primary inputs and fanout branches of a combinational circuit are called checkpoints.
Checkpoint theorem:
A test set that detects all single (multiple) stuck-at faults on all checkpoints of a combinational circuit, also detects all single (multiple) stuck-at faults in that circuit. A SIMPLE HEURISTIC FOR FAULT COLLAPSING.
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Alternatives to Fault Simulation
Prototyping with fault injection capabilities
Costly Limited fault injection capability Design changes hard to implement Long lead time
Hardware emulators
Costly Require special hardware
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Fault Simulator in a VLSI Design Flow
Verified design netlist Fault simulator Modeled fault list
Remove tested faults
Verification input stimuli Test vectors
Delete Test compactor vectors
Fault coverage ? Stop
Low
Test generator
Add vectors
Adequate
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Fault Simulation Algorithms
Serial Parallel Deductive Concurrent Others
Critical path tracing Parallel pattern, etc.
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[A] Serial Algorithm
Algorithm:
Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list: Modify netlist by injecting one fault. Simulate modified netlist, vector by vector, comparing responses with saved responses. If response differs, report fault detection and suspend simulation of remaining vectors.
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Advantages:
Easy to implement; needs only a true-value simulator, less memory. Most faults, including analog faults, can be simulated.
Disadvantage:
Much repeated computation; CPU time prohibitive for VLSI circuits.
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Serial Algorithm (Cont.)
Alternative: Simulate many faults together.
Test vectors
Fault-free circuit Circuit with fault f1
Comparator
f1 detected?
Comparator Circuit with fault f2 Comparator Circuit with fault fn
f2 detected?
fn detected?
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[B] Parallel Fault Simulation
Takes advantage of multi-bit representation of data and availability of bitwise operations.
Compiled-code method. Works best with two-states (0,1).
Extends the basic concept of parallel logic simulation.
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Basic mechanism:
In each pass of simulation, the fault-free circuit as well as (W-1) faulty versions are simulated in parallel for a given vector, where W is the machine word length. If q faults are to be simulated for a vector, q/(W-1) passes are required. Fault dropping cannot be used.
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How to insert faults?
For each fault, an appropriate fault mask is used to insert the effect of the fault at its site. For each line, the fault mask is comprised of two W-bit integers, MZ and MO.
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Line under consideration (Cj)
ith bit of mask ith bit simulates
Fault-free version of circuit Faulty circuit with Cj / 0 Faulty circuit with Cj / 1 Faulty circuit with a fault not located at Cj
MZ
1 0 1 1
MO
0 0 1 0
If Z denotes the logic value (vector) computed at Cj, it is corrected using the expression: Z = (Z AND MZ) OR MO
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Parallel Fault Simulation Example
a b
1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 1 1 1
c/0 detected
e/0 detected
c
1 1 1 1 1
e
0 0 1 0 0
1 0 1 0 1
Fault free
c/0
f/1
e/0
e/1
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Fault Masks:
a b c d e f g MZ : 1 1 1 1 1 MZ : 1 1 1 1 1 MZ : 1 0 1 1 1 MZ : 1 1 1 1 1 MZ : 1 1 1 0 1 MZ : 1 1 1 1 1 MZ : 1 1 1 1 1 MO : 0 0 0 0 0 MO : 0 0 0 0 0 MO : 0 0 0 0 0 MO : 0 0 0 0 0 MO : 0 0 0 0 1 MO : 0 0 1 0 0 MO : 0 0 0 0 0
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[C] Parallel-Pattern Single-Fault Propagation (PPSFP) Basic idea:
A batch of vectors are simulated in parallel. If the fault list contains q faults during the simulation of a batch of W vectors, then their simulation is carried out in a total of (q+1) passes. In each pass after the first, one fault is inserted into the circuit.
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Faster than parallel fault simulation.
Computation of logic values is faster at all lines except at the fault site.
Limitations:
Applicable to combinational circuits only.
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[D] Deductive Fault Simulation
This method utilizes a dynamic data structure:
One-pass simulation. Each line k contains a list Lk of faults detectable at k.
It comprises of two (interleaved) steps:
a) Fault-free circuit simulation is performed for the given vector. b) The value implied by the vector at every line in each faulty circuit is deduced (using set theoretic rules).
Originally implemented for 3-valued logic.
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Fault List:
The fault list Li associated with line i is the set of all faults {f} that cause the values of i in N and Nf to differ at the current simulation time. N is the fault-free circuit, and Nf the circuit in presence of fault f. If i is a primary output (PO), then Li is the set of detected faults.
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Computation of fault list:
Uses a method called fault-list propagation. Performed when one of the following occurs: Logic event: change in signal value of an input or output line of the gate. List event: change in the fault list of one or more inputs of the gate.
Some illustrative examples to illustrate computation of fault list is shown next.
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A B
1 1 1
LZ = LA U LB U {Z/0}
A B
1 1 0 Z
LZ = LA U LB U {Z/1}
A B
0 1
LZ = (LA LB) U {Z/1}
0 Z
= (LA LB) U {Z/1}
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Limitations:
Set-theoretic rules are difficult to derive for complex gates and higher-level functional blocks. Gate delays are difficult to use. Memory requirement is unpredictable.
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An Example
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[E] Concurrent Fault Simulation
Basic motivating factor:
Most of the time during simulation, most of the values in most of the faulty circuits agree with the corresponding values in the good circuit.
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Basic concept:
The fault-free version of the circuit, and each of its faulty versions, are concurrently simulated for a given vector. Simulates the good circuit N. For every faulty circuit Nf, simulate only those elements in Nf that are different from the corresponding ones in N.
EVENT-DRIVEN APPROACH
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Data structure used:
Concurrent fault list, in which entries are of the form: < fault, input_values, output_value >
a b 0 1 0 c
a/1 : 11; 1 b/0 : 00; 0 c/1 : 01; 1
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Alternate way of representing the fault list
a b 0 1 1 1 0 0 0 1 0 c
a/1 b/0
c/1
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Maintaining the fault lists:
Information about a fault will be entered in the fault list if one or more of the following conditions are satisfied: a) The fault f/x is local to the gate. b) The value implied at at least one input or output of the gate is different from that implied at the corresponding line in the faultfree version of the circuit.
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Initially, the values of all lines are set to the unspecified state X. An entry is removed from the fault list if the corresponding input/output values are identical to that of the fault-free circuit.
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Advantages and limitations:
Runs faster as compared to deductive fault simulation for most of the circuits. Memory requirement is higher since the sizes of the fault lists are greater. It can easily be extended to cases where the results of fault simulation depend on timing of events. Delays of the gates can be different.
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An Example
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[F] Critical Path Tracing
Differs from the paradigms discussed earlier in two main ways:
a) The method targets all faults within certain parts of a circuit. The complexity of fault simulation is independent of the number of faults. b) The method can only be applied to fanoutfree circuits, in its strictest form. Handling of fanouts requires explicit simulation, and hence more computational overheads.
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An Example
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Fault Sampling
A randomly selected subset (sample) of faults is simulated. Measured coverage in the sample is used to estimate fault coverage in the entire circuit. Advantage:
Saving in computing resources (CPU time and memory.)
Disadvantage:
Limited data on undetected faults.
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Motivation for Sampling
Complexity of fault simulation depends on:
Number of gates Number of faults Number of vectors
Complexity of fault simulation with fault sampling depends on:
Number of gates Number of vectors
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Random Sampling Model
Detected fault All faults with a fixed but unknown coverage Np = total number of faults (population size) C = fault coverage (unknown) Random picking Ns = sample size Ns << Np c = sample coverage (a random variable) Undetected fault
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Summary
Fault simulator is an essential tool for test engineers. Concurrent fault simulation algorithm offers the best choice. For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size.
The method has significant advantages in reducing CPU time and memory needs of the simulator.
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