Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division
Digital Learning Handout
Course Title TESTABILITY OF VLSI
Course No(s) ES ZG532 / MEL ZG531
Credit Units 5
Credit Model Theory
Content A uthor
Instructor Incharge SANJAY VIDHYADHARAN
Course Description:
COURSE OBJECTIVES
CO1 Understand the basics of designing a testable chip to increase the yield
CO2 To understand differences between defects and faults related to chip design
CO3 To learn various fault models, design rules, test pattern generation for combinational
and sequential circuits
Text Book(s):
T1 Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits”, Michael
L. Bushnell and Vishwani D. Agrawal, –Kluwer Academic Publishers (2000).
Reference Book(s) & other resources:
R1 Digital Systems Testing & Testable Design ”, Miron Abromavicici , Melvi Breuer & Friedman
R2 VLSI Test Principles and Architectures: Design for Testability. Laung-Terng Wang, Cheng-Wen
Wu, Xiaoqing Wen. Elsevier, 14-Aug-2006
R3 Digital System Test and Testable Design: Using HDL Models and Architectures. Zainalabedin
Navabi.Springer Science & Business Media, 10-Dec-2010
COURSE OUTCOMES
LO1 Apply the concepts of chip testing to help design a better yield in IC design.
LO2 Analyze the problems associated with testing of integrated circuits at earlier design levels to
reduce the testing costs.
LO3 Identify the design for testability methods for combinational & sequential circuits
LO4 Apply appropriate fault verification techniques to minimize chip faults after fabrication
Experiential Learning Components:
Students will be given case studies to refer from various conferences and journals in
the area of testability and present.
Content Structure:
Contact List of Topic Title Sub-Topics Reference
Hour
1 Introduction Introduction to VLSI T1-Chapter 1, 2
testing and DFT & 3
Technology Issues
Failure patterns
Automated Test
Equipment
2 Fault Modeling and Logic Stuck at faults T1-Chapter 4
Simulation Propagation &
detectability of faults
Check Point Theorem
Fault equivalence.
3 Basic Fault Simulation Fault simulation – T1-Chapter 5 &
primary Inputs, Primary 6
Outputs, fault
sensitization. ROTH’s
Test Detect algorithm,
SCOPA measures for
circuit
4 Testability Measures nodes and Observation T1-Chapter 5 &
measures for 6
combinational circuits.
SCOPA measures for
sequential circuits.
5 Basics of Combinational ATPG ATPG search space. T1-Chapter 7
Fault propagation &
detection
Fault cone and D-
Frontier approach.
Algorithmic procedure
for sensitization –
propagation and
detection of stuck-at
faults.
6 ATPG Algorithms ROTH’s D algorithm ; T1-Chapter 7
example
PODEM algorithm ;
example
Other Algorithms.
7 Sequential Circuit Test Time Frame expansion T1-Chapter 8
Generation approach
Use of nine-valued
Logic .
Multi cycle test process
with test vectors ;
example
8 Review session
9 Delay Test Methodology Path delay testing for T1-Chapter 12
timing critical paths. & 14
ON & OFF PATH
segregation.
Path delay sensitization
5 valued logic usage.
10 Scan Based DFT Scan design rules. T1-Chapter 12
SCAN sequence & 14
Use of LSSD cells for
delay testing.
DFT error fixes for
digital circuits to enable
SCAN based testing
11 BIST – Pattern Generation BIST architectures. T1-Chapter 15
Pseudo Random Pattern
Generation.
LFSR as pattern
generator and signal
analyzer.
LFSR theory.
Modular LFSR &
characteristic
polynomial.
Primitive Polynomial
and Companion Matrix.
12 Response Compaction Response compaction – T1-Chapter 15
Polynomial division
MISR
BILBO structures.
13 Memory Test and BIST for Functional memory T1-Chapter 9 &
Memory model Types of faults 15
MARCH tests
Memory BIST
14 IDDQ Tests and Boundary Scan IDDQ testing T1-Chapter 13
IC configuration for & 16
15 Boundary Scan Boundary Scan T1-Chapter 13
Boundary Scan control & 16
features.
Boundary scan Test
Cell. TAP controller
and states.
TEST instructions.
Test Bus configuration
Basics of Boundary
Scan
Description Language
16 Review session
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
Evaluation Name Type Weight Duration Day, Date, Session,
Component Time
EC – 1* Quiz Online 10% 1 week September 1-10, 2023
Assignment/Lab Assignment Online 10 % 10 days October 1-10, 2023
EC - 2 Mid-Semester Test Open Book 30% 2 hours
Friday,
22/09/2023 (AN)
EC - 3 Comprehensive Exam Open Book 50% 2½
hours Friday,
24/11/2023 (AN)
EC1* (20% - 30%): Quiz (optional): 5-10 %, Lab Assignment/Assignment: 20% - 30%
Syllabus for Mid-Semester Test (Open Book): Topics in Contact Hours: 1 to 8
Syllabus for Comprehensive Exam (Open Book): All topics
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with
the latest announcements and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on
the Elearn portal.
Evaluation Guidelines:
EC-1 consists of either two Assignments or three Quizzes. Students will attempt them through
the course pages on the Elearn portal. Announcements will be made on the portal, in a timely
manner.
For Closed Book tests: No books or reference material of any kind will be permitted.
For Open Book exams: Use of books and any printed / written reference material (filed or
bound) is permitted. However, loose sheets of paper will not be allowed. Use of calculators is
permitted in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material
is not allowed.
If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam which will be made
available on the Elearn portal. The Make-Up Test/Exam will be conducted only at selected exam
centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study
schedule as given in the course handout, attend the online lectures, and take all the prescribed
evaluation components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam
according to the evaluation scheme provided in the handout.
