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VLSI Design and Testing

This document provides information on the course "VLSI Design Verification & Testing" including the course code, category, credits, learning objectives, content, textbooks, assessment methods, and outcomes. The course aims to teach students testing and verification in the VLSI design process, ATPG concepts, and sequential circuit testing. It covers topics like high-level synthesis, logic synthesis, formal verification methods, model checking algorithms, binary decision diagrams, and digital testing techniques. Students will be assessed through weekly tests, monthly tests, and an end semester test. Upon completing the course, students will be able to apply testing concepts to improve IC design yields, tackle testing problems early in design, and understand verification and testing algorithms.

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430 views2 pages

VLSI Design and Testing

This document provides information on the course "VLSI Design Verification & Testing" including the course code, category, credits, learning objectives, content, textbooks, assessment methods, and outcomes. The course aims to teach students testing and verification in the VLSI design process, ATPG concepts, and sequential circuit testing. It covers topics like high-level synthesis, logic synthesis, formal verification methods, model checking algorithms, binary decision diagrams, and digital testing techniques. Students will be assessed through weekly tests, monthly tests, and an end semester test. Upon completing the course, students will be able to apply testing concepts to improve IC design yields, tackle testing problems early in design, and understand verification and testing algorithms.

Uploaded by

sirapu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Rajiv Gandhi University of Knowledge Technologies, NUZVID

Department of Electronics & Communications Engineering

Course Code Course name Course L-T-P Credits


Category
EC 3243 VLSI Design Verification & Testing PEC 3-0-0 3

Course Learning Objectives:


1. In this course the student will learn testing and verification in vlsi design process,
ATPG concepts and sequential circuits

2. To expose the students, the basics of testing techniques for VLSI circuits and Test
Economics.

Course Content:

Unit - I (9 hours)
Introduction, Overview of VLSI Design Flow,High Level Synthesis (HLS) Overview
,Scheduling in High Level Synthesis (HLS),Resource Sharing and Binding in HLS

Unit - II (9 hours)
Logic Synthesis, Physical Design, Intoduction to formal methods for design verification,
Temporal Logic: Introduction and Basic Operations on Temporal Logic

Unit - III (9 hours)


Syntax and Semantics of CTL, Equivalences between CTL Formulas, Introduction to
Model Checking, Model Checking Algorithms, Model Checking with Fairness.

Unit - IV (9 hours)
Binary Decision Diagram: Introduction and Construction, Ordered Binary Decision
Diagram (OBDD), Operation on OBDD, OBDD for state Transition systems

Unit - V (9 hours)
Symbolic model checking, Introduction to Digital VLSI Testing, Functional and
Structural Testing, Fault Equivalence, Fault Simulation

Unit – VI (9 hours)
Testability Measures (SCOAP) , Introduction to Automatic Test Pattern
generation(ATPG) and ATPG Algebras, D-Algorithm, ATPG for synchronous sequential
circuits, Scan Chain based Sequential circuit testing, Built in Self Test (BIST)

1
Rajiv Gandhi University of Knowledge Technologies, NUZVID
Department of Electronics & Communications Engineering

TEXT BOOKS:

1. Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman, “Digital Systems


Testing and Testable Design,” Revised, IEEE Press (1990)
2. Samiha Mourad and Yervant Zorian, “Principles of Testing Electronic Systems”,
Wiley (2000)
3. Michael L. Bushnell and Vishwani D. Agrawal, “Essentials of Electronic Testing,
for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer Academic
Publishers (2000)
Video Reference Link:
1. Prof Arnab Sarkar, IIT Guwahati, VLSI Design Verification and Test, URL:
http://nptel.ac.in/courses/117103125

Assessment Method
Assessment Weekly tests Monthly tests End Semester Test Total
Tool
Weightage (%) 10% 30% 60% 100%

Course outcomes: At the end of this course student will able to


CO 1 Apply the concepts in testing which can help them design a better yield in IC
design.
CO 2 Tackle the problems associated with testing of semiconductor circuits at earlier
design levels so as to significantly reduce the testing costs.
CO 3 Acquire knowledge Model checking and designing algorithms
CO 4 To understand construction, current application and research into BDD
machines.
CO 5 Acquire knowledge about fault modelling and collapsing
recognize the BIST techniques for improving testability the performance of radar
CO 6 systems

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