— ee ewe CHAPTER 04 42) sacs a . prersc Means Complex Tngtreuc-lion Sof ‘Omsel OM pUSEI 6 perse f5 a type of preocessore where SINGLE nsdrcvcrtory, ' | ‘onn @an execute Several ow-Jevel opercations (such a, , y > doad ficorn memory, an arithmetic operation, anf a mMeEMo "ty dotore) > or are capoble of multi-step openatons ort addre- $51] Moder catthin Single inptreuctions. this makes the CISC vimetreucttons shor bod Scomplex’ - »075C preoce 1g werte helpful uf king ud Shorcdet : a ode yak fc shore ire artdert to! ree Code and 7 < ont coment. rroquircey the memor Y h cocessores amd mucicocon. Ircodterts had have CISC > Micreoprcoces Sorts iicchikeotune uncludes Motorcolo 600, 6809 and 620007 2080, and x86-damily 5 Intel families; athe undel 208 e064 ~Samity .¢ the code vsize uz comportadtyely sehorcter ushich vrurumizes the memory requircementk. + Execution of o single inskeuction accompiubhes deveral Jow-uever tasks. ainnddrossing ie € ™memorny Srtom, i vantages Zz ws munimized bud Ut elock eyekes do execute & Hon 3 F Therceby reeduce sthe overcall of athe computer . ‘Sort CISC instevetfon ap eeet| 1 * The hartdwarce nircuctune needs do be more compl 5 F ex do vimpsidy wotiwone dmplementotion * Designed to Minimize Lhe memory reequircemnen) whew |memony War sematierc and cosilert. Bot today the Heenarao har changed mowadarsn memory un ‘Tmexpen_ sive and mosity all computens have o Jarege amount of memory . RISC Processon RISC meant Reduced Instruction Set Compuders. |+ rIsc una ype oS micropreecessort atchitecture that usilizes © moll, highly — opdimived net of inntituetions +h than a& more ecialized net of unsarcuetions reathert J . ne that the rcequirced opertands _», RISC vey Lems @ preocessor’s registers, noe Mn the main ane un the 2 7 ue memory— The use os ARM arcchitectune processors tn Smartphones and dablet compudsercs such arthe dpad and Andiroid devices pitovided a wide. usert base fore R1SC- based nysteam Advantages of RISC Processorc e arte Simplerc and * RISC preoeessorrs are also used In Superecompotens, Unix warcksdalion, embedded preocessorns in Jasert prumtercs, routers and similar products. i Os aw a 7 w 7 * ‘ if q i 3 fewert machine instruction. } e are tar Joos cto fasten the execution, h gimple addr essing modes. © ertecudes santerc b ge@ most OF Insetreuction opercates on prtot or neqistert and there i6 mo need to access memory tore each instrevetfon, : © oxecute one imstrtuchon per cloak cycle . ( ( ( ( (] Disadvarrtages oS RISC Processose | e RISC Instruction ize is seduced bud more Ineaetee OS are requirted to percform on operation when compared with CISc. °-the machine instructions are hardwired tn RISC 50,74 would cost if any insdrwotion needs modificatton eu Finds ig difficulty in processing complex instreoction and complex addrressing mode. « do nod alow dicect memory do memory aramsyert, db requires Load and rotorce, insdreuctions cto, do s0+ Advantages oF High-level Languages program development is Fosterc — Preogrrams arte easiert do maintain Prognams are portable.7 CISG ¥S RISC ecIsc RISc |® Emphasis on hardwarce @ Emphasis on roStwarte |imchades mudsi- clock Com- Single-clock reduced [Plex singdreactions. inatreuction only. " Load and mtorre” incore | @ Memory to mMeMo NY : @® Reg.ir tore to register? “Load ond niorce. arte 4 porcated tn Instrcuctions | undependend- insdreuetig @ Small code sizes, high @ low cx Cycles pert Second dastp é zy * { i+ t sh tOrUNg = memor 6 ft ‘ (5) The machir | ome fy of -denpth Machine rind 4} lanavage msinettom.Assembly Language > Loe eves Pigeon ming Jangvuage 14 helps in dercrd anda the Preagreareming Code. Homguage do machine eats Od High Ate er nasal © 14 attownr compiler cobs to rtun Sn a imple way. | © » © \ * It 16 Memory eSficierc, or it teequires Less memorcy. | d © 1 5 torte dn npoed, ar its oxecudiondime wr less. \ fe Tt is maindy hardware ortionsed. | jo Tt requirces Less insdruetion to get the. result. |, it is used Gore artifical gobs Cime-cretioal dobs) le 14 is not reequirced do keep track of memory Locations Having en underdadonding oS Assembsy Longuoge makes one. aware of —» eHow programs injorcfaice with 06, Processor, and 81055 j @ How dato. vik) eprresented In memory amd ofhere external devices, ad * How the preocessose accesses and execd 5 dada 5 8. ctions access and Proc devices « unsinve tion) 5 i © How Unrdru al @ How a program accesses extern_Disacventoges 0; os J Assembly Lange jagye. J@ Et cakes o tod oS dime and eSford so eurtite, the. cade | Yoore the ame. The syntax wr» diSicust do rememberc. | Jed has a Jack of porctability between disferent Computers Assembly Lang age, Preagream. MopEL SMALL STACK 100H OATA A OW 2 | B® DW §umM Ow ? CODE MATN PROC imitiotize 0S MOY AX DATA MoV 05, Ax add the nombery Mow Ay,iqi 70AX bonie ADD AX By Ax has BIB Mov 5uM, AK 5 SUM=A+Bext depos Mov ax,4¢oot i | INT 94H MAIN END? END MAIN Assembly Language therce arcehoure parcts : 1. Model Segment 2an assemblerc dircorttye thad Specifies the.size oS the PICGA Kear 2.Data Segment s vardables are declarced in +he € dado. Segment: 9, taok eqament * Temportarcy gdorrage of addresses rnd data ‘ode Segment 1A preognom’s ingdreugtions seam placed in the code segment.CHAPTER- 02 3) Threee-Adldicess Machines t= @aA=6+CKD+A is converted do the following Code: mult 7,050 5 T= cxD add 7,78 $ 1=BtCxO add ees A= B+ C*DTA @ N=O+C#D-E+F+A we convercted do the folowing Code : add F185 T=8+c%D Sub TEE T=-B+C*D-E add he, =| = OtCtD-Eie A = B+CxD-E+F the | mult GG) 9 T= C*D | | add ALALT 95 2/3 Address and Load - Stowe CodeJoo - Addreess Machines : @ A=G6+C*D4A > converted to the following Code: J ad FC Ba—c ; mult Gp C*D } add Tape -8t+c*D add AsT 3 A=6B+C#D+A @A=6+Cx0-E4F4A > conveitied to the Follocing Code + load T¢ °° 5 T=C mult D see CXD watt E 7 P+0*D-ESE / iE ¢ [ A, > = B+cxD-E+F+AA= B+DXF-0/64-A conyers td @-address, 2-addicess and Joad/ store micheteeturce « B-addice Machines: wr» Convertied do tthe. folowing Code + mult T,D,F 3 =D*F dévi TGB +m =¢/e 606 Wiaeea, 3a = DXF -Cis add T4118 5 Ta = B+D*F-¢/8 add Th, 1A 5 Tl =B+D#F-c/e+A MOVE. AsTz 3 move dhe value of ta MA address Machines + ie eonvercted to the following code oad Ty,D > mult Ty, F 9 14 = D¥F Joad h,0 5 divi 1,85 h= ¢/6 add 14,83 Th = B4DKF sub Ta) Th = BADIF- O/B add Asa 3 Ty = B4D*F-C/p4+A Move A,T, } move +the value of Ta 1 Aethe loa d/Store Arehitectore + A=B+DxE e/B+A i» convercded 40 the following Code t= load RB,B ;doad B Joaf RD,D »1ood D load RFsF 3Joad F | oad Re,@ ;soad c Joad RB, B ; toad B | doad RA,A >JoadA mouJt RO, RD» RF , RD-pD*F divi Re, RC, RB 5 Re = C/B add = RD, RD, RB! 5. RD = B+DKE Sub RD, RD, RC 5 RD =6hD*F-e/B add RDRD,A 53RD - B+D*F-c/g4p Joforte A, RD > Storce the reguld A The tinal resudt wilt be A=B+0%F -e/B 4Andorte A; RC ~The fal reso witt be . yay1) gob © RO, RORE 05 RC B+CKO-E add RC, RO,RF ; RC = BACKD= add ROR, RA 3 RO=B+CKD-E hdorte X oS RC sesolt * the final result ig x -@4) Cock eyole, Clock perdod, epeed oF precessote «earth, Clo eyelet jeflee J lr | __ = Glock signa! 5a | = | Computer System. the dime. perciod oS this clock signal %6.colled Clock cycle. 74 i6 dhe. pmabiers dime onid Sort 0. ‘micrcoprocessore. Clock, porciott : ‘ MHz = 10° ‘ GcH? = 10” a Clock period = Cocks $reequency Fro1. Clock 4rcequemcy 4GcH7 what will bethe clock er > we know, . Clock petaod ick a f 4 = 4%10? dng [vlo?=dnm] os Anothert point! Answer Glock petiod Clock cxcler +o Cxeecnoianenss 2, alock eye le&+6 execute an instruction it fakey 3x4ns =3nsCHAK IDK VO 5!) Differconct ype. oF reegistercs, dheire function __ > Therto. ane disfercent types of reegioterc A. Geemerta! Registert aa aaa eeah aN data pointer. Index reegisterc regisierc register Sourtce Destination iimdex Index 2. Control register 3—Imdere. register 4. Seqmen+ reegisterc 4. Grenercal Register : lsean be used Sorc any mathematical, logieal and data qmoyvement operations. = can be divided into 4-byte,2-byte and 4-byte- 4. Docta Registerc : Fourt 46-bit meegistervs AX (Acevmota tort) + BX (ase) Ox (courctet©) > py (deta)[ Eight &-bit Registervs AH AL BH BL CH an DU -DL ° AX (Accumosatore Register) > AX Stands fore Accumvuiator Register. ~» osed to perform aruthmetical, Logical and dosto. movement operco-hons € AY ——— AL (Lower Byte) ——+ Corctains 4-B H+e(e bits 3 fa) contains 1+ byte (g-bi15) 5 contains g- byte (a6-bits) ( 92-bits) AH (Highe tc Byte) AX EAX( Extended) ——? Contos 4-byte © Fonction: Stortes Data fore ALU opertacoms2BX (Base Regicterd : @ BX Stands fore Base Legiste re 2. < Bx 46 ee | BL CLowere Byte) ——> 4-byte | BH CHighere @yte) —> 4 byte Bx 3 2 byte EBX (Ex-tended) 4 byte fonction = Con-tains adhe address of othercmemory location e C¥ (Courrterc Register) t > 0¥ tlands force Counter: Regisite tr — same | a cH eL | 15 eo me *L (Locwere Byte > d-byte GH ( Highert Byte) —? 4-by te ex byte EG@x ( Extended) 7 A-byte ¢ Function ; Used Son Loop or counterc PUMpose< DX (Dato Registe): cag ay aa totands Pore Data a Aol re: ~ same rh ‘ts ; ited Di-Clowere byte) —> 1-by te DH CHigherc byte) —> 4 ~byte bY 92 - Gertes EDX (Extended) 94> byte (32. bit) *Funeton : Usedin mubiphcation and division operestis | 2. Poin-tere Re gisterc: ot Bombs, aka 9 : Ber a GP Fonction: used +o maintain the y4a0k. Sdack pol nte rc Base pofnterc 3. Inaex Re. tere edo parcté + 4, Source. Index (61) + Osed-to torte an offset addres fort s00nee opercand > SI megisten work with DS.* Destination andex(D1) r 11 is used do Jotorte. om offset laddtress Fone destination opercand * DI reegisterc worck fore ES 5S: pt Inder _registerc ESI 31 | Sourcee yrdex Destination Index 34 46 45 oO Funetion: used in st rang movement inettuctions 2 Coen rerc: two 39-bit reegisterr 4, pointore registerc 2. Flog registerc Function? Corto} Hag is Used in totnéng operations - strung opettections should hcan the birang q in the +ortwarttd-to backwartd direction Zoe qislerc; Six Segment Register CS, DS, $9, ES,FS,65 Fonctior tO re comaining da-ta, Code and backC Segment Registers; “the prrocessore at any Poirtin-lime, eam onig access up to six Segments oS the. main METNOICH. “the six | Segment Megistorve poitrtdo asherce these. Segimercts ave Jtocated Jn phe memory: | 4.05Cepde Segment): - the. code Segment (cs) reegisterc potmts Aocwherce the Programs wmbtrroctionrs are tetorced an the. NaN memorcy « 2- DS (Dota Segment): > Ds rtegistere ig the deJauit base Jocation fore memory varuables > @PuU caleylates the offsets addrtess of yartiable, + points 40 the data pard of the prcog ica ( Stack Gegrnerct \s the ust clas gmerct ( 55) registerc pointstothe € program pidock segment too opertations : push, pop PUSh : Push operation ig used to mserct olement onto athe Jotack. por = Pap ” ” » " delete element from yedack «Te . ES(CExtra eget) » x | 5. BS eOboctra segmend) & | 6. Ge6( Extra segment) The Jast athreee Segmnemt megisterd> —ES,FS and Gs — ore additional Segment registers that can be used in a Simitarc way ay athe oxherc Segment = | Wa prcogrcanns decta could registerv>: Fore example, not fit into a single dato Segment, we could vse 5 Jawo regmeni register» to potrt tothe devo dota 4: § | 15 oO ‘ CS code. Segment DS pacto. Segment Eo stack Segment sa Eoctrea Segrnenct Boetrea Segmer| GS |e +10. Segment tthe six Segment regis tere» oS the pontiom prwcessortCHAPTER : 04 ) 6 . 1) I, Mrevelion Mercrrociea (ee chapleeen 1,° ; the MOY Tnadreaetion + ~ho dacta are. copied Brom, feoree cto destination and ahe rourtee opercand rtemaing unchanged « Both opercands Jshould be oS the hame hizel e / 2015-410: Stel Moy regi tere, eg isterc ® mov Megesierc, irom ediate * Moy memory, immediate e@ mov », ¢ 2 MAME registerc, me ‘d The INC and DEC Imsdrcvetion® The inc (inc rement) Hislreaetion adds one to its operand and the dec (DEC Reme nd) dnstrevetion adds one -to its operand andthe dec DEC. rcement) instruction both insdrcuctions mequirte ingle operand The opercand can be oidher an a reegisterc ore in memory $Poth Unyrtreuetfons require a Sir 2 apercand +The opera: t t saintere Ort In Memory. can be eidherc Tn a reg, tere Or d Tne destination dec destination3. The o Add Ingircuction + ‘ >The add dmedroet can be eae 3008, ome bid operands. the sitar is — add destination, sourtce The semantics of the add inntrwetion are - destination = destination + Sourcee |The sub (Subsriact) Unrsdreuction can be used to hubstract dwo &-,416-ore 32-bit nomberts The synta Jb > > Sub destination, sourtce +> The Source opercand uh pubsracted 4rcom the destination operand and dhe result > placed fn dhe destination destination = destination — Soustce5. The XCHGe Instrections OE eR ie The xchg imptreaction erechanges g-, 46— ore a and destination opercands. the Syntax vila that of the mov inntruction . ran xchg AX, EDX xehg [rcesponsel,cl. xehg [stofat,] Dx 3 The xlot (translate) irtrcuetion cam be uned do petcforrm charcacterc dreanstotion thet late The EGX registerc munt do be Loaded with address of the dranblation dable and AL) mu an index value into che table. he nkardi + conta Pal nna co" uetion ¢ The cmp (comparce) iwetrucsio? not equal, LO MPAree £00 operta nds (equal,8. eration Inndrcvedion: THercation can be 8. Hercation Inrtrcvesion + F ion + Lowsin: implemented with Jomp insdruetion Pai 1. 4 ' mes. Code can be used to execute Zloop body 750 mov CL,5'0 ( repeats + Opp DOE dec el / 3nz repeats; efumps backto mepects if cLis not 0 [2 Logical struction: The pentium Jinndrcuedion set | prrovides dogical inbtruetions uncloding and ort, xorc (te not. The syntax anptrwetion: ig — amd destination, sourcce orc destination , gourtce xore destination, spurree Mot destination40. care amatreuedions : 2h mhe pentiom Inatrevetion ret Melodes pevertal shit ons. oo Instrevetion here : chi (SHI lesa)8) Symiod aable: na > tye » Byte ww > @ bale > tare! types Vv x OW ¢ Marck Trnes to OW O Va 5 un marck ¢ me Loe ¢ q OP The grade is ; doubleword | aa . Hsedacizexchar 5 Xo 2 we & X40 = 20 SAX 14 = 40 ao |. aaanumd4 num2 Chard name OT Answert: Example 702 DW i100 DGB 225 DB ‘welcome to c6e 197 Clanr’,‘0? Poet ttt ines Citta t dimes 20 D@ o oO offset | offserssize 04+ 2X4=2) | 2+4xd=3: “Tp Ds esent “1gpe of addressing mote + alee addressing ‘mode in the Most efficient wa 4 doda because the date are wishin the » no memorme access i6 rrequited. « and, theneso moy EAX,ERX mov desdinction, ‘Sourtce The mov netrmedion copies contents of rource to n= the contents of source are not destroyed» mov EAX, EBX mov Bx,Ccx AL,CL sing Mode: 5 addressing rnode, data are specified ar parc the. instruction Hels. AS a mesult, even though memory, ut iS Jocated in the not 'm the dato segment. mov AL,45 = In Hhs case, this mode can onls spectsy the sooree operand, The immediate dota ane alway conrtant .F © Déirtect Addressing Mode: guide. fe book: mov AL, response] +copier Y trtlo AL register > > ? 1 > Mov [response ],‘N’ 3.N is wratten trlo Htesponse MOY Lnamety,/K? ;wrude harsthe tind Charcacler of name 4 | Mov [table 11,56 35615 wrudten an she dra alex eInditcect Addiessing Mode :, MoV EPX,dabled 3 copy address oS table 1 +0 EBX mov [ERX],100 5 table [o]=100 add EBX,4 ; EBX = FQX+4 mov [EBx1,92 ; toble[4]=99 >In this address ing mode, the offset orc effective address oS the ida un one of the genercal reegistert. Fore this (e050 this addressing mode is Sometimes troforeread domes ane me giskerc indircedt addrtes ing ‘mode .an Arutay ¢ Updating values of Fxample:o1 Suppose ara end and addites $1,2,3,4.5} -wrute a code to update } element of an arcrty sing Indircect lode. Leke arraa= £ 4,2 0, 30.4>5'} Answer? Mov EQXx,4abled copy addrcess af dable 1 toEBx Mov [EGX] 10 t table 1Lo] =10 ‘ Mov EBX, 4 + EBX = EBK+4 { prov TEby] 26 : dable 114] =20 prev" EDK, 4 ee: Ex ears | Mov [EBxXI30 tdable41l2I1=30 Example :02 wrae as embly Language inetreuction do initialize an arucay Arca ={4,2,3,4 5} Fore Cr the elemernls oS this arerey, explain ¢ hich mule mews which ade rressing mode is appreopra‘ate, and why ‘ Then concte asasanguoge tnreArcuckions applying appropiato do update the rnd, Sred and 44h lotements value oS this anitay 5° thod the updete arcicay becomes ike Hthis: Arca =£1,90,33,44,5 addressing mode Answert +Ses. EMEA. % &egical t0 Physical address caleuladion and Vice venga il ice verso Location of Segments : Segmend — 16 bi (L ogical Address) and offset — 20 bit CPhysical addrtess) Fi2)KO4 = Fotos 16 bit/2 bite Converct Hexadecimal numbert: (46 bid do 20 bid) 12.4 D —>46 bit | K40F ~ 124D0h—>20bid Frample:ot Fort the memory docation whose physical address 18 specified by 41256Ah, give she addrtess IN Segment + offset orem bore segments 42568, and 1240h ans: Let ¢be cthe offselin segment 1256h y be dhe offset in Segmene 12408 tHerte, we KNOW Physical address = AI%HGAh =12560h+% segment %10f + offset jfnodnes one is, Physical address segment x toh -+offset > 195c6AR = 12400h+Y= 3266AK -12608- A Y = 1256Ah -12400h = 16Ah, 4256Ah = 4256 ? COOA =41240-046A png: Example :02 A memory Jocation ho» physical address @OFD2A -M whos segment does it have offsel BFDIA2 > we know that, Physical address = Segmemtx4oh-+ osfset Physical address = S0FD2h osfset = BEDI 50 segmerd addness = Y5o0h J Ans: sceerrTTrer