International Journal of Engineering Research ISSN:2319-6890)(online),2347-5013(print)

Volume No.4, Issue No.6, pp : 291-295 01 June 2015

Modeling and Simulation of LDMOS Device

Sunitha HD1, Keshaveni N2
1
Research Scholar, EPCET, Bangalore, 2Professor, KVG college of Engineering, Sullia
1
snmurthy74@gmail.com, 2keshaveni@gmail.com

Abstract: Laterally Diffused MOSFET (LDMOS) are widely 45% power efficiency was demonstrated in [15]. Ankarcrona
used in modern communication industry and other [16] presented the modeling of RF LMDOS transistor with
applications. LDMOS offers various advantages over the effect of substrate on the output resistance of the device.
conventional MOSFETs with little process change. In the Large signal analysis of the substrate effects on RF-SOI
present paper, an LDMOS device is modeled and simulated in LDMOS transistors was carried out by Vestling [17]. Wagner
SILVACO device simulator package using the ATHENA and [18] modeled the thermal effects in RF LDMOS transistors.
ATLAS modules. The complete fabrication process is modeled A large signal Model for RF LDMOS Transistors was given
and the device performance is simulated. The modeled device by Tamoum [19]. The graded channel and quasi saturation
gives a 46 V breakdown voltage for a device gate length of effect in power LDMOS device were presented in [20].
5µm. The device threshold voltage is 0.97V. The device Modeling and parameter extraction for LDMOS is detailed in
characteristic are also simulated and presented. [21].
Index Terms—LDMOS, SILVACO, ATHENA, ATLAS In this paper, a single-crystalline silicon based LDMOS
transistor design is presented on a ChipfilmTM substrate. The
I. INTRODUCTION device fabrication process is designed and simulated using a
process simulator. Finally the device structure generated from
Aparadigm shift from thick and rigid electronic chips to flexible
the process simulator is analyzed for its performance using a
ultra thin chips has resulted in an entire new realm of electronic
device simulator package. The fabrication process is kept
applications. 3D ICs, flexible circuits, RFIDs are a few of the
simplest and as similar to the standard CMOS device
numerous applications. The flexible circuits require
fabrication so that it is compatible and in lieu with the
mechanically rugged flexible substrates, ultra thin substrates and
standard CMOS processes.
low cost production. Handling of ultra-thin chips is a major issue
in flexible electronics circuits. The conventional methods of
backside CMP are not efficient beyond 50µm thickness. II. LDMOS BASICS
ChipfilmTM technology provides a non-conventional technique of LDMOS transistors are voltage controlled devices, hence
obtaining ultra thin substrates. Before fabrication, the unlike the bipolar devices, there is no gate current flowing the
conventional bulk silicon wafers are processed through gate. Hence the bias circuitry is very much simplified as
ChipfilmTM technology. compared to the bipolar devices. The majority of the LDMOS
Integration of organic, amorphous Silicon and poly- devices have the source connected to the backside of the
Silicon transistors on flexible substrates was presented by Bock device. Hence, the requirement of toxic BeO packages is
[1] and Troccoli [2]. Crystalline silicon transistors better suited eliminated. The bulk source can be eutectically soldered to
for efficient systems cannot be directly fabricated on flexible the package and the bond wire requirement is removed
substrates. Li et al. [3] proposed a method to transfer the pre- reducing the inductance. The LDMOS devices show better
fabricated thin film single crystal silicon transistors on flexible temperature stability than the bipolar devices. Also they
substrates. provide device stabilization preventing oscillations at higher
LDMOS is a mature technology with its long usage in the frequencies. A cross section schematic of the LDMOS is
wireless industry and has an excellent reliability record [4]. The shown in Fig. 1. The device has a sinker diffusion connecting
main driver for LDMOS is a high volume application, which the source to the backside substrate. The device consists of a
enables continuous improvement of the LDMOS technology [5], drain extension which help realize higher breakdown
[6],. The device design of LDMOS enables high voltage voltages. The drain is shielded from the gate by metal field
withstanding capability through the drift regions [7]. RESURF plate realizing extremely low feedback capacitance. The
technique presented in [8] further enhances the breakdown higher breakdown value in LDMOS is due to the Reduced
voltage level. LDMOS is projected as a technology of choice for Surface Field technology. In RESURF, one horizontal p -n
high power applications as compared to GaAs, GaN [9]. junction and a vertical p+n junction develop two diode
LDMOS process is compatible with the BCD technology [10]. structures. The vertical diode shall have a lower breakdown
A method of fabricating LDMOS device was given by Smayling voltage determined by the epitaxial doping level. The
and Torenno [11]. Mosher [12] fabricated and demonstrated a horizontal junction breakdown voltage is higher due to the
self aligned RESURF region LDMOS device. Medium voltage high ohmic substrate. At thinner layers of the epitaxial layer,
LDMOS device was fabricated by Efland [13]. Formicon [14] the depletion of the vertical junction becomes more and more
presented a LDMOS device for 32V LDMOS technology with a reinforced by the horizontal junction. Hence for the same
power performance upto 130W in 2.7-3.5GHz frequency band applied voltage, the depletion layer stretches along the
with a 36% drain efficiency. A Si LDMOS power amplifier with surface longer than expected from one-dimensional

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 International Journal of Engineering Research ISSN:2319-6890)(online),2347-5013(print)
Volume No.4, Issue No.6, pp : 291-295 01 June 2015

calculation. After a certain thickness, the reduced surface field IV. PROCESS MODELING AND SIMULATION
does not reach the critical value even at high voltages and hence
the breakdown is eliminated or raised to very high voltages.This
The LDMOS fabrication process is modeled and simulated
forms the basis of an increased breakdown voltage LDMOS
in a process simulator tool. The device structure is simulated
device.
using the process simulator and a device simulator is used for
the performance simulation. PEARSON model is used for ion
implantation process as it is most suitable for asymmetrical
implantation profiles. This function is used to obtain the
longitudinal implantation profiles. The implantation profile as
per the Pearson function is given by the differential equation:

Mesh generation is an important step in the device and

process simulation. In the present structure meshing of
Fig. 1. Basic LDMOS device structure varying densities is used. The mesh density is finer near the
junctions and also near the gate oxide. The coarse mesh is
III. LDMOS FABRICATION PROCESS used in the substrate and the bulk epitaxy. This helps in
getting accurate solutions without burdening the solver with
The LDMOS Fabrication process is presented in Table I. The
large number of computing nodes. Fig 2 shows the meshing
process starts with a conventional bulk silicon wafer. In
used for the LDMOS device under consideration.
ChipfilmTM technology 1-2µm thick wafer surface is the
substrate. An epitaxial layer is grown over this layer. The TABLE II
FABRICATION PROCESS PARAMETERS
buried p+ doping profile of the ChipfilmTM wafers is replicated
in process simulator by simulating the epitaxial layer growth Step Description
over a p+ layer. A p-epitaxial layer of thickness 2µm is grown
over the starting wafer. The epitaxial layer is p-doped with a Epitaxy deposition Boron conc = 1e14, 45 min, 900ºC temperature
boron concentration of 1×1015 cm-3. A thin layer of gate oxide Dry oxidation Duration 30 min, temperature 1000 ºC
of thickness 57.3 nm is grown using dry oxidation process. A Vt adjust implant Boron implantation, dose = 6×1011, Energy =
boron threshold voltage adjust implantation is carried out next. 20keV
Next, the poly-silicon gate is deposited and patterned. Also, the N+ diffusion for poly Phosphorous Dose = 2×1014, Energy = 100keV
region for drain extension diffusion is patterned and an n+ gate and drain
extension region
implant is carried out to dope the poly-silicon gate and to
produce a n-doped drain extension region besides the gate. The Source drain diffusion Phosphorous Dose = 3×1015, Energy = 100keV
source and drain implant regions are patterned and n+ implant is Fermi compress anneal Time = 30min, temperature = 1000ºC, N
carried out. Finally a Fermi compress anneal followed by metal
drain source contact deposition is carried out. The process
parameters are detailed in Table II.
TABLE I
LDMOS DEVICE FABRICATION PROCESS STEPS

Step Description

1 Starting material initial p-type substrate

2 p-epitaxy deposition
3 Gate oxide deposition by dry oxidation
4 Gate oxide patterning and polysilicon gate deposition
5 Poly silicon gate patterning
6 Patterning for drain extension diffusion
7 N+ diffusion for poly gate and drain extension region
8 Source and drain region patterning
9 N+ diffusion for source and drain regions
10 Fermi compress anneal
11 Contact electrode area patterning and metal deposition Fig. 2. Meshing for the LDMOS device structure

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 International Journal of Engineering Research ISSN:2319-6890)(online),2347-5013(print)
Volume No.4, Issue No.6, pp : 291-295 01 June 2015

The intrinsic device is simulated without parasitic for DC and

AC analysis. Drift-diffusion equations are solved to get the DC
characteristics and the threshold voltage is extracted.

Fig. 6 Simulated LDMOS device net doping concentration along the channel

Fig.3. Simulated LDMOS Device

Fig. 7 Simulated Total Electric field

The extracted threshold value is in tune with the value

obtained from the Id-Vgs plot. The output characteristics of
the device are also simulated. The device breakdown voltage
is simulated by sweeping the drain voltage and observing the
Fig. 4 Simulated LDMOS Device Doping Profile drain current.

V. RESULTS AND DISCUSSION

A. General Device Characteristics

The simulated device structure is shown in Fig 3. Fig.4-6

gives the plot of doping profiles in the simulated device. Fig
7 presents the electric field distribution across the device. The
electric filed is the highest near the interface between gate
oxide and silicon where the channel is formed. The extracted
oxide thickness for the dry oxidation process under
conditions given in table II is 57.3nm.

Fig. 5 Simulated LDMOS device net doping concentration B. DC Characteristics

The DC characteristics of LDMOS include the estimation

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 International Journal of Engineering Research ISSN:2319-6890)(online),2347-5013(print)
Volume No.4, Issue No.6, pp : 291-295 01 June 2015

of the threshold voltage and the input output characteristics.

The threshold voltage extracted by device simulator is 0.97V.
The Id-Vgs plot of Fig 8 also shows a similar value of the
threshold voltage.
The important characteristic of the LDMOS device is the high
breakdown voltage. The device was simulated to extract the
breakdown voltage by sweeping the drain source voltage. The
device breakdown voltage is found to be 46 V. The plot of drain
current with drain voltage swept up to breakdown is shown in
Fig 9. The drain current shoots up instantly around 46V
depicting an avalanche breakdown type phenomenon. The
electric potential distribution from drain to source in the
breakdown condition is shown in Fig 10. As seen from Fig 11,
the electric field is maximum near the drain edge where the
breakdown actually occurs and increases to a value near to the
breakdown field of Si.
Device transconductance is derived from the AC analysis and is
shown in Fig12. Fig.10. Electric Potential at Breakdown

Fig.8 Id-Vgs Plot

Fig. 11 Electric Field at breakdown

Fig.9. Simulated Breakdown Voltage Plot

Fig.12. LDMOS transconductance plot

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 International Journal of Engineering Research ISSN:2319-6890)(online),2347-5013(print)
Volume No.4, Issue No.6, pp : 291-295 01 June 2015

VI. CONCLUSION AND FUTURE WORK vi. Rjis, F. V. (2008). Status and Trends of Silicon
LDMOS base station PA technologies to go beyond 2.5GHz
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with the standard CMOS fabrication sequence. Hence, the device Technology, in: Proc. Int. ISPSD Conf. 2000, 11–18, 2000.
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