Product Specification

AU OPTRONICS CORPORATION

( V ) Preliminary Specifications
( ) Final Specifications

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Module 14.0” FHD 16:9 Color TFT-LCD
with LED Backlight design

Model Name B140HTN01.3 (H/W:0A)

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Note ( ) LED Backlight with driving circuit design

Customer
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Date
.co Approved by Date
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Jonken Fan 02/24/2014
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Checked &
Date Prepared by Date
Approved by

Lorna Wang 02/24/2014

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Note: This Specification is subject to change NBBU Marketing Division

without notice. AU Optronics corporation

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AU OPTRONICS CORPORATION

Contents
1. Handling Precautions....................................................................................... 4
2. General Description.......................................................................................... 5
2.1 General Specification......................................................................................................... 5
2.2 Optical Characteristics....................................................................................................... 6

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3. Functional Block Diagram.............................................................................. 11
4. Absolute Maximum Ratings........................................................................... 12
4.1 Absolute Ratings of TFT LCD Module ............................................................................. 12
4.2 Absolute Ratings of Environment..................................................................................... 12
5. Electrical Characteristics............................................................................... 13

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5.1 TFT LCD Module ............................................................................................................. 13
5.2 Backlight Unit................................................................................................................... 16
6. Signal Interface Characteristic ...................................................................... 17
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6.1 Pixel Format Image.......................................................................................................... 17
6.2 Integration Interface Requirement ................................................................................... 18
6.3 Interface Timing ............................................................................................................... 22
6.4 Power ON/OFF Sequence ............................................................................................... 23
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7. Panel Reliability Test...................................................................................... 26
7.1 Vibration Test ................................................................................................................... 26
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7.2 Shock Test ....................................................................................................................... 26
7.3 Reliability Test .................................................................................................................. 26
8. Mechanical Characteristics ........................................................................... 27
8.1 LCM Outline Dimension................................................................................................... 27
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9. Shipping and Package ................................................................................... 29

9.1 Shipping Label Format..................................................................................................... 29
9.2 Carton Package ............................................................................................................... 30
9.3 Shipping Package of Palletizing Sequence ..................................................................... 30
10. Appendix: EDID Description ........................................................................ 31
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AU OPTRONICS CORPORATION

Record of Revision

Version and Date Page Old description New Description Remark

0.0 2014/02/24 All First Edition for Customer

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AU OPTRONICS CORPORATION

1. Handling Precautions

1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input
connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration

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or spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on
hard surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure

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human earth when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.

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9) At the insertion or removal of the Signal Interface Connector, be sure not to rotate
nor tilt the Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for
example), do not twist nor bend the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are
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applied to the TFT Module from outside. Otherwise the TFT Module may be
damaged.
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12) Small amount of materials having no flammability grade is used in the LCD module. The
LCD module should be supplied by power complied with requirements of Limited Power
Source (IEC60950 or UL1950), or be applied exemption.
13) Disconnecting power supply before handling LCD modules, it can prevent electric shock,
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DO NOT TOUCH the electrode parts, cables, connectors and LED circuit part of TFT
module that a LED light bar build in as a light source of back light unit. It can prevent
electrostatic breakdown.
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AU OPTRONICS CORPORATION

2. General Description
B140HTN01.2 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel,
a driver circuit, and LED backlight system. The screen format is intended to support the 16:9
FHD, 1920(H) x1080(V) screen and 262k colors (RGB 6-bits data driver) with LED backlight
driving circuit. All input signals are eDP(Embedded DisplayPort) interface compatible.
B140HTN01.2 is designed for a display unit of notebook style personal computer and

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industrial machine.
2.1 General Specification
The following items are characteristics summary on the table at 25 ℃ condition:
Items Unit Specifications

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Screen Diagonal [mm] 354.69
Active Area [mm] 309.14x173.89

Pixels H x V

Pixel Pitch

Pixel Format
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1920x3(RGB) x 1080

0.161X0.161

R.G.B. Island

Display Mode Normally White

White Luminance (ILED=22mA) [cd/m2] 300 typ. (5 points average)

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(Note: ILED is LED current) 255 min. (5 points average)
Luminance Uniformity 1.25 max. (5 points)
Contrast Ratio 500 typ
Response Time [ms] 8 typ / 16 Max
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Nominal Input Voltage VDD [Volt] +3.3 typ.

Power Consumption [Watt] 4.6 max. (Include Logic and Blu power)
Weight [Grams] 295 g max.
Physical Size [mm] Min. Typ. Max.
Include bracket Length 319.9 320.4 320.9
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Width 204.6 205.1 205.6

Thickness - - 3.0 (Panel Side)
3.0 (PCBA Side)
Electrical Interface 2 Lane eDP 1.2
Glass Thickness [mm] 0.4
Surface Treatment Glare, Hardness 3H

Support Color 262K colors ( RGB 6-bit )

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AU OPTRONICS CORPORATION
Temperature Range
Operating [oC] 0 to +50
Storage (Non-Operating) [oC] -20 to +60
RoHS Compliance RoHS Compliance

2.2 Optical Characteristics

℃ (Room Temperature) :

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The optical characteristics are measured under stable conditions at 25
Item Symbol Conditions Min. Typ. Max. Unit Note
White Luminance 5 points average 2
255 300 - cd/m 1, 4, 5.
ILED=20mA
θR Horizontal (Right) 40 45 -

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degree
θL CR = 10 (Left) 40 45 -
Viewing Angle 4, 9
ψH Vertical (Upper) 10 15 -
ψL CR = 10 (Lower) 30 35 -
Luminance
Uniformity
Luminance
Uniformity
Contrast Ratio
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δ13P
CR
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13 Points
-

-
400
-

-
500
1.25

1.60
-
1, 3, 4

2, 3, 4

4, 6
Cross talk % 4 4, 7
Response Time TRT Rising + Falling - 8 16 msec 4, 8
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Rx 0.590 0.620 0.650
Red
Ry 0.320 0.350 0.380
Gx 0.290 0.320 0.350
Color / Green
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0.570 0.600 0.630

Chromaticity
Coodinates Bx CIE 1931 0.120 0.150 0.180 4
Blue
By 0.080 0.110 0.140
Wx 0.283 0.313 0.343
White
Wy 0.299 0.329 0.359
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NTSC % - 60 -

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AU OPTRONICS CORPORATION

Note 1: 5 points position (Ref: Active area)

W
W /4 W /4 W /4 W /4

H /4

1 2

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H /4

H 3

H /4

4 5

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H /4

Note 2: 13 points position (Ref: Active area)

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10
10
W /4
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W

W /4 W /4
10

1 2 3
H /4

4 5
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H /4

H 6 7 8

H /4
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9 10

H /4 11 12 13
10

Note 3: The luminance uniformity of 5 or13 points is defined by dividing the maximum luminance values by the
minimum test point luminance
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δ
Maximum Brightness of five points
W5 =
Minimum Brightness of five points

δ
Maximum Brightness of thirteen points
W13 =
Minimum Brightness of thirteen points

Note 4: Measurement method

The LCD module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change
during measuring. In order to stabilize the luminance, the measurement should be executed after lighting

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AU OPTRONICS CORPORATION

Backlight for 30 minutes in a stable, windless and dark room, and it should be measured in the center of screen.

Photo detector

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°
Field=2

50 cm

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Note 5
LCD Panel
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： Definition of Average Luminance of White (Y ):
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L
TFT-LCD Module

Measure the luminance of gray level 63 at 5 points ，Y = [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
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L

L (x) is corresponding to the luminance of the point X at Figure in Note (1).

Note 6 ： Definition of contrast ratio:

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Contrast ratio is calculated with the following formula.

Brightness on the “White” state

Contrast ratio (CR)=
Brightness on the “Black” state
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Note 7 ： Definition of Cross Talk (CT)

CT = | YB – YA | / YA × 100 (%)

Where
YA = Luminance of measured location without gray level 0 pattern (cd/m2)

YB = Luminance of measured location with gray level 0 pattern (cd/m2)

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Note 8: Definition of response time:

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The output signals of BM-7 or equivalent are measured when the input signals are changed from “Black” to
“White” (falling time) and from “White” to “Black” (rising time), respectively. The response time interval between
the 10% and 90% of amplitudes. Refer to figure as below.

100%
"White"
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"White"
Signal(Relative value)

90%
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10%
0%
Tr Tf
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Note 9. Definition of viewing angle

Viewing angle is the measurement of contrast ratio ≧10, at the screen center, over a 180° horizontal and
180° vertical range (off-normal viewing angles). The 180° viewing angle range is broken down as follows; 90°
(θ) horizontal left and right and 90° (Φ) vertical, high (up) and low (down). The measurement direction is
typically perpendicular to the display surface with the screen rotated about its center to develop the desired
measurement viewing angle.

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3. Functional Block Diagram

The following diagram shows the functional block of the 14.0 inches wide Color TFT/LCD 30 Pin

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4. Absolute Maximum Ratings
An absolute maximum rating of the module is as following:

4.1 Absolute Ratings of TFT LCD Module

Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vin -0.3 +4.0 [Volt] Note 1,2

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4.2 Absolute Ratings of Environment
Item Symbol Min Max Unit Conditions
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Operating Temperature TOP 0 +50 [ C] Note 4
Operation Humidity HOP 5 95 [%RH] Note 4
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Storage Temperature TST -20 +60 [ C] Note 4

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Storage Humidity HST 5 95 [%RH] Note 4

Note 1: At Ta (25 ℃)
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Note 2: Permanent damage to the device may occur if exceed maximum values
Note 3: LED specification refer to section 5.2
Note 4: For quality performance, please refer to AUO IIS (Incoming Inspection Standard).
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Operating Range Storage Range

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AU OPTRONICS CORPORATION

5. Electrical Characteristics
5.1 TFT LCD Module
5.1.1 Power Specification
Input power specifications are as follows;

The power specification are measured under 25 ℃ and frame frenquency under 60Hz

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Symble Parameter Min Typ Max Units Note
VDD Logic/LCD Drive 3.0 3.3 3.6 [Volt]
Voltage
PDD VDD Power - - 1.0 [Watt] Note 1
IDD IDD Current - - 303 [mA] Note 1

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IRush Inrush Current - - 2000 [mA] Note 2
VDDrp Allowable - - 100 [mV]
Logic/LCD Drive p-p
Ripple Voltage

Note 1 : Maximum Measurement Condition

Note 2
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：Black Pattern at 3.3V driving voltage. (P
Typical Measurement Condition : Mosaic Pattern

：Measure Condition
d max=V3.3 x Iblack)
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90% 3.3V

10%
0V
0.5ms

Vin rising time

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5.1.2 Signal Electrical Characteristics

Input signals shall be low or High-impedance state when VDD is off.

Signal electrical characteristics are as follows;

Display Port main link signal:

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Display port main link

Min Typ Max unit
VCM RX input DC Common Mode Voltage 0 2 V
VDiffP-P Peak-to-peak Voltage at a receiving Device 120 mV
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Fallow as VESA display port standard V1.1a

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Display Port AUX_CH signal:

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Display port AUX_CH
Min Typ Max unit
VCM AUX DC Common Mode Voltage 0 2 V
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AUX Peak-to-peak Voltage at a receiving Device

Fallow as VESA display port standard V1.1a.

d 0.32 1.36 V

Display Port VHPD signal:

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Display port VHPD
Min Typ Max unit
VHPD HPD Voltage -- -- 3.6 V

Fallow as VESA display port standard V1.1a.

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5.2 Backlight Unit

5.2.1 LED characteristics

Symbol

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Parameter Min Typ Max Units Condition
Backlight Power PLED - - 3.6
℃
[Watt] (Ta=25 ), Note 1
Consumption Vin =12V

LED Life-Time N/A 15,000 - - Hour (Ta=25 ℃), Note 2

IF=20 mA

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Note 1: Calculator value for reference PLED = VF (Normal Distribution) * IF (Normal Distribution) / Efficiency
Note 2: The LED life-time define as the estimated time to 50% degradation of initial luminous.

5.2.2 Backlight input signal characteristics

Parameter
LED Power Supply
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Symbol
VLED
Min
7.0
Typ
12.0
Max
21.0
Units
[Volt]
Remark

LED Enable Input 2.5 - 5.5 [Volt]

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High Level
VLED_EN
LED Enable Input - - 0.5 [Volt]
Low Level Define as
PWM Logic Input 2.5 - 5.5 [Volt] Connector
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High Level
VPWM_EN Interface
PWM Logic Input
Low Level
- - 0.5 [Volt] (Ta=25 ℃)
PWM Input Frequency FPWM 200 1K 2K Hz

PWM Duty Ratio %

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Duty 5 -- 100
*Note 2
Note 1 : Recommend system pull up/down resistor no bigger than 10kohm
Note 2 : If the PWM duty ratio(min) is set between 5% to 1% ，the PWM input frequency should be set below 1KHz . The
brightness-duty characteristic might not be able to keep in it’s linearity if the dimming control is operated in 1% to
5% range

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6. Signal Interface Characteristic

6.1 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.

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6.2 Integration Interface Requirement

6.2.1 Connector Description

Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following

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components.

Connector Name / Designation For Signal Connector

Manufacturer IPEX or compatible
Type / Part Number I-PEX JP CO.,LTD;20455-040E-12

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Mating Housing/Part Number IPEX or compatible
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6.2.2 Pin Assignment (2 Lane)

eDP lane is a differential signal technology for LCD interface and high speed data transfer device.
PIN NO Symbol Function

1 NC No Connect (Reserved for DCR)

2 H_GND High Speed Ground

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3 Lane1_N Comp Signal Link Lane 1

4 Lane1_P True Signal Link Lane 1

5 H_GND High Speed Ground

6 Lane0_N Comp Signal Link Lane 0

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7 Lane0_P True Signal Link Lane 0

8 H_GND High Speed Ground

10

11
AUX_CH_P

AUX_CH_N

H_GND
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True Signal Auxiliary Ch.

Comp Signal Auxiliary Ch.

High Speed Ground

12 LCD_VCC LCD logic and driver power

13 LCD_VCC LCD logic and driver power

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14 LCD_Self_Test or NC LCD Panel Self Test Enable (Optional)

15 LCD_GND LCD logic and driver ground

16 LCD_GND LCD logic and driver ground

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17 HPD HPD signal pin

18 BL_GND Backlight ground

19 BL_GND Backlight ground

20 BL_GND Backlight ground

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21 BL_GND Backlight ground

22 BL_Enable Backlight On / Off

23 BL_PWM_DIM System PWM signal Input

24 NC No connect (Reverse for AUO TEST only)

25 NC No connect (Reverse for AUO TEST only)

26 BL_PWR Backlight power (6V~21V)

27 BL_PWR Backlight power (6V~21V)

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28 BL_PWR Backlight power (6V~21V)

29 BL_PWR Backlight power (6V~21V)

30 NC No Connect (Reserved for CM)

31 NC No Connect (Reserved for TP)

32 NC No Connect (Reserved for TP)

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33 GND Ground–Shield

34 VTSP No Connect (Reserved for TP)

35 VTSP No Connect (Reserved for TP)

36 NC/TP_EN No Connect (Reserved for TP)

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37 TP_CLK No Connect (Reserved for TP)

38 TP_Data No Connect (Reserved for TP)

39

40
INT

RST
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No Connect (Reserved for TP)

No Connect (Reserved for TP)

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Connector

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Pin 30 Pin 1

Note1: Start from right side.

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Note2: Input signals shall be low or High-impedance state when VDD is off.
Internal circuit of eDP inputs are as following.
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3. Lane1-
4. Lane1+

6. Lane0-
7.Lane0+
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6.3 Interface Timing

6.3.1 Timing Characteristics
Basically, interface timings should match the 1920x1080 /60Hz manufacturing guide line timing.

Parameter Symbol Min. Typ. Max. Unit

Frame Rate - - 60 - Hz

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Clock frequency 1/ TClock 69.4 70.5 75 MHz

Period TV 1112 1120 1152

Vertical
Active TVD 1080 TLine
Section
Blanking TVB 32 38 72

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Period TH 1040 1050 1084
Horizontal
Active THD 960 TClock
Section
Blanking THB 80 90 124

Note 1 : The above is as optimized setting .co

Note 2 : The maximum clock frequency = (1920+B)*(1080+A)*60 < 75MHz
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6.4 Power ON/OFF Sequence

Display Port panel power sequence:

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Display Port AUX_CH transaction only:
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Display Port panel power sequence timing parameter:

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Note1: The sink must include the ability to generate black video autonomously. The sink must automatically enable black video
under the following conditions:
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-upon LCDVDD power on (with in T2 max)-when the "Novideostream_Flag" (VB-ID Bit 3) is received from the source (at the end
of T9).
-when no main link data, or invalid video data, is received from the source. Black video must be displayed within 64ms (typ)
from the start of either condition. Video data can be deemed invalid based on MSA and timing information, for example.

Note 2: The sink may implement the ability to disable the black video function, as described in Note 1, above, for system
development and debugging purpose.
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Note 3: The sink must support AUX_CH polling by the source immediately following LCDVDD power on without causing damage
to the sink device (the source can re-try if the sink is not ready). The sink must be able to respond to an AUX_CH transaction with
the time specified within T3 max.

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Display Port panel B/L power sequence timing parameter:

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7. Panel Reliability Test

7.1 Vibration Test

Test Spec:

Test method: Non-Operation

Acceleration: 1.5 G

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Frequency: 10 - 500Hz Random

Sweep: 30 Minutes each Axis (X, Y, Z)

7.2 Shock Test

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Test Spec:

Test method: Non-Operation

Acceleration: 220 G , Half sine wave

Active time: 2 ms

Pulse:

7.3 Reliability Test

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X,Y,Z .one time for each side

Items Required Condition Note

Temperature
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℃, 90%RH, 300h
Ta= 40℃
Humidity Bias
High Temperature
℃, Dry, 300h
Ta= 50℃
Operation
Low Temperature
℃, 300h
Ta= 0℃
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Operation
High Temperature
℃, 35%RH, 300h
Ta= 60℃
Storage
Low Temperature
℃, 50%RH, 250h
Ta= -20℃
Storage
Thermal Shock
℃to 60℃
Ta=-20℃ ℃, Duration at 30 min, 100 cycles
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Test
Contact : ±8 KV Note 1
ESD
Air : ±15 KV

Note1: According to EN 61000-4-2 , ESD class B: Some performance degradation allowed. Self-recoverable.
No data lost, No hardware failures.
Remark: MTBF (Excluding the LED): 30,000 hours with a confidence level 90%

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8. Mechanical Characteristics
8.1 LCM Outline Dimension

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請勿觸碰
Don't Touch! 請勿觸碰
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Don't Touch!

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Note: Prevention IC damage, IC positions not allowed any overlap over these areas.

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. Shipping and Package

9.1 Shipping Label Format

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9.2 Carton Package

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9.3 Shipping Package of Palletizing Sequence
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10. Appendix: EDID Description

Address FUNCTION Value Value Value Note
HEX HEX BIN DEC
00 Header 00 00000000 0
01 FF 11111111 255
02 FF 11111111 255
03 FF 11111111 255

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04 FF 11111111 255
05 FF 11111111 255
06 FF 11111111 255
07 00 00000000 0
08 EISA Manuf. Code LSB 06 00000110 6
09 Compressed ASCII AF 10101111 175

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0A Product Code 3D 00111101 61
0B hex, LSB first 10 00010000 16
0C 32-bit ser # 00 00000000 0
0D
0E
0F
10
11
d
Week of manufacture
Year of manufacture
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00
00
00
17
00000000
00000000
00000000
00000000
00010111
0
0
0
0
23
12 EDID Structure Ver. 01 00000001 1
13 EDID revision # 04 00000100 4
Video input def.
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14 (digital I/P, non-TMDS, CRGB) 95 10010101 149
15 Max H image size (rounded to cm) 1F 00011111 31
16 Max V image size (rounded to cm) 11 00010001 17
17 Display Gamma (=(gamma*100)-100) 78 01111000 120
18 Feature support (no DPMS, Active OFF, RGB, tmg Blk#1) 02 00000010 2
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19 Red/green low bits (Lower 2:2:2:2 bits) 9F 10011111 159

1A Blue/white low bits (Lower 2:2:2:2 bits) E5 11100101 229
1B Red x (Upper 8 bits) 96 10010110 150
1C Red y/ highER 8 bits 58 01011000 88
1D Green x 53 01010011 83
1E Green y 8A 10001010 138
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1F Blue x 26 00100110 38
20 Blue y 24 00100100 36
21 White x 50 01010000 80
22 White y 54 01010100 84
23 Established timing 1 00 00000000 0
24 Established timing 2 00 00000000 0
25 Established timing 3 00 00000000 0
26 Standard timing #1 01 00000001 1
27 01 00000001 1
28 Standard timing #2 01 00000001 1
29 01 00000001 1
2A Standard timing #3 01 00000001 1
2B 01 00000001 1

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2C Standard timing #4 01 00000001 1
2D 01 00000001 1
2E Standard timing #5 01 00000001 1
2F 01 00000001 1
30 Standard timing #6 01 00000001 1
31 01 00000001 1
32 Standard timing #7 01 00000001 1
33 01 00000001 1

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34 Standard timing #8 01 00000001 1
35 01 00000001 1
36 Pixel Clock/10000 LSB 14 00010100 20
37 Pixel Clock/10000 USB 37 00110111 55
38 Horz active Lower 8bits 80 10000000 128

m
39 Horz blanking Lower 8bits B4 10110100 180
3A HorzAct:HorzBlnk Upper 4:4 bits 70 01110000 112
3B Vertical Active Lower 8bits 38 00111000 56
Vertical Blanking Lower 8bits
3C
3D
3E
3F
40
Vert Act : Vertical Blanking
HorzSync. Offset
HorzSync.Width
VertSync.Offset : VertSync.Width
d
Horz&Vert Sync Offset/Width Upper 2bits
.co
(upper 4:4 bit)
26
40
30
64
31
00100110
01000000
00110000
01100100
00110001
38
64
48
100
49
41 00 00000000 0
42 Horizontal Image Size Lower 8bits 35 00110101 53
43 Vertical Image Size Lower 8bits AD 10101101 173
slc
44 Horizontal & Vertical Image Size (upper 4:4 bits) 10 00010000 16
45 Horizontal Border (zero for internal LCD) 00 00000000 0
46 Vertical Border (zero for internal LCD) 00 00000000 0
47 Signal (non-intr, norm, no stero, sep sync, neg pol) 18 00011000 24
w.y

48 Pixel Clock/10,000 (LSB) B8 10111000 184

49 Pixel Clock/10,000 (MSB) 24 00100100 36 40Hz frame rate
4A Horizontal Addressable Pixels, lower 8 bits 80 10000000 128
4B Horizontal Blanking Pixels, lower 8 bits B4 10110100 180
4C H Pixels, upper nibble : H Blanking, upper nibble 70 01110000 112
4D Vertical Addressable Lines, lower 8 bits 38 00111000 56
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4E Vertical Blanking Lines, lower 8 bits 26 00100110 38

4F V lines, upper nibble : V blanking, upper nibble 40 01000000 64
50 Horizontal Front Porch, lower 8 bits 30 00110000 48
51 Horizontal Sync Pulse, lower 8 bits 64 01100100 100
V Front Porch, lower nibble : V Sync Pulse, lower
52 nibble 31 00110001 49
53 VFP, 2 bits: VSP 2 bits: HFP 2 bits: HFP 2 bits 00 00000000 0
54 Horizontal Image Size in mm, lower 8 bits 35 00110101 53
55 Vertical Image Size in mm, lower 8 bits AD 10101101 173
H Image Size, upper nibble : V Image Size, upper
56 nibble 10 00010000 16
57 Horizontal Border 00 00000000 0
58 Vertical Border 00 00000000 0
59 Bit Encode Sync Information 18 00011000 24

B140HTN01.3 Document Version : 0.0 Page 32 of 33

 Product Specification
AU OPTRONICS CORPORATION
5A DC 00 00000000 0
5B HTOTAL 00 00000000 0
5C HA 00 00000000 0
5D HBL 00 00000000 0
5E HFP 00 00000000 0
5F HFPe 00 00000000 0
60 HBP 00 00000000 0
61 HB 00 00000000 0

.tw
62 HSO 00 00000000 0 nVDPS
HS Reserved 00
63 00 00000000 0
64 VTOTAL 00 00000000 0
65 VA 00 00000000 0
66 VBL 00 00000000 0

m
67 VFP 00 00000000 0
68 VBP 00 00000000 0
69 VB 00 00000000 0
VSO
6A
6B
6C
6D
6E
VS
Detail Timing Description #4
Flag
Reserved
.co
For Brightness Table and Power Consumption
d 00
00
00
00
00
00000000
00000000
00000000
00000000
00000000
0
0
0
0
0
6F 02 00000010 2
70 Flag 00 00000000 0 Header
71 PWM % [7:0] @ Step 0 0C 00001100 12
slc
72 PWM % [7:0] @ Step 5 21 00100001 33
73 PWM % [7:0] @ Step 10 FF 11111111 255
74 Nits [7:0] @ Step 0 16 00010110 22
75 Nits [7:0] @ Step 5 3C 00111100 60
w.y

76 Nits [7:0] @ Step 10 D0 11010000 208 Brightness Table

77 Panel Electronics Power @ 32x32 Chess Pattern = 11 00010001 17
78 Backlight Power @ 60 nits = 0B 00001011 11
79 Backlight Power @ Step 10 = 24 00100100 36
7A Nits @ 100% PWM Duty = D0 11010000 208 Power Consumption
7B Flag 20 00100000 32
ww

7C Flag 20 00100000 32
7D Flag 20 00100000 32
7E Extension Flag 00 00000000 0
7F Checksum 53 01010011 83

B140HTN01.3 Document Version : 0.0 Page 33 of 33