See PERIMENT NO. 1(4 onject: To verify the truth tables of basic and uni iversal logic Bates R & NAND) and verification NO) of De Morgan’s theorems, (OR, AND, Nor Apparatus required: 1. For logic Gates: Logic gate experiment kit, | aallners ‘ . leads wi 3. For De Morgan’s law: - Experiment kit, conne i wit DC power supply. 7 DC power si supply Theory: TLOGIC GATES 1 Ge gate is an elementary building block of a digit | i digital circui lap ce ae at Sans Tow (0) or high (0), fepeseted by diferent vot iin am of he 90 Ban conetal ean, and generally does, change often, as the cisule proceiss'Gahs ae ore cima, the low state is approximately zero volts (0 V), while the high se arn © gates Mts positive (#5 V). There are seven fundamentalfbas ih Sti print Fee a ONO ic logic gates: AND, OR, XOR. Boolean equations: =A +B (OR gate) ‘A.B (AND gate ) (A + BY (NOR gate) (A. BY (NAND gate) ‘A or B (NOT gate ) Circuit diagram: ad) Q) @yY a Y= (6) Y= Where A and B are inputs and Y is output.The right side of the second theorem im lies OR gate (see in figure). This combination fon Again the triangles are deleted and the bubbl remind us of the inversion that takes Place bef bubbled OR gate (see symbol as given figure)” AN Instructions: |. Connections should be made tight and carefully, 2. Only D.C. voltages are to be used, . Voltage should be applied within specified limit Write output 1 when indicator is ON and 0 when indi Take reading under instrument range. rocedure: . LOGIC GATES: ) For AND gate operation: - To operate AND gate ND gate input switches as shown in fig. Connect th dicator glows, then write “ON” in desired column OFF”. he inputs are i S are iny i n is used s e figure) of has come into use. 80 offen that the les moved dij Ted Ding. From icator is OFF. befo abbreviated «,, rectly to the inputs, The: NOW on, we Feaching an YMbOI (see in Se bubbles Will call the » connect logic input switches with the € output of AND gate to the logic of the observation table, otherwise Seri Inputs Indicato1 serial number a os A B ON/OFF Outpat 1 0 0 ore ° 2 0 1 ore ° 2s 1 0 Ore oO 4 1 1 on iL te:- Write output 1 when indicator is ON and output 0 when indicator is OFF. For OR gate operation: To operate OR gate, connect logic input switches to the OR gate ut as shown in fig., connect the output of the OR gate to the logic indicator. use per . Inputs Indicator rial number a 5 ON/OFF Output 1 0 0 OFF 2 2 0 1 on 1 3 1 0 on 4 4 1 1 ON z e: Write output | when indicator is ON and ‘output 0 For NOR gate operation: To-opérate NOR gate, ¢ R gate input shown in fig. connect the output th cator. e output of NOR when indicator is OFF sonnect logic input switches with the gate to the logic ial number Inputs Indicator Output ctive from November -2022 Page No.‘ON/OFF. L A B 7 s + of ©° 3 4 1 ore ject logic input SW" ator. (4) For NAND gate operation: To operate NAND gate, NAND gate to the logic ind the NAND gate inputs shown in fig., connect the output of . it Indicator Outpu' Serial number =e ON/OFF x 1 0 0 oN en 2 0 1 4 L 3 1 0 2 + 1 1 Zoe © logic input (5) For NOT gate operation: To operating NOT gate connect any one of the two aa switched with the NOT gate input as shown in fig., connect the output 1 8 logic indicator, Input Indicator ON / OFF Output 0 On 1 1 Of 0 2. De Morgans Theorems: @ Addition operation in Boolean al; sebra is equivalent to the or in the logic circuits and multi ition in the Boolean is same as AND and inversion is equivalent to not operation in the logie circuit, a. First theorem A B re r A+B o ea rn 7 + 2 = oe eres be 1 1 oO oO o. Second theorem AtB Ola] Graph: n 10and corresponding truth |. LOGIC GATES:cOn comparison of output of observation PIE AYE LTE” operation is table for ..O8S..).... GATE operation, the [N% experimentally verified. 2. De Morgan’s Theorems: The results in truth tables verify laws 1 and 2. _— eg a ee List of taken precautions: Questions: 1) What is a logic gate? | 2A Logec ott San , dul tock of aiyide Soak. “d “d 2) Define number system and truth table. 7 ee Bath fable io a tebe thot gaves cubpeh i OL pesiilote —conmbinadkion, of ihpat te a lori circuit}. Number Sagiim : TH humbex asa i) ae ae bro debrtrine fe bow a avg 7 3) What do you mean by positive logic and negative togic? Sys my Such at duiival at > es CAG Hie higher dy toe viloge supa ay. om wer Vell oly Ts pestikve gah. ‘t Sports (8! Thom te |onge ach meptvelgic’ tb be Lower wllnge sepa “Shae be organ” ak and stcond harem.’ ©” Thy “de che wh 4? : aft negahtyy Do Duwergens [ost the owns: dts tack nt q guhive. mh fn 7 : to AY trbbud Goh. be = Ah AND gett is 2quive ea sare Theestm? th og Te -B Sine AND, off Sad NOT anes de cal DS kc es? act. TH NOR Gok Is ALD PND 6 . inte tan TER OR Met atl bee gale beau « Ths fontner rene Te Have gah ck ee Gah Sey. Ate Ledlp eb bony J ee . 6) Why NOR and NAND fates ar aled 8S universal gate freed ui 7 Effective from November -2022 Page No.' , ) ) ) y y , 7 Nor @ind nan gate ov called a9 tnvivial gates be come fre. honey Me papey tne ua Indiv day Cau ye Uae bo Han dwane, 7) What is the importance of the study of the logic gates? WD tegie gos peshowms basic Lgiel funtion ond OM . fund dined 7) blouls of 7 “ye Gyo Gi Lege gehs om Y used to Carey ie epesehion st ond te ox id ay epededs Se om” Sin reset La, we Une bineny tp need betwee! anatog and dpi ‘waveform OPicaitsinstriameants. JS OM ( < Farame foe frosted Oru + Digi Got Dfinehor > - thokte tout whieh [TR eieatt och prea ool aw hes abili Ww only spel Puy “a dito 7 Inpat apel> “The input grant ty Ky M\ He anels co a ete Arbok Crest is Conbretus fire Sana Adis euch fine oot pot fel ot ee Sad : a in 4 she ro! Dea aly one aN Ja} an uy Spr.EXPERIMENT NO. 1(B) Object: To study the properties of universal gate and construct the following Gate:~ 1, AND gate, OR gate, NOT gate, and NOR gate using NAND gates. 2. AND gate, OR gate, NOT gate, and NAND gate using NOR gates Apparatus Requirements: Logie Gate Kit, Connecting wires, ‘Theory: For every Boolean expression the logic ci cean be built. Conversely for every logic cireuit, one can write a Boolean expression. To built logic circuit, OR gate is used for ‘addition sign, AND gate is used for multiplication sign and NOT gate is used for inverse ic gates for particular logic functions are Jined by suitable combinations of these gates. NAND 1g blocks. given, other logic functions can be gate & NOR gate can be used to build AND, OR, & NOT gate, the basie Hence NAND & NOR gate are called universal building blocks of logie gates. Procedure:- Connect the circuit as show in diagram through patch cords. Al & BI inputs of “AND” gate to logic input ‘0° & ‘0° as shown in truth table for *AND' gate. Also connect output of “AND” gate to output indicator. ‘Switch ON the instrument using ON/OFF toggle switch provided on the front panel Cheek the output indi i {fit does not glow the indicator is thatthe output isin state"0”. Similarly verify the output for other combinations if ‘AI’ & “BI” as shown in the ‘truth table. _"AND" GATE z = Bz NAND AS AND GATE Effective from November -2022 Page No. IResult:-. AJ. cxifaed AcesOy». e Soe SPAT 4 ta get \v Preeautions:=.Q.1.f.Lo nbn Shebd be figld cowd rigid. Acoands te anen rags : Ui) Peading shoud be faten Com fully. Gi Conn pererts shoatd be tected Lefer Gomplelt of teeperines ch, JIS IISIIII Questions Fe 1. What is eet ie 2. 4 Univers of) qee isa ack whth Can ‘perms of nd Robes funds on usitreut pad fe une on other ah bare 2. Why NAND & NOR are called universal gate? a ee ord Nor an Codd Unviver tol Jobe becoun Meg BONS prtpedy that diay individush Cont be cad fre . 3 a anak oe Ne hp tet “7d a Carer}. > a qt a tre eedvicel Greif Wit on PL CPT od be om mow impel. Te sulahold 4. Whatisoutstabie NPAT ON spa cebob ts bow d ing trey DT teeth fhe ta Leger ie tence pod Os )/, (io mpt ly) tre 1a deh ah ot Und te fell helena a 4 Povsinte Anputs qi a “ih He nec Repro otf festive from Névember 2022 Grit nd tye Paseo ee oxtuh. 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The input resistance 's independent of drain voltage above ‘PINC acon biased pun (gate of source) junction therefore is very high ‘Transfer characteristic is similar to that of a vacuum triode. List of taken precautions: , pptiticd (tke tee serminels of we FET smose we covepetly 0 @ sovce ond gate ghovsd be shoxt circuited: @ Tae — veoding property under ansexvmone org’ ied CO Vobtoye exceeding He OY ok he FET shutd not be off Questions: - 1, What isa transistor? semiconsucter dence thee can be used corrent ox vellage- A > A bronsistor dso tye #4 ebectrle sister 1 a conduc ond ansvdote z ch ond on amplifier, BO” 0 beth , bronsistey posically old OO S01 qrinnerr device ehOl je used bo contvod ov regisote 8% plow of erectronie signa’ ei What isan est grensistor GED ko tye F dronsister that VSS wk oe “peed to conte the blow of cursont th O semiconductey: pets oe ie broom 03 unlpedee dsonsistoys sine EY invelve shgle 2” type operation + rae is eqs use -elthey dlectoas oF hedes os Chore Mr s0 Wee ee ets of FET? nase Pes ve phe bernined though conch the majority Aege Ogee patees gre entered dn we PET: A) peoin + dvain is the fesminod thxough which ta mayenty charge cossiess exist Fret te PET: _ -2022 Page No{“ 4 ay ember.GD Gote : The gates — erminal is Farmed by thisin of on Mote semicondvetey with a — Préype. semicenducder - 4. Why FET is preferred over transistors? 2 © FETS Hip ih inpre —Impedemee. thon tromeisters 40 eg Or preferrakly ued 05 the yor stope to muleistage amphifier: @ They generate tower noise than trondsoy - 5. FET is UJT or BJT? Explain? > FET js UtT, sce they Invelve reve Ure either Alectrens Q-chamel) sgle comer tye ope vation bey eae Ge homed) os charge rs canier In thelr operators. Sudha ideepate = 62/12/29 EXPERIMENT NO. 6 Object: To study output and transfer characteris i fer characteristi ; Transistor (MOSFET) and to identify thery ie peed ors Men Oxide ‘on Field Effect Apparatus required: Trainer kit, connecting wires, power supply. Theory T Peel a Silicon Field Effect Transistor (MOSFET) is a device with eat chee a as input impedance greater than most vacuum tubes, a simple eae cheaper to fabricate than a junction transistor, essentially infinite current ane ely small size. Various designations of this device include IGEFTT (insulated gate jeld effect transistor), etc. Its extreme high input impedance has opened new vistas for electronic circuits, particularly in ultra-sensitive electronic instruments, timing monitoring and various types of logic circuitry. The MOSFET uses a metal gate electrode, which is separated from the channel by the insulating properties of thin layer of glassy silicon dioxide. Figure, as given below shows the theoretical basic structure and the modem planar version of a MOSFET. Like the p-n junction, this insulated gate electrode can deplete an adjacent channel of its active carriers when suitable bias voltages are applied. In contrast with the junction gate operation, however, the conductivity of the depletion type MOS transistor channel can be substantially increased simply by reversing the polarity of the gate voltage. As a result of this unique characteristic, the input resistance remains high regardless of the signal voltage polarity. In additions the typical leakage currents associated with silicon Gioxide insulator are relatively insensitive to temperature change and are many times small in magnitude than silicon junction leakage currents. There are two modes of operation for MOSFETS; enhancement mode and depletion mode. The drain is biased positive with respect to the source. When the gate is shorted to the source, that is V,.= 0, current flows through the channel, bulk resistance being the only limiting factor. As the in eunrent increases the voltage drop across the bulk of the channel makes the gate to channel ,d near the ‘drain and a stage is reached when further increase in drain to eared by the increase in channel resistance due to depletion of carriers re change in drain current. Then the channel is said to have been resin voltage at which the drain current does not increase further, is getting more deplete: source voltage is compe! resulting in no apprecial pinched-off. The source called pinch-off voltage. i the channel of the carrier thus reducing the drain A negative, ge bias aay alied electric field adds on tothe one produced by courant. Wik ee hannel is pinched off at a small drain currents. It is observed that the drain current and the chant because ofthe field developed Ps the channel resistive drop. channel width is less ae ae oes ve all the current to flow between drain and source with Sufficient negative bias 1M "Electrons are attracted 10 the underside of the gate and thus positive bias applied to the Suiting in increased drain current eovrsnel conductivity is increasedObservation Table-1: Output characteristic curve fe Ves (volt) = dak..Volts | Vos (volt) =...1.. Volts | Ves (volt) =“... Volts | sa Vos Wolt) | Tp (mA) | Vns(wolt) | Io (mA) | Vos (volt) | Tp (mA) 1 Os Od os O-4 OS oy 2. lo Be be o8 to 0-4 3, vse «4 ee ue Ls v3 2 20 0-7 20 1-2 20 Le . Qs oF as b 9. 2-2 6. xo oF +o 6? Zo Ve i 35 OF ae 2 as 24 Z tee at oO © Keo 24 9. 4 et sr a ioe ae a thd oy iid 62 Oe 24‘Fable:2- Transfer characteristic curve [ SNe | Voswoltp=..10... Volts Vas footy = LE Vols | [- Yes oly [To mA) Wess(voity | ToGmy K 9-4 oO | 24° 02 2 r 340 ol oe ol ar on | atl o8 ot) ees) on" | aq | et Pos | ot [ao fre | [or oe fea | Pag | ee [as | eta peop pee ee [pes fo He. 3-3 20. \y a8 By) Geaphs:. ‘istic: betweem Vps and Ip keeping Vas constant. Cyetpast characteristic: ‘Yransfer chavacteristic: Pioe draiw current Ip against Vas ow separate: gsapth paper.Results: As pes the guyh, sdvdiet weveal thae it is o Wechowed MosteT List of taken precautions: O Make — connections Cove fulty OThe twee teminals of. MOSFET mise be casey sdortied, O Take weodings under instroment vonge. Questions: 1. What is a MOSFET? Az MOSFET ds o valtege - controtled device whese sutput depends on tHe gate voltage. The metal oxide gate Is electricoldy desolate, fom the chanel sing a ttn tayer of giilcon dioxide. Which aneceoses les input — impendence. sigh Fleantdy, 2, "What is the difference between FET and MOSFET? ! Ac A MesreT is 0 sobidegs of FETA FET. 0 Pleld offect transistor, THS con fe a MOSFET, TFET 0x any one of rumerus otters FET wows on poncipte of gate terminal chaughy wesiipauce pefweer? er tertinds.37 MOSFET MOS deleribet the gate, “anfporayfon . Te two othe n Me steetater on contd hrok Eind Sof MOSFER? © "AMS 2 ter OF sermrcondodter, oS? . ' Bs Ww A= The fierce temjnat of MOSFET are Gere (2 dson (0) ond Source G), 4. How does current conduction take place in a MOSFET? Az lomert — tendvetton dn MESFET bewrs de to formotton of a Mph density ntype/ chamel In te p tye body region due do elecéfic field Prdveed by the ate sovsce vellt - Page No. (i) Effective from November -2022