1 BITSILICA FPGA Design
Services:
RTL implementation leveraging expertise in Design languages
including VHDL, Verilog, and SystemVerilog.
Custom IP development and Interfacing the IP cores
Xilinx SDK embedded application development on microprocessors:
Zynq-7000 SoCs and Zynq UltraScale+ MPSoC.
System debugging support in MicroBlaze cores, Zynq-7000 SoCs
and Zynq UltraScale+ MPSoC.
High speed interface development support in AXI, AXI-4 and10G
Ethernet PHY.
Support in Specification development, Architecture Design and
Selection of IP cores.
Design Data and interface control modules, Data processing
algorithms and custom module development.
Development for FPGA and MPSoC/RFSoC.
Memory management support for MPSoC.
Real-Time FPGA Application Support.
FPGA optimization of Existing solutions.
2 Silicon Labs Careers Strong foundational knowledge of digital circuit design
concepts, simulation, and verification techniques
Competence in RTL coding & VLSI
Microprocessor architecture and implementation
Low-power digital circuit design techniques
High-speed, high-performance digital circuit design
techniques
Logic synthesis, RTL check and timing analysis
Competence in behavioral modeling (e.g. Verilog,
SystemVerilog), high-level languages (e.g., C, C++, Matlab) and
scripting languages (e.g Python)
Wireless protocols and MAC implementation.
SOC peripherals exposure.
3 Technical Skills:
Proficient in RTL: VHDL/Verilog/System Verilog
Conceptual understanding of Digital Systems
Understanding of FPGA design flow and tools
Knowledge of High-Speed Serial IO and Video IPs
Basic communication protocols: JTAG, I2C, UART, SPI,
etc.
Understanding of C/C++ language basics
FPGA Architecture knowledge
4 ViteStork
Consulting Pvt. Ltd.
Job Description
Responsibilities: Excellent Leading & communication
skills and demonstrate the desire to take on diverse
Parameswari Towers, challenges. Experienced with large FPGA
Plot No: 95,
development flow and tools on Xilinx devices.
Flat No: 301, 3rd
Floor, Motinagar, Experience in wireless communication Proficient in
Hyderabad - 500018 Verilog RTL language. Experienced with large FPGA
Landline: 040 - development on Xilinx devices. Very familiar with
35527266 Xilinx's build flow including design entry in Verilog,
Mobile: 9573385581
| 8341144633 synthesis, place and route, timing constraints and timing
Email: closure. Hands on with lab FPGA debug
info@vitestork.com methodologies. Hands on experience with lab debug
equipment, such as oscilloscopes and logic analysers.
Experience with verification methodologies, RTL and
gate level simulations and debug. Experience
debugging silicon and PCB issues. Run basic
verification tests (on simulations) Minimum
Qualifications: BSc/ MSc in Electr
5
6
7
8
Aliza
McCullough
9690 Anastacio Lock
HoustonTX
Phone
+1 (555) 881 6311
EXPERIENCE
Boston, MA
HEANEY-RYAN
Performance analysis and tuning of workloads on heterogeneous platform
Perform RTL coding
Communicate and work with team members across multiple disciplines
Work with Partners/Supplier to optimize and customize their products
Develop detailed design specifications
Developing UPI RTL code using Verilog for UP link/protocol layers
Designing and developing RTL code using VHDL or Verilog to accelerator kernels for linear algebra, graphical
models, combinatorial logic, machine learning etc
Chicago, IL
BERNHARD INC
Assist in shaping the micro-architecture of the chip
Power management with multiple power domains
High-speed data path and control units
Pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis, and full-chip
simulation plus debug
Strong background in computer architecture including one or more of the following
Integer and floating point numeric units
Demonstrated track record of bringing logic designs into high volume production
Boston, MA
ROOB-KUHIC
present
Work with micro architect to develop specifications for devices
Work with DV team to develop test cases and debug
Interface to IP cores provided by vendors
Work with the physical design teams in aiding the implementation of the functional blocks
Guide the physical design teams in aiding the implementation of the functional blocks
Usage of EDA tools, including simulators (NCVerilog, Modelsim), synthesis tools (DC), timing (primetime-SI)
Familiar with Altera FPGA placement and fitting techniques
EDUCATION
Bachelor’s Degree in Electrical Engineering
INDIANA UNIVERSITY
SKILLS
Self driven individual and a good team player
Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision
Inherent sense of urgency and accountability
Ability to multi-task in a dynamic, fast-paced environment
Excellent verbal and written communication skills
Ability to interface internally and externally with all levels of the organization
MS in Engineering with 3+ years of experience, or BS in Engineering with 5+ years of experience in RTL design
of submicron SOC products (eg: Microprocessor based SOC’s)
Haven Feest
85711 Golden Shoal Detroit MI Phone +1 (555) 398 4177
EXPERIENCE
Detroit, MI
MUELLER AND SONS
6) Flexible in working hours to accommodate working with co-workers in different time-zones
Working with architects and designers to develop technical specifications
Analyse results and provide recommendations to Product Engineering teams in order to improve product quality
or to meet design intent
Execute the verification test plan by developing checkers, stimulus and coverage using System Verilog and/or C+
+ and running simulations
Team and personal development – You take time to drive your own development, whilst also encouraging team
members and partners to do the same
Efficiently execute test plans on multiple platforms, measure progress and metrics, and work with cross-
functional teams to achieve these results
Work closely with architecture and RTL designers to develop comprehensive verification plan based on IP core
standard specification
Boston, MA
WILLIAMSON AND SONS
Execute formal and functional verification, synthesisand static timing analysis
Execute power aware verification
Verification plan development, RTL/gate simulations to meet project target in both quality and schedule
Create and maintain verification plans
Proficient in English: speaking, reading and writing
Problem solving in case issue and bug found
Debug RTL and gate level simulations
Los Angeles, CA
GULGOWSKI-SCHUMM
present
Infrastructure work including developing scripts and tools for efficiency and quality improvements
Develop advanced verification environment and test bench components in System Verilog using VMM or UVM
methodology
Networking domain knowledge (e.g. Ethernet, GFP, OTN)
Perform RTL code coverage, assertion coverage, and gate level simulations
Drive and adopt new verification methodologies and flows for efficiency improvements
Develop comprehensive test plan and implement test cases
Architect and develop verification environment and testbench components such as BFMs and checkers
EDUCATION
Bachelor’s Degree in Electrical Engineering
SAN DIEGO STATE UNIVERSITY
SKILLS
Excellent debug skills with ability to quickly and accurately root cause failures and make high quality verification
fixes
Proficient in Solidworks
Ability to oversee testing and produce final reports
Excellent verbal and written skills
Excellent testing and "hands on" development aptitude
Electronics knowledge
Knowledge of optical communications
Good written and oral communication skills
Good communication and teamwork skills
Good communication skills and a team player
Related
I am an Electrical Engineering graduate with no knowledge in VLSI, can I get a job as an RTL design
engineer if I know about digital design?
Yes!! U can.
But, u need a lot of interest. I will answer this question assuming that u don’t know any
Hardware Description languages(Verilog/VHDL).
Step 1: U should have good knowledge in both combinational and sequential circuits.
Especially sequential because that is key for RTL coding. Spend lot of time in learning.
Step 2: After that learn verilog, how digital circuits are implemented using verilog,
different levels of modelling (Gate level, Behavior level, Dataflow level) and know the
differences.
Step 3: Start coding small examples like adders, multiplexers, Decoders, Priority
encoders with and without clock. Once u get some hands on experience in verilog start
with sequential circuits, design flipflops, then shift- Registers (SISO, SIPO, PISO, PIPO).
Then start some mini projects like designing traffic lights, 64 bit ALU etc... Many
companies want hands on experience and depth knowledge in concepts. U should debug
any type of verilog code that was given to you and understand clock synchronizing well.
Step 4: step 2 and 3 require minimum 3 months for perfect RTL designer. How much
better u r in coding, it need practice. Since, there may be many concepts u miss, like
blocking and non-blocking assignments, loops( U should not use for,while loops in
always blocks), some miscellaneous concepts.
Step 5: Since u r in electrical domain HR’s will have on & off doubts. Like, whether he
can do this job or not? whether he had necessary pre-requisites? Y should i prefer him
rather than electronic’s guy who had relative knowledge in this domain? Is there any
specialty in him? Now, these points make u one step ahead of others:
1: Paper publications.
2: Final year projects/ Mini projects: Verilog/VHDL.
3: Internship/Training/Certificates.
4. Learn further languages like system verilog for Designers.SystemVerilog
Tutorial, IP Protocols( Not that much depth required), Scripting language either
Perl or TCl can help u further more.
Step 6: Targeting VLSI Industries, now this is very difficult step. VLSI industry is not
like software industry, VLSI industries spends lot of money with unknown result.
Because, if u take live example software industries mostly work on debugs even after the
product/Website released into market. But Chip is something different, once it was placed
in market, it should not have any bugs. So, we should predict all possible ways that may
occur which violates our Design. That is why VLSI industries want professionals or well
experienced people. Companies don’t take risk by hiring a fresher, because they need to
train him minimum 6 months and to gain experience they will assign some reverse
engineering projects. As a whole first 2 years fresher is non- Productive to company, now
with 2 years experience u will become professional and productive to company. With 3
years of experience, if u do well, now many companies will offer u decent packages and
now with 5–8 years experience u will become master in it and enjoy benefits of VLSI
industries. All u need to do is somehow u should enter into VLSI INDUSTRY.
U can ask referrals from ur seniors or college alumni, Try start-up’s, Use Job searching
platforms like Naukri, Monster jobs etc.., Through social networking like LinkedIn,
contact HR’s..
Entering into industry is difficult part, but it’s not impossible, because one of my
colleague is from Electrical department and in RTL Design, joined 5 months back,
working perfectly and he is already in SIEMENS project. So, there is hope, all u need is
interest, hard work and using opportunities perfectly.
Thank you,
Hope it answers ur question.
FPGA Prototyping/Emulation Engineer
Ceremorphic
Ceremorphic Technologies Private Limited
My Home Twitza, 8th Floor, Hitech City Main Rd, Diamond Hills, Hitech City, Hyderabad, Telangana
500081.
Hyderabad, Telangana
You must create an Indeed account before continuing to the company website to apply
About the Role
The candidate would own and drive the design, implementation, and verify FPGA prototypes of
next-generation SOCs. The responsibilities mainly cover the following:
FPGA integration and implementation of All interfaces (PCIe, DDR, etc)
FPGA implementation and timing closure
Provide emulation Platform solution for FW development
Provide emulation Platform for Pre silicon Validation
FPGA Validation and debug
Key Requirements
Hands on design experience using Verilog, System Verilog and porting large designs to FPGA
including combination of custom RTL as well as proven IP cores.
FPGA experience includes implementation, synthesis (Synplify/Vivado), timing closure using
Vivado.
Ability to partition a big AISC design into multiple FPGA sub-systems and implement modules for
interconnection between these sub-systems.
Proficiency in Perl, Tcl language.
Good hardware debug skills using FPGA debug tools like Chipscope and lab debug equipment
like Oscilloscopes and Logic Analyzers to root cause issues at silicon or board level.
Hands on experience using PCIe controller, DMA and working knowledge of AXI protocols and
ARM is required
Ability to work closely with software team and get involved in hardware-software co-debug.
