MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

General Description Features

The MAX11100 low-power, 16-bit analog-to-digital con- S 16-Bit Resolution, No Missing Codes
verter (ADC) features a successive-approximation ADC, S +5V Single-Supply Operation
automatic power-down, fast 1.1Fs wake-up, and a high-
S Adjustable Logic Level (2.7V to 5.25V)
speed SPI/QSPI™/MICROWIRE®-compatible interface.
The MAX11100 operates with a single +5V analog supply S Input Voltage Range: 0 to VREF
and features a separate digital supply, allowing direct S Internal Track-and-Hold, 4MHz Input Bandwidth
interfacing with 2.7V to 5.25V digital logic.
S SPI/QSPI/MICROWIRE-Compatible Serial Interface
At the maximum sampling rate of 200ksps, the MAX11100
S Small 10-Pin µMAX and WLP Packages
typically consumes 2.45mA. Power consumption is typi-
cally 12.25mW (VAVDD = VDVDD = +5V) at a 200ksps S Low Power
(max) sampling rate. AutoShutdown™ reduces supply 2.45mA at 200ksps
current to 140FA at 10ksps and to less than 10FA at 140µA at 10ksps
reduced sampling rates. 0.1µA in Power-Down Mode
Excellent dynamic performance and low power, com-
bined with ease of use and small package size (10-pin
FMAX® and 12-bump WLP), make the MAX11100 ideal
for battery-powered and data-acquisition applications Functional Diagram
or for other circuits with demanding power consumption
and space requirements.
AVDD DVDD
Applications
Motor Control REF
Industrial Process Control AIN
Industrial I/O Modules TRACK-AND- 16-BIT SAR OUTPUT DOUT
HOLD ADC BUFFER
AGND
Data-Acquisition Systems
Thermocouple Measurements
SCLK CONTROL
Accelerometer Measurements
Portable- and Battery-Powered Equipment CS
MAX11100

DGND
Ordering Information appears at end of data sheet.

QSPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.
AutoShutdown is a trademark and µMAX is a registered trademark of Maxim Integrated Products, Inc.
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX11100.related

For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-6046; Rev 1; 1/12
 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

ABSOLUTE MAXIMUM RATINGS

AVDD to AGND........................................................-0.3V to +6V Continuous Power Dissipation (TA = +70NC)
DVDD to DGND........................................................-0.3V to +6V FMAX (derate 5.6mW/NC above +70NC)......................444mW
DGND to AGND....................................................-0.3V to +0.3V WLP (derate 16.1mW/NC above +70NC)......1300mW (Note 1)
AIN, REF to AGND................................ -0.3V to (VAVDD + 0.3V) Operating Temperature Range........................... -40NC to +85NC
SCLK, CS to DGND..................................................-0.3V to +6V Maximum Junction Temperature......................................+150NC
DOUT to DGND..................................... -0.3V to (VDVDD + 0.3V) Storage Temperature Range............................. -65NC to +150NC
Maximum Current Into Any Pin........................................ Q50mA Lead Temperature (FMAX only; soldering, 10s)..............+300NC
Soldering Temperature (reflow).......................................+260NC
Note 1: All WLP devices are 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by
design and characterization.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, CREF = 4.7FF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY (Note 2)
Resolution 16 Bits
Relative Accuracy INL (Note 3) -2 +2 LSB
Differential Nonlinearity DNL -1 +2 LSB
Transition Noise RMS noise Q0.65 LSBRMS
Offset Error 0.1 1 mV
Gain Error (Note 4) Q0.002 Q0.01 %FSR
Offset Drift 0.4 ppm/°C
Gain Drift (Note 4) 0.2 ppm/°C
DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 2)
Signal-to-Noise Plus Distortion SINAD 86 91.5 dB
Signal-to-Noise Ratio SNR 87 91.7 dB
Total Harmonic Distortion THD -106 -90 dB
Spurious-Free Dynamic Range SFDR 92 108 dB
Full-Power Bandwidth -3dB point 4 MHz
Full-Linear Bandwidth SINAD > 86dB 10 kHz
CONVERSION RATE
Conversion Time tCONV (Note 5) 5 240 Fs
Serial Clock Frequency fSCLK 0.1 4.8 MHz
Aperture Delay tAD 15 ns
Aperture Jitter tAJ < 50 ps
Sample Rate fS fSCLK/24 200 ksps
Track/Hold Acquisition Time tACQ 1.1 Fs

Maxim Integrated   2

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, CREF = 4.7FF,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ANALOG INPUT (AIN)
Input Range VAIN 0 VREF V
Input Capacitance CAIN 40 pF
Input Leakage Current SCLK idle 0.01 10 FA
EXTERNAL REFERENCE
Input-Voltage Range VREF 3.8 VAVDD V
VREF = 4.096V, fSCLK = 4.8MHz 60 150
Input Current IREF VREF = 4.096V, SCLK idle 0.01 10 FA
CS = DVDD, SCLK idle 0.01
DIGITAL INPUTS (SCLK, CS)
0.7 x
Input High Voltage VIH VDVDD = 2.7V to 5.25V V
VDVDD
0.3 x
Input Low Voltage VIL VDVDD = 2.7V to 5.25V V
VDVDD
Input Leakage Current IIN VIN = 0 to VDVDD Q0.1 Q1 FA
Input Hysteresis VHYST 0.2 V
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT)
VDVDD
Output High Voltage VOH ISOURCE = 0.5mA, VDVDD = 2.7V to 5.25V V
- 0.25
Output Low Voltage VOL ISINK = 2mA, VDVDD = 2.7V to 5.25V 0.4 V
Three-State Output Leakage
IL CS = DVDD Q0.1 Q10 FA
Current
Three-State Output Capacitance COUT CS = DVDD 15 pF
POWER SUPPLIES
Analog Supply VAVDD 4.75 5.25 V
Digital Supply VDVDD 2.7 5.25 V
Analog Supply Current IAVDD CS = DGND, 200ksps 1.85 2.5 mA
Digital Supply Current IDVDD CS = DGND, DOUT = all zeros, 200ksps 0.6 1.0 mA
IAVDD +
Shutdown Supply Current CS = DVDD, SCLK = idle 0.1 10 FA
IDVDD
VAVDD = VDVDD = 4.75V to 5.25V, full-
Power-Supply Rejection Ratio PSRR 68 dB
scale input (Note 6)

Maxim Integrated   3

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

TIMING CHARACTERISTICS
(VAVDD = VDVDD = 4.75V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Acquisition Time tACQ 1.1 Fs
SCLK to DOUT Valid tDO CDOUT = 50pF 50 ns
CS Fall to DOUT Enable tDV CDOUT = 50pF 80 ns
CS Rise to DOUT Disable tTR CDOUT = 50pF 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0 ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns

TIMING CHARACTERISTICS
(VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to 5.25V, fSCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), VREF = 4.096V,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Acquisition Time tACQ 1.1 Fs
SCLK to DOUT Valid tDO CDOUT = 50pF 100 ns
CS Fall to DOUT Enable tDV CDOUT = 50pF 100 ns
CS Rise to DOUT Disable tTR CDOUT = 50pF 80 ns
CS Pulse Width tCSW 50 ns
CS Fall to SCLK Rise Setup tCSS 100 ns
CS Rise to SCLK Rise Hold tCSH 0 ns
SCLK High Pulse Width tCH 65 ns
SCLK Low Pulse Width tCL 65 ns
SCLK Period tCP 208 ns
Note 2: VAVDD = VDVDD = +5V.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.

Maxim Integrated   4

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Typical Operating Characteristics

(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7FF, VREF = 4.096V, TA = +25NC, unless otherwise noted.)

INTEGRAL NONLINEARITY (INL) DIFFERENTIAL NONLINEARITY (DNL) INL AND DNL

vs. CODE vs. CODE vs. ANALOG SUPPLY VOLTAGE
1.0 1.0 1.5
MAX11100 toc01

MAX11100 toc02

MAX11100 toc03
0.8 0.8 MAX INL
0.6 0.6 1.0

0.4 0.4

INL AND DNL (LSB)

0.5
0.2 0.2
DNL (LSB)
INL (LSB)

0 0 0 MAX DNL MIN DNL

-0.2 -0.2
-0.4 -0.4 -0.5

-0.6 -0.6
-1.0
-0.8 -0.8 MIN INL
-1.0 -1.0 -1.5
0 16384 32768 49152 65536 0 16384 32768 49152 65536 4.75 4.85 4.95 5.05 5.15 5.25
8192 24576 40960 57344 8192 24576 40960 57344 VAVDD (V)
OUTPUT CODE (DECIMAL) OUTPUT CODE (DECIMAL)

INL AND DNL vs. TEMPERATURE MAX11100 FFT SINAD vs. FREQUENCY
1.5 0 100
MAX11100 toc05
MAX11100 toc04

MAX11100 toc06
MAX INL 90
1.0 -20
80
-40 70
INL AND DNL (LSB)

0.5
MAGNITUDE (dB)

60
SINAD (dB)

-60
0 MAX DNL MIN DNL 50
-80 40
-0.5
-100 30
20
-1.0 MIN INL -120
10
-1.5 -140 0
-40 -15 10 35 60 85 0 10 20 30 40 50 60 70 80 90 100 0 1 10 100
TEMPERATURE (°C) FREQUENCY (kHz) FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION
SFDR vs. FREQUENCY vs. FREQUENCY
120 0
MAX11100 toc07

MAX11100 toc08

110 -10
100 -20
90 -30
80 -40
SFDR (dB)

70 -50
THD (dB)

60 -60
50 -70
40 -80
30 -90
20 -100
10 -110
0 -120
0.1 1 10 100 0 1 10 100
FREQUENCY (kHz) FREQUENCY (kHz)

Maxim Integrated   5

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7FF, VREF = 4.096V, TA = +25NC, unless otherwise noted.)

ANALOG SUPPLY CURRENT

SUPPLY CURRENT vs. SAMPLE RATE vs. SUPPLY VOLTAGE
10.0000 1.90

MAX11100 toc10
MAX11100 toc09
1.0000 1.88
IAVDD
SUPPLY CURRENT (mA)

0.1000 1.86

IAVDD (mA)
IDVDD
0.0100 1.84

0.0010 1.82

0.0001 1.80
1 10 100 1000 4.75 4.85 4.95 5.05 5.15 5.25
SAMPLE RATE (ksps) VAVDD (V)

SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE vs. SUPPLY VOLTAGE
2.5 20

MAX11100 toc12
MAX11100 toc11

18
2.0 16
SUPPLY CURRENT (mA)

14
1.5 IAVDD 12
ISHDN (nA)

10
1.0 8
6
0.5 4
IDVDD 2
0 0
-40 -15 10 35 60 85 4.75 4.85 4.95 5.05 5.15 5.25
TEMPERATURE (°C) SUPPLY VOLTAGE (V)

SHUTDOWN SUPPLY CURRENT OFFSET ERROR

vs. TEMPERATURE vs. ANALOG SUPPLY VOLTAGE
150 500
MAX11100 toc14
MAX11100 toc13
SHUTDOWN SUPPLY CURRENT (nA)

125 300
OFFSET ERROR (µV)

100
100
75
-100
50

-300
25

0 -500
-40 -15 10 35 60 85 4.75 4.85 4.95 5.05 5.15 5.25
TEMPERATURE (°C) VAVDD (V)

Maxim Integrated   6

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Typical Operating Characteristics (continued)

(VAVDD = VDVDD = 5V, fSCLK = 4.8MHz, CLOAD = 50pF, CREF = 4.7FF, VREF = 4.096V, TA = +25NC, unless otherwise noted.)

GAIN ERROR
OFFSET ERROR vs. TEMPERATURE vs. ANALOG SUPPLY VOLTAGE
500 0.010

MAX11100 toc16
MAX11100 toc15
300 0.006

GAIN ERROR (%FS)

OFFSET ERROR (µV)

100 0.002

-100 -0.002

-300 -0.006

-500 -0.010
-40 -15 10 35 60 85 4.75 4.85 4.95 5.05 5.15 5.25
TEMPERATURE (°C) VAVDD (V)

SIGNAL-TO-NOISE RATIO (SNR) AND

SIGNAL-TO-NOISE AND DISTORTION
GAIN ERROR vs. TEMPERATURE RATIO (SINAD) vs. TEMPERATURE
0.010 93.0
MAX11100 toc17

MAX11100 toc18
fIN = 1kHz

0.006 92.5
SNR AND SINAD (dB)
GAIN ERROR (%FS)

SNR
0.002 92.0

-0.002 91.5
SINAD
-0.006 91.0

-0.010 90.5
-40 -15 10 35 60 85 -40 -15 10 35 60 85
TEMPERATURE (°C) TEMPERATURE (°C)

Maxim Integrated   7

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Pin Configurations

TOP VIEW MAX11100

(BUMP SIDE DOWN)
1 2 3 4 TOP VIEW
+ REF AVDD AGND SCLK
A DOUT 1 + 10 SCLK

AGND REF DGND CS DGND 2 9 CS

MAX11100
B DVDD 3 8 AGND
AGND 4 7 AVDD
AIN AGND DVDD DOUT
AIN 5 6 REF
C

µMAX
WLP

Pin Description
PIN
NAME FUNCTION
WLP µMAX
External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7FF
A1, B2 6 REF
capacitor.
A2 7 AVDD Analog +5V Supply Voltage. Bypass to AGND with a 0.1FF capacitor.
A3, B1,
4, 8 AGND Analog Ground
C2
Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
A4 10 SCLK
4.8MHz.
B3 2 DGND Digital Ground
Active-Low Chip-Select Input. Forcing CS high places the MAX11100 shutdown with a typical
B4 9 CS current of 0.1FA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
C1 5 AIN Analog Input
C3 3 DVDD Digital Supply Voltage. Bypass to DGND with a 0.1FF capacitor.
Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when
C4 1 DOUT
CS is high.

Maxim Integrated   8

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

VDD
Detailed Description
The MAX11100 includes an input track-and-hold (T/H)
1mA
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 16-bit output.
DOUT DOUT
Figure 4 shows the MAX11100 in its simplest configura-
tion. The serial interface requires only three digital lines
1mA CLOAD = 50pF CLOAD = 50pF
(SCLK, CS, and DOUT) and provides an easy interface
DGND DGND
to microprocessors (FPs).
The MAX11100 has two power modes: normal and shut-
a) VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL down. Driving CS high places the MAX11100 in shut-
down, reducing the supply current to 0.1FA (typ), while
Figure 1. Load Circuits for DOUT Enable Time and SCLK to pulling CS low places the MAX11100 in normal operating
DOUT Delay Time mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
VDD consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface timing diagram.
1mA
Analog Input
DOUT DOUT Figure 5 illustrates the input sampling architecture of the
ADC. The voltage applied at REF sets the full-scale input
1mA CLOAD = 50pF CLOAD = 50pF voltage.

DGND DGND Track-and-Hold (T/H)

In track mode, the analog signal is acquired on the inter-
a) VOH TO HIGH-Z b) VOL TO HIGH-Z nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
Figure 2. Load Circuits for DOUT Disable Time

CS
tCSW

tCL tCH
tCSS tCSH
SCLK

tCP

tDO tTR
tDV
DOUT

Figure 3. Detailed Serial Interface Timing

Maxim Integrated   9

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

tACQ = 13(RS + RIN) x 35pF
AIN AIN CS CS where RIN = 800I, RS = the input signal’s source
SCLK SCLK impedance, and tACQ is never less than 1.1Fs. A source
VREF REF DOUT DOUT impedance less than 1kI does not significantly affect the
4.7µF MAX11100 ADC’s performance.
+5V AVDD
To improve the input signal bandwidth under AC condi-
0.1µF
+5V DVDD tions, drive AIN with a wideband buffer (> 4MHz) that
AGND can drive the ADC’s input capacitance and settle quickly.
0.1µF DGND
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-speed
GND
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
Figure 4. Typical Operating Circuit
undersampling techniques. To avoid aliasing of unwant-
ed high-frequency signals into the frequency band of
REF interest, use anti-alias filtering.
TRACK
AIN CAPACITIVE DAC
ZERO Analog Input Protection
CSWITCH Internal protection diodes, which clamp the analog input
HOLD CDAC 32pF
3pF RIN to AVDD or AGND, allow the input to swing from VAGND
GND 800Ω
- 0.3V to VAVDD + 0.3V, without damaging the device.
HOLD
TRACK If the analog input exceeds 300mV beyond the supplies,
limit the input current to 10mA.
AUTOZERO
RAIL Digital Interface
Figure 5. Equivalent Input Circuit Initialization After Power-Up and Starting a
Conversion
During the acquisition, the analog input (AIN) charges The digital interface consists of two inputs, SCLK and
capacitor CDAC. The acquisition interval ends on the CS, and one output, DOUT. A logic-high on CS places
falling edge of the sixth clock cycle (Figure 6). At this the MAX11100 in shutdown (AutoShutdown) and places
instant, the T/H switches open. The retained charge on DOUT in a high-impedance state. A logic-low on CS
CDAC represents a sample of the input. places the MAX11100 in the fully powered mode.
In hold mode, the capacitive digital-to-analog converter To start a conversion, pull CS low. A falling edge on CS
(DAC) adjusts during the remainder of the conversion initiates an acquisition. SCLK drives the A/D conversion
cycle to restore node ZERO to zero within the limits of and shifts out the conversion results (MSB first) at DOUT.
16-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
Timing and Control
Conversion-start and data-read operations are con-
switches back to AIN, and charge CDAC to the input
trolled by the CS and SCLK digital inputs (Figure 6
signal again.
and Figure 7). Ensure that the duty cycle on SCLK is
The time required for the T/H to acquire an input sig- between 40% and 60% at 4.8MHz (the maximum clock
nal is a function of how quickly its input capacitance frequency). For lower clock frequencies, ensure that
is charged. If the input signal’s source impedance is the minimum high and low times are at least 65ns.
high, the acquisition time lengthens and more time must Conversions with SCLK rates less than 100kHz can
be allowed between conversions. The acquisition time result in reduced accuracy due to leakage.
(tACQ) is the maximum time the device takes to acquire
Note: Coupling between SCLK and the analog inputs
the signal. Use the following formula to calculate acquisi-
(AIN and REF) may result in an offset.
tion time:

Maxim Integrated   10

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

CS

SCLK 1 4 6 8 12 16 20 24
tCSS tCL
tCSH
DOUT tCH D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tDV tACQ tDO
tTR

Figure 6. External Timing Diagram

COMPLETE CONVERSION SEQUENCE

CS

DOUT

CONVERSION 0 CONVERSION 1

POWERED UP POWERED DOWN POWERED UP

TIMING NOT TO SCALE.

Figure 7. Shutdown Sequence

Variations in frequency, duty cycle, or other aspects of conversion result has been clocked out, and prior to the
the clock signal’s shape result in changing offset. rising edge of CS, produce trailing zeros at DOUT and
A CS falling edge initiates an acquisition sequence. The have no effect on the converter operation.
analog input is stored in the capacitive DAC, DOUT Force CS high after reading the conversion’s LSB to
changes from high impedance to logic-low, and the ADC reset the internal registers and place the MAX11100 in
begins to convert after the sixth clock cycle. SCLK drives shutdown. For maximum throughput, force CS low again
the conversion process and shifts out the conversion to initiate the next conversion immediately after the speci-
result on DOUT. fied minimum time (tCSW).
SCLK begins shifting out the data (MSB first) after the fall- Note: Forcing CS high in the middle of a conversion
ing edge of the 8th SCLK pulse. Twenty-four falling clock immediately aborts the conversion and places the
edges are needed to shift out the eight leading zeros MAX11100 in shutdown.
and 16 data bits. Extra clock pulses occurring after the

Maxim Integrated   11

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Output Coding and Transfer Function Input Buffer
The data output from the MAX11100 is binary and Figure 8 Most applications require an input buffer amplifier to
depicts the nominal transfer function. Code transitions achieve 16-bit accuracy. If the input signal is multiplexed,
occur halfway between successive-integer LSB values switch the input channel immediately after acquisition,
(VREF = 4.096V and 1 LSB = 63FV or 4.096V/65536). rather than near the end of or after a conversion (Figure 9).
This allows the maximum time for the input buffer ampli-
Applications Information fier to respond to a large step change in the input signal.
The input amplifier must have a slew rate of at least 2V/Fs
External Reference to complete the required output-voltage change before
The MAX11100 requires an external reference with a the beginning of the acquisition time.
+3.8V and AVDD voltage range. Connect the external At the beginning of the acquisition, the internal sam-
reference directly to REF. Bypass REF to AGND with pling capacitor array connects to AIN (the amplifier
a 4.7FF capacitor. When not using a low-ESR bypass output), causing some output disturbance. Ensure that
capacitor, use a 0.1FF ceramic capacitor in parallel with the sampled voltage has settled before the end of the
the 4.7FF capacitor. Noise on the reference degrades acquisition time.
conversion accuracy.
The input impedance at REF is 40kI for DC currents. Digital Noise
During a conversion the external reference at REF must Digital noise can couple to AIN and REF. The conversion
deliver 100FA of DC load current and have an output clock (SCLK) and other digital signals active during input
impedance of 10I or less. acquisition contribute noise to the conversion result.
Noise signals synchronous with the sampling interval
For optimal performance, buffer the reference through result in an effective input offset. Asynchronous signals
an op amp and bypass the REF input. Consider the produce random noise on the input, whose high-frequen-
MAX11100’s equivalent input noise (38FVRMS) when cy components can be aliased into the frequency band
choosing a reference. of interest. Minimize noise by presenting a low imped-
ance (at the frequencies contained in the noise signal)
at the inputs. This requires bypassing AIN to AGND, or
buffering the input with an amplifier that has a small-
OUTPUT CODE
signal bandwidth of several MHz, or preferably both. AIN
FULL-SCALE has 4MHz (typ) of bandwidth.
11 . . . 111 TRANSITION
Distortion
11 . . . 110
Avoid degrading dynamic performance by choosing an
11 . . . 101
amplifier with distortion much less than the MAX11100’s
total harmonic distortion (THD = -102dB at 1kHz) at
frequencies of interest. If the chosen amplifier has
insufficient common-mode rejection, which results in
FS = VREF degraded THD performance, use the inverting configu-
V
1 LSB = REF ration (positive input grounded) to eliminate errors from
65536
00 . . . 011 this source. Low temperature-coefficient, gain-setting
00 . . . 010 resistors reduce linearity errors caused by resistance
changes due to self-heating. To reduce linearity errors
00 . . . 001
due to finite amplifier gain, use amplifier circuits with suf-
00 . . . 000
ficient loop gain at the frequencies of interest.
0 1 2 3 FS

INPUT VOLTAGE (LSB) FS - 3/2 LSB DC Accuracy

To improve DC accuracy, choose a buffer with an offset
much less than the MAX11100’s offset (1mV (max) for
Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF, +5V supply), or whose offset can be trimmed while main-
Zero Scale (ZS) = GND taining stability over the required temperature range.

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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

A0 A1
IN1

IN2 4-TO-1
MUX MAX11100

IN3 AIN

OUT
IN4 CS

CLK

CONVERSION ACQUISITION

CS

A0

A1

CHANGE MUX INPUT HERE

Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling

Serial Interfaces edge and the output is available in MSB-first format.

The MAX11100’s interface is fully compatible with SPI, Observe the SCLK to DOUT valid timing characteris-
QSPI, and MICROWIRE standard serial interfaces. tic. Clock data into the FP on SCLK’s rising edge.
If a serial interface is available, establish the CPU’s 3) Pull CS high at or after the 24th falling clock edge. If
serial interface as master, so that the CPU generates the CS remains low, trailing zeros are clocked out after
serial clock for the MAX11100. Select a clock frequency the least significant bit (D0 = LSB).
between 100kHz and 4.8MHz: 4) With CS high, wait at least 50ns (tCSW) before start-
1) Use a general-purpose I/O line on the CPU to pull CS low. ing a new conversion by pulling CS low. A conver-
2) Activate SCLK for a minimum of 24 clock cycles. The sion can be aborted by pulling CS high before the
serial data stream of eight leading zeros followed by conversion ends. Wait at least 50ns before starting a
the MSB of the conversion result begins at the fall- new conversion.
ing edge of CS. DOUT transitions on SCLK’s falling

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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Data can be output in three 8-bit sequences or con-
I/O CS tinuously. The bytes contain the results of the conversion
SCK SCLK padded with eight leading zeros before the MSB. If the
MISO DOUT serial clock has not been idled after the LSB (D0) and CS
VDD
SPI has been kept low, DOUT sends trailing zeros.
MAX11100 SPI and MICROWIRE Interfaces
When using the SPI (Figure 10a) or MICROWIRE (Figure 10b)
SS
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS (Figure 10c). Three con-
Figure 10a. SPI Connections secutive 8-bit readings are necessary to obtain the entire
16-bit result from the ADC. DOUT data transitions on
the serial clock’s falling edge. The first 8-bit data stream
I/O CS contains all leading zeros. The second 8-bit data stream
SK SCLK
contains the MSB through D8. The third 8-bit data stream
SI DOUT contains D7 through D0.
MICROWIRE

MAX11100

Figure 10b. MICROWIRE Connections

1ST BYTE READ 2ND BYTE READ

1 4 6 8 12 16
SCLK
CS

0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7

DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z

3RD BYTE READ

20 24

HIGH-Z
D7 D6 D5 D4 D3 D2 D1 D0
TIMING NOT TO SCALE.
LSB

Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)

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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

CS CS
SCK SCLK
MISO DOUT
QSPI VDD

MAX11100
SS

Figure 11a. QSPI Connections

SCLK 1 4 6 8 12 16 20 24
CS
END OF
HIGH-Z
DOUT* ACQUISITION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
*WHEN CS IS HIGH, DOUT = HIGH-Z

Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)

PIC16 with SSP Module and PIC17 Interface

VDD VDD
The MAX11100 is compatible with a PIC16/PIC17 micro-
controller (FC) using the synchronous serial-port (SSP)
SCLK SCK module.
DOUT SDI To establish SPI communication, connect the controller
CS I/O as shown in Figure 12a. Configure the PIC16/PIC17 as
PIC16/17
system master, by initializing its synchronous serial-port
MAX11100 control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Table 1 and Table 2.
GND
In SPI mode, the PIC16/PIC17 FC allows 8 bits of data
to be synchronously transmitted and received simultane-
Figure 12a. SPI Interface Connection for a PIC16/PIC17 ously. Three consecutive 8-bit readings (Figure 12b) are
necessary to obtain the entire 16-bit result from the ADC.
QSPI Interface DOUT data transitions on the serial clock’s falling edge
Using the high-speed QSPI interface with CPOL = 0 and and is clocked into the FC on SCLK’s rising edge. The
CPHA = 0, the MAX11100 supports a maximum fSCLK first 8-bit data stream contains all zeros. The second 8-bit
of 4.8MHz. Figure 11a shows the MAX11100 connected data stream contains the MSB through D8. The third 8-bit
to a QSPI master and Figure 11b shows the associated data stream contains bits D7 through D0.
interface timing.

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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

1ST BYTE READ 2ND BYTE READ

12 16
SCLK
CS

0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7

DOUT*
MSB
*WHEN CS IS HIGH, DOUT = HIGH-Z

3RD BYTE READ

20 24

HIGH-Z
D7 D6 D5 D4 D3 D2 D1 D0
TIMING NOT TO SCALE.
LSB

Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)

Table 1. Detailed SSPCON Register Contents

MAX11100
CONTROL BIT SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
SETTINGS
WCOL BIT 7 X Write Collision Detection Bit
SSPOV BIT 6 X Receive Overflow Detect Bit
Synchronous Serial-Port Enable Bit:
SSPEN BIT 5 1 0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP BIT 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 BIT 3 0
SSPM2 BIT 2 0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC/16.
SSPM1 BIT 1 0
SSPM0 BIT 0 1

Table 2. Detailed SSPSTAT Register Contents

MAX11100
CONTROL BIT SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SETTINGS
SMP BIT 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE BIT 6 1 SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A BIT 5 X Data Address Bit
P BIT 4 X STOP Bit
S BIT 3 X START Bit
R/W BIT 2 X Read/Write Bit Information
UA BIT 1 X Update Address
BF BIT 0 X Buffer Full Status Bit

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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Definitions Effective Number of Bits

Effective number of bits (ENOB) indicate the global
Integral Nonlinearity accuracy of an ADC at a specific input frequency and
Integral nonlinearity (INL) is the deviation of the values sampling rate. An ideal ADC error consists of quantiza-
on an actual transfer function from a straight line. This tion noise only. With an input range equal to the full-scale
straight line can be either a best-fit straight line fit or a range of the ADC, calculate the effective number of bits
line drawn between the endpoints of the transfer function, as follows:
once offset and gain errors have been nulled. The static ENOB = (SINAD - 1.76)/6.02
linearity parameters for the MAX11100 are measured Figure 13 shows the effective number of bits as a function
using the endpoint method. of the MAX11100’s input frequency.
Differential Nonlinearity Total Harmonic Distortion
Differential nonlinearity (DNL) is the difference between Total harmonic distortion (THD) is the ratio of the RMS
an actual step width and the ideal value of 1 LSB. A DNL sum of the first five harmonics of the input signal to the
error specification of 1 LSB guarantees no missing codes fundamental itself. This is expressed as:
and a monotonic transfer function.
 
Aperture Definitions V 2 + V3 2 + V4 2 + V5 2 
Aperture jitter (tAJ) is the sample-to-sample variation in = 20 × log 2
THD
 V1 
the time between samples. Aperture delay (tAD) is the  
time between the falling edge of the sampling clock and
the instant when the actual sample is taken. where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital Spurious-Free Dynamic Range
samples, signal-to-noise ratio (SNR) is the ratio of the Spurious-free dynamic range (SFDR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza- RMS amplitude of the fundamental (maximum signal
tion error (residual error). The ideal, theoretical minimum component) to the RMS value of the next largest fre-
analog-to-digital noise is caused by quantization noise quency component.
error only and results directly from the ADCs resolution
(N bits):
16
SNR = (6.02 x N + 1.76)dB
14
In reality, there are other noise sources besides quantiza-
EFFECTIVE NUMBER OF BITS

tion noise: thermal noise, reference noise, clock jitter, etc. 12

SNR is computed by taking the ratio of the RMS signal to 10
the RMS noise, which includes all spectral components
8
minus the fundamental, the first five harmonics, and the
DC offset. 6

Signal-to-Noise Plus Distortion 4

Signal-to-noise plus distortion (SINAD) is the ratio of 2

the fundamental input frequency’s RMS amplitude to
0
the RMS equivalent of all the other ADC output signals, 0.1 1 10 100
excluding the DC offset. INPUT FREQUENCY (kHz)

 SignalRMS 
= 20 × log 
SINAD(dB)  Figure 13. Effective Number of Bits vs. Input Frequency
 (
Noise + Distortion) RMS 


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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Supplies, Layout, Grounding, and Bypassing Ordering Information
Use PCBs with separate analog and digital ground
planes. Do not use wire-wrap boards. Connect the two PART TEMP RANGE PIN-PACKAGE
ground planes together at the MAX11100. Isolate the
MAX11100EUB+ -40NC to +85NC 10 FMAX
digital supply from the analog with a low-value resistor
MAX11100EWC+ -40NC to +85NC 12 WLP
(10I) or ferrite bead when the analog and digital sup-
plies come from the same source (Figure 14). +Denotes a lead(Pb)-free/RoHS-compliant package.
Constraints on sequencing the power supplies and
inputs are as follows: Chip Information
U Apply AGND before DGND.
PROCESS: BiCMOS
U Apply AIN and REF after AVDD and AGND are present.
U DVDD is independent of the supply sequencing. Package Information
Ensure that digital return currents do not pass through For the latest package outline information and land patterns (foot-
the analog ground and that return-current paths are prints), go to www.maximintegrated.com/packages. Note that a
low impedance. A 5mA current flowing through a PCB “+”, “#”, or “-” in the package code indicates RoHS status only.
ground trace impedance of only 0.05I creates an error Package drawings may show a different suffix character, but
voltage of about 250FV, 4 LSB error with a +4V full-scale the drawing pertains to the package regardless of RoHS status.
system. PACKAGE PACKAGE OUTLINE LAND
The board layout should ensure that digital and analog TYPE CODE NO. PATTERN NO.
signal lines are kept separate. Do not run analog and dig- 10 FMAX U10+2 21-0061 90-0330
ital (especially the SCLK and DOUT) lines parallel to one
Refer to
another. If one must cross another, do so at right angles.
12 WLP W121A2+1 21-0009 Application
The ADCs high-speed comparator is sensitive to high- Note 1891
frequency noise on the AVDD power supply. Bypass an
excessively noisy supply to the analog ground plane with
a 0.1FF capacitor in parallel with a 1FF to 10FF low-ESR
capacitor. Keep capacitor leads short for best supply-
noise rejection.

AIN AIN CS CS
SCLK SCLK
VREF REF DOUT DOUT
4.7µF MAX11100
+5V AVDD

10Ω

0.1µF DVDD
AGND
0.1µF DGND

GND

Figure 14. Powering AVDD and DVDD from a Single Supply

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 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 9/11 Initial release —
1 1/12 Revised the Absolute Maximum Ratings and Electrical Characteristics. 2–4

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 19
© 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Maxim Integrated   20

 MAX11100

16-Bit, +5V, 200ksps ADC with 10µA Shutdown

Maxim Integrated   21