[go: up one dir, main page]

0% found this document useful (0 votes)
19 views3 pages

HPCA Assignment 1& 2 For Improvement & Backlog

Download as pdf or txt
Download as pdf or txt
Download as pdf or txt
You are on page 1/ 3

Assignment: 1 & Assignment 2

&
HPCA Syllabus For Midsem Exam
08 July 2023 05:50
(Submit you r Assig nm ents on the Day of Midse m Exa m )

Assignment: 1

1. What are the use of various components of MIPS data path unit example. In
latest MIPS pipeline data path unit , how branch address is evaluated in the
decoding unit, Explain the above with neat diagram.
2. Find out the minimum no of clock cycle required towards the completion of
following expression without and with using Operand forwarding technique in 5
stage pipelines.

A, B, C, D,E represents the memory variables.


A =B+CD=A +E

3(a). How to find the CPU Execution time of a machine? What is the use of
SpeedUp factor in the performance evaluation of a computer.

3.(b) Find the average CPI, Execution time of a program that contains 50000
instruction and it is feed to a machine that supports the Mixed instruction type
with 1MHZ clock rate. Assume that 30% instruction are data transfer
instruction, 40% instruction are ALU instruction and the rest are the control
instruction. Each of data transfer, ALU and control instruction takes respectively
6clk cycle, 4clk cycle and 7 clk cycle.
© Referring to Q3(b) If the same machine subject to change in some hardware
and software configuration. Adding some more hardware change the clock rate
from 1 MHZ to 2 MHZ and using updated compiler the number of instruction
of the program changes from 50000 to 40000 then find the Speed up gain of the
machine.
Assignment -2

1. What is Dynamic Scheduling and what are the 4 stages used in scoreboard
toperform Dynamic Scheduling.

2. Suppose you have a data science pipeline with 3 operators that take 5s, 10s,
and 15s to execute, respectively. According to Amdahl's law, what is the
maximum speedup you can achieve by optimizing the 2nd operator?

3. Perform the Dynamic Scheduling of the following codes with Scoreboard


technique
L.D F2, 5(R3) MUL.D F0, F2, F3ADD.D F5, F3, F4DIV.D F10, F6, F3
With these given information:

HPCA Syllabus For Midsem Exam ::

Overview of Computer Architecture ::


1.Introduction To High performance Computer Architecture
2.Review of basic computer architectures
3.Introduction to instruction Set architecture (ISA)
I.CISC & RISC processor with examples
4 Measuring and Reporting Performance
I.Processor performance equation (with numerical)
II.Performance Measurement with respect to execution time, CPU time(concept with
numerical)
III.Performance Measurement with respect to the basic performance equation (concept with
numerical)
IV.Amdahl’s law (concept with Exercises on speedup and overall speedup calculation)
Pipelining ::
1 Basic concepts to parallel processing & pipelining Concept.
2 Introduction to MIPS Architecture with its data path
I.Registers in MIPS
II.MIPS Instruction Format(R type,I Type and J type)
III.MIPS Instruction set with examples
IV.MIPS Data-path and Control
3 A brief introduction to Hazard and Types of Hazards (Concepts and exercises)
I.Structural Hazard
II.Data Hazard (Inter-instruction dependency with suitable examples:)
III.Control Hazard
4 Pipeline Stall Cycles and its possible effects on performance (Concepts and exercises)
I. A technique for overcoming or reducing the effects of Various hazards (Solutions to
different Hazards) (concepts and numericals)
II. Operand forwarding and Instruction scheduling
III.Flush pipeline, Branch Prediction, Delay Slot

You might also like