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Single-layer MoS2 transistors

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 LETTERS
PUBLISHED ONLINE: 30 JANUARY 2011 | DOI: 10.1038/NNANO.2010.279

Single-layer MoS2 transistors

B. Radisavljevic1, A. Radenovic2, J. Brivio1, V. Giacometti1 and A. Kis1 *

Two-dimensional materials are attractive for use in next-gener- Ion/Ioff between 1 × 104 and 1 × 107 and a bandgap exceeding
ation nanoelectronic devices because, compared to one-dimen- 400 meV (ref. 26) are desirable.
sional materials, it is relatively easy to fabricate complex The starting point for the fabrication of our transistors was
structures from them. The most widely studied two-dimensional scotch tape-based micromechanical exfoliation1,17 of single-layer
material is graphene1,2, both because of its rich physics3–5 and its MoS2. MoS2 monolayers were transferred to degenerately doped
high mobility6. However, pristine graphene does not have a silicon substrates covered with 270-nm-thick SiO2 (Fig. 2a). We
bandgap, a property that is essential for many applications, have previously found that this oxide thickness is optimal for
including transistors7. Engineering a graphene bandgap optical detection of single-layer MoS2 , and have established the cor-
increases fabrication complexity and either reduces mobilities relation between contrast and thickness as measured by atomic force
to the level of strained silicon films8–13 or requires high vol- microscopy (AFM)27. Electrical contacts were fabricated using elec-
tages14,15. Although single layers of MoS2 have a large intrinsic tron-beam lithography followed by deposition of 50-nm-thick gold
bandgap of 1.8 eV (ref. 16), previously reported mobilities in electrodes. The device was then annealed at 200 8C to remove resist
the 0.5–3 cm2 V21 s21 range17 are too low for practical devices. residue28 and decrease contact resistance (for more details see
Here, we use a halfnium oxide gate dielectric to demonstrate Supplementary Information). At this point our single-layer
a room-temperature single-layer MoS2 mobility of at least devices show a typical mobility in the range 0.1–10 cm2 V21 s21,
200 cm2 V21 s21, similar to that of graphene nanoribbons, and similar to previously reported values for single layers17 and thin
demonstrate transistors with room-temperature current on/off crystals containing more than 10 layers of MoS2 (ref. 29). This is
ratios of 1 3 108 and ultralow standby power dissipation. lower than the previously reported phonon-scattering-limited
Because monolayer MoS2 has a direct bandgap16,18, it can be room-temperature mobility in the 200–500 cm2 V21 s21 range for
used to construct interband tunnel FETs19, which offer lower bulk MoS2 (ref. 30). Encouraged by recent theoretical predictions
power consumption than classical transistors. Monolayer of mobility improvement by dielectric screening31 and its successful
MoS2 could also complement graphene in applications that application to graphene32, we proceeded with atomic layer depo-
require thin transparent semiconductors, such as optoelectro- sition (ALD) of 30 nm HfO2 as a high-k gate dielectric for the
nics and energy harvesting. local top gate and mobility booster to realize the full potential of
MoS2 is a typical example from the layered transition-metal the single-layer MoS2. We chose HfO2 because of its high dielectric
dichalcogenide family of materials. Crystals of MoS2 are composed constant of 25, bandgap of 5.7 eV and the fact that it is commonly
of vertically stacked, weakly interacting layers held together by used as a gate dielectric both by the research community and major
van der Waals interactions (Fig. 1a). Single layers, 6.5 Å thick microprocessor manufacturers33,34. The resulting structure, com-
(Fig. 1b,c), can be extracted using scotch tape17,20 or lithium-based posed of two field-effect transistors connected in series, is shown
intercalation21,22. Large-area thin films can also be prepared using in Fig. 2b. A schematic depiction of the device is shown in
MoS2 suspensions. Bulk MoS2 is semiconducting with an indirect Fig. 2c. The width of the top gate of our device was 4 mm and the
bandgap of 1.2 eV (ref. 23), whereas single-layer MoS2 is a direct top gate length, source–gate and gate–drain spacing were 500 nm.
gap semiconductor16,18 with a bandgap of 1.8 eV (ref. 16). MoS2 We performed electrical characterization of our device at room
nanotubes24 and nanowires25 also show the influence of quantum- temperature using a semiconductor parameter analyser and shielded
mechanical confinement in their electronic and optical properties. probe station with voltage sources connected in the configuration
Other features that could make MoS2 interesting for nanoelectronic depicted in Fig. 3a. We first characterized our MoS2 transistors with
applications include the absence of dangling bonds and thermal 6.5-Å-thick conductive channels by applying a drain–source bias
stability up to 1,100 8C. Vds to a pair of gold electrodes and gate voltage Vbg to the degenerately
Single-layer MoS2 could also be interesting as a semiconducting doped silicon substrate while leaving the top gate electrically float-
analogue of graphene, which does not have a bandgap in its pristine ing35. The gating characteristics of the left-most transistor shown in
form. Bandgaps up to 400 meV have been introduced by quantum- Fig 2b are presented in Fig. 3b; these are typical of FET devices
mechanical confinement in patterned8 or exfoliated graphene nano- with an n-type channel. We concentrate on this device in the remain-
ribbons9, but always at the price of significant mobility reduction der of this Letter. Characterization details for other devices and fabri-
(200 cm2 V21 s21 for a 150 meV bandgap)9,10, loss of coherence11 cation batches are available in the Supplementary Information. All the
or increased off-state currents due to edge roughness12. Bandgaps MoS2 transistors we fabricated, regardless of the number of layers or
have also been induced by applying a perpendicular electric field in contacting material, show behaviour typical of FET devices with
bilayer graphene14,15, but the highest reported optical gap is n-type channels. Repeated Vbg sweeps on the same device do not
250 meV, requiring the application of a voltage exceeding 100 V show significant variation, while keeping all the voltages constant
(ref. 14). This makes it very difficult to build logic circuits based on results in constant Ids , indicating that the top gate is not likely to
graphene that would operate at room temperature with low accumulate charge during measurements. We estimate that a constant
standby power dissipation. In fact, for any potential replacement of surface charge of n ≈ 4.6 × 1012 cm22 trapped on the top gate
silicon in CMOS-like digital logic devices, a current on/off ratio7 would shift the threshold voltage by 1 V but not change the

1
Electrical Engineering Institute, Ecole Polytechnique Federale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland, 2 Institute of Biotechnology, Ecole
Polytechnique Federale de Lausanne (EPFL), CH-1015 Lausanne, Switzerland. *e-mail: andras.kis@epfl.ch

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© 2011 Macmillan Publishers Limited. All rights reserved.

LETTERS NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2010.279

a we exclude the possibility that our field-effect behaviour is domi-

nated by Schottky barriers at the contacts.
Although the room-temperature value of phonon-scattering
limited30 mobility for bulk MoS2 is in the 200–
6.5 Å
500 cm2 V21 s21 range, exfoliation of single layers onto SiO2
results in a decrease of mobility to 0.1–10 cm2 V21 s21. The
improvement in mobility with the deposition of a high-k dielectric
could be due to suppression of Coulomb scattering due to the high-
k dielectric environment31 and modification of phonon dispersion36
in MoS2 monolayers. Extensive future theoretical work including
the calculation of phonon dispersion relations in single-layer
MoS2 , calculation of scattering rates on phonons and charge impu-
S rities would be needed to provide a complete picture.
Mo Before we compare the value of mobility in our case with the mobi-
lity of graphene or thin-film silicon we should note that semiconduc-
tors such as carbon nanotubes or graphene nanoribbons mostly
b 3.0
follow the general trend of decreasing mobility with increasing
2.5 bandgap26. Even though graphene has a high room-temperature
mobility of 120,000 cm2 V21 s21, this value relates to large-area,
2.0
gapless graphene6. On the other hand, measurements on 10-nm-
wide graphene nanoribbons with Eg ≈ 400 mV indicate mobilities
µm

1.5

1.0
lower than 200 cm2 V21 s21 (ref. 9), in good agreement with theoreti-
cal models that predict decreased mobility in small-width graphene
0.5 nanoribbons due to electron–phonon scattering13. This is comparable
0.0
to the mobility of 250 cm2 V21 s21 found in 2 nm thin strained
0 1 2 3 4 5 6 silicon films37. Our MoS2 monolayer has similar mobility but a
µm higher bandgap than graphene nanoribbons9, and a smaller thickness
than the thinnest silicon films fabricated to date37.
c 2.0 One of the crucial requirements for building integrated circuits
1.5 based on single layers of MoS2 is the ability to control charge
density in a local manner, independently of a global back gate.
Height (nm)

1.0
We can do this by applying a voltage Vtg to the top gate, separated
0.5 from the monolayer MoS2 by 30 nm of HfO2 (Fig. 3a), while
0.0 keeping the substrate grounded. The corresponding transfer charac-
6.5 Å teristic is shown in Fig. 4a. For a bias of 10 mV we observe an
−0.5

−1.0 a SiO2 b Gates HfO2

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Lateral distance (µm)

Figure 1 | Structure and AFM imaging of monolayer MoS2. a, Three- Monolayer

dimensional representation of the structure of MoS2. Single layers, 6.5 Å MoS2
thick, can be extracted using scotch tape-based micromechanical cleavage.
b, Atomic force microscope image of a single layer of MoS2 deposited on a Leads
silicon substrate with a 270-nm-thick oxide layer. c, Cross-sectional plot
along the red line in b.
c Top gate Monolayer MoS2
Drain Source
slope of the Ids – Vbg curve in Fig. 3b used for estimating channel
mobility. The source current versus source bias characteristics (Fig
3b, inset) is linear in the +50 mV range of voltages, indicating that
our gold contacts are ohmic. HfO2
The on-resistance of our transistor was 27 kV for Vds ¼ 10 mV SiO2
and Vbg ¼ 10 V, with a gate width of 4 mm and bottom gate length
of 1.5 mm. We have noticed that the device resistance can increase Si substrate
during storage at ambient conditions for a period of two
months. This could be attributed to absorption of oxygen
and/or water from the environment and could be mitigated by
device encapsulation. Figure 2 | Fabrication of MoS2 monolayer transistors. a, Optical image of a
From the data presented in Fig. 3b we can extract the low-field single layer of MoS2 (thickness, 6.5 Å) deposited on top of a silicon
field-effect mobility of 217 cm2 V21 s21 using the expression substrate with a 270-nm-thick SiO2 layer. b, Optical image of a device based
m ¼ [dIds/dVbg] × [L/(WCiVds)], where L ¼ 1.5 mm is the channel on the flake shown in a. The device consists of two field-effect transistors
length, W ¼ 4 mm is the channel width and Ci ¼ 1.3 × connected in series and defined by three gold leads that serve as source and
1024 F m22 is the capacitance between the channel and the back drain electrodes for the two transistors. Monolayer MoS2 is covered by
gate per unit area (Ci ¼ 101r/d; 1r ¼ 3.9; d ¼ 270 nm). Note that 30 nm of ALD-deposited HfO2 that acts both as a gate dielectric and a
this value represents the lower limit because of contact resistance. mobility booster. Scale bars (a,b), 10 mm. c, Three-dimensional schematic
As our device displays ohmic Ids–Vds behaviour (Fig. 3b, inset), view of one of the transistors shown in b.

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NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2010.279 LETTERS
a semiconductor, because interband transitions there require
Vds Vtg phonons and recombination centres.
Ids To summarize, we have realized a field-effect transistor with a
Cr/Au
single, two-dimensional layer of the semiconductor MoS2 as a con-
30 nm HfO2
ductive channel and HfO2 as a gate insulator. The conductive
Au Au 50 nm
0.65 nm channel in our device is only 6.5 Å thick. Our transistor exhibits a
SiO2 270 nm
room-temperature current on/off ratio exceeding 1 × 108 and
mobility of 200 cm2 V21 s21, comparable to the mobility achieved
Si in thin silicon films37 or graphene nanoribbons9. Such a transistor
Vbg could form the backbone of future electronics based on layered
materials in which MoS2 transistors could be fabricated on insulat-
b ing boron nitride substrates40. Our results provide an important step
350 towards the realization of electronics and low-standby-power inte-
1.0
grated circuits based on two-dimensional materials. Being a thin,
300 Vds = 10 mV
Ids (µA)

transparent semiconducting material, MoS2 monolayers also

0.0
250 present a wealth of new opportunities in areas that include meso-
Current Ids (nA)

scopic physics, optoelectronics and energy harvesting. With the

−1.0
200 possibility of fabricating large-area circuits using solution-based
−40 −20 0 20 40
150 Vds (mV) a
µ = 217 cm2 V–1 s–1 10−4
Vbg = 0 V Vds = 500 mV
100 10−5
100 mV
10−6
50 10 mV
10−7
0 Current Ids (A)
10−8
−10 −5 0 5 10 200
Back gate voltage Vbg (V) 10−9 Vds = 10 mV

Ids (nA)
10−10
Figure 3 | Characterization of MoS2 monolayer transistors. a, Cross- 100
10−11 Vbg
sectional view of the structure of a monolayer MoS2 FET together with
electrical connections used to characterize the device. A single layer of 10−12 0
S = 74 mV dec−1
MoS2 (thickness, 6.5 Å) is deposited on a degenerately doped silicon 10−13 −4 0 4
substrate with 270-nm-thick SiO2. The substrate acts a back gate. One of Vtg
10−14
the gold electrodes acts as drain and the other source electrode is grounded.
−4 −2 0 2 4
The monolayer is separated from the top gate by 30 nm of ALD-grown
Top gate voltage Vtg (V)
HfO2. The top gate width for the device is 4 mm and the top gate length,
source–gate and gate–drain spacing are each 500 nm. b, Room-temperature
b 800
transfer characteristic for the FET with 10 mV applied bias voltage Vds. Back- Vbg = 0 V
gate voltage Vbg is applied to the substrate and the top gate is disconnected. 600
Inset: Ids–Vds curve acquired for Vbg values of 0, 1 and 5 V.
400
on-current of 150 nA (37 nA mm21), current on/off ratio Ion/Ioff .
Current Ids (nA)

200
1 × 106 for the +4 V range of Vtg , an off-state current that is smaller
than 100 fA (25 fA mm21) and gate leakage lower than 2 pA mm22. 0
The observed current variation for different values of Vtg indicates
that the field-effect behaviour of our transistor is dominated by −200
the MoS2 channel and not the contacts. Vtg = 4 V
−400
At the bias voltage Vds ¼ 500 mV, the maximal measured on- Vtg = −1.25 V
current is 10 mA (2.5 mA mm21), with Ion/Ioff higher than 1 × 108 −600 Vtg = −1.75 V
for the +4 V range of Vtg. The device transconductance, defined as Vtg = −2.5 V
gm ¼ dIds/dVtg at Vds ¼ 500 mV is 4 mS (1 mS mm21), similar to −800
values obtained for high-performance CdS nanoribbon array transis- −40 −20 0 20 40
tors (2.5 mS mm21 at Vds ¼ 1 V)38. High-performance top-gated Drain voltage Vds (mV)
graphene transistors can have normalized transconductance values
as high as 1.27 mS mm21 (ref. 39). The large degree of current Figure 4 | Local gate control of the MoS2 monolayer transistor. a, Ids–Vtg
control in our device is also clearly illustrated in Fig. 4b, where we curve recorded for a bias voltage ranging from 10 mV to 500 mV.
plot the drain–source current versus drain–source bias for different Measurements are performed at room temperature with the back gate
values of voltage applied to the local gate. From the channel grounded. Top gate width, 4 mm; top gate length, 500 nm. The device can
current dependence on top-gate voltage, we deduce a subthreshold be completely turned off by changing the top gate bias from –2 to –4 V. For
slope for the transition between the on and off states of Vds ¼ 10 mV, the Ion/Ioff ratio is .1 × 106. For Vds ¼ 500 mV, the Ion/Ioff ratio
74 mV dec21 for a bias Vds ¼ 500 mV. Being a direct gap semicon- is .1 × 108 in the measured range while the subthreshold swing S ¼
ductor, single layers of MoS2 offer the intriguing possibility for the 74 mV dec21. Top and bottom gate leakage is negligible (Supplementary
realization of an interband tunnel FET, which is characterized by a Fig. S3). Inset: Ids–Vtg for values of Vbg ¼ –10, –5, 0, 5 and 10 V. b, Ids–Vds
turn-on sharper than the theoretical limit of 60 mV dec21 for classi- curves recorded for different values of Vtg. The linear dependence of the
cal transistors and consequently smaller power dissipation. This feat current on bias voltage for small voltages indicates that the gold contacts
has remained difficult in the case of silicon, an indirect gap are ohmic.

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LETTERS NATURE NANOTECHNOLOGY DOI: 10.1038/NNANO.2010.279

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erratum

Single-layer MoS2 transistors

B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti and A. Kis

Nature Nanotechnology doi:10.1038/nnano.2010.279 (2011); published online: 30 January 2011; corrected online: 17 February 2011.

In the version of this Letter originally published online, the label ‘Vtg’ was missing from Fig. 3a and the expression ‘μ = 217 cm−2 Vs’
should have read ‘μ = 217 cm2 V−1 s−1’ in Fig. 3b. These errors have now been corrected in all versions of the Letter.

© 2011 Macmillan Publishers Limited. All rights reserved.

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