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Physica E 16 (2003) 42 – 46
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Logic circuits based on carbon nanotubes

A. Bachtolda; b;∗ , P. Hadleya , T. Nakanishia , C. Dekkera
a Department of Applied Physics and DIMES, Delft University of Technology, Lorentzweg 1, 2628 CG Delft, The Netherlands
b LPMC, Ecole Normale Sup(
erieure, 24 rue Lhomond, 75005 Paris, France

Abstract

We demonstrate logic circuits with -eld-e/ect transistors based on single carbon nanotubes. A new technique is used
for achieving local gates in nanotube -eld-e/ect transistors that provide excellent capacitive coupling between the gate and
nanotube, enabling the transistor to be ambipolar. The transistors show favorable device characteristics such as a high gain,
a large on-o/ ratio, and room-temperature operation. Importantly, it also allows for the integration of multiple devices on a
single chip. Indeed, we demonstrate 1-, 2-, and 3-transistor circuits that exhibit a wide range of digital logic operations such
as an inverter, a logic NOR, and an AC ring oscillator.
? 2002 Elsevier Science B.V. All rights reserved.

Keywords: Nanotube; Electronic transport; Logic circuits

The anticipated limits to the further miniaturiza- nanotube by a gate oxide layer of only a few nm thick-
tion of microelectronics have led to intense research ness. Fig. 1a and b show an atomic force microscope
directed towards the development of molecular elec- image and a schematic cross section of the device,
tronics. The use of single-wall carbon nanotubes has respectively. The gate consists of a microfabricated Al
stimulated these e/orts because these molecules ex- wire with a well-insulating native Al2 O3 layer that lies
hibit a range of suitable properties for nanoelectron- beneath a semiconducting nanotube which is electri-
ics. Various basic single-nanotube components have cally contacted to two Au electrodes. This con-gura-
recently been demonstrated, such as molecular wires, tion, where the Al2 O3 thickness of a few nm is much
diodes, -eld-e/ect transistors, and single-electron shorter than the separation between the contact elec-
transistors [1–6]. The next challenge in the devel- trodes (∼ 100 nm), allows for an excellent capacitive
opment of molecular electronics is to go beyond coupling between the gate and the nanotube. More-
single-molecule components and integrate such de- over, di/erent local Al gates can easily be patterned
vices onto a chip to demonstrate digital logic op- such that each one addresses a di/erent nanotube tran-
erations. Here, we report such logic circuits using sistor. This layout thus allows the integration of mul-
single-nanotube -eld-e/ect transistors. tiple nanotube -eld-e/ect transistors (FETs) on the
The main innovative aspect of our nanotube tran- same chip.
sistor layout is a local gate that is insulated from the Our nanotube circuits are realized in a three-step
process. First, Al gates are patterned using electron
∗ Corresponding author. LPMC, Ecole Normale Sup= erieure, 24
beam lithography on an oxidized Si wafer. During
rue Lhomond, 75005 Paris, France. Fax: +33-1-44-32-38-40. evaporation, the sample was cooled to liquid nitrogen
E-mail address: bachtold@lpmc.ens.fr (A. Bachtold). temperature in order to minimize the roughness of the

1386-9477/03/$ - see front matter ? 2002 Elsevier Science B.V. All rights reserved.
PII: S 1 3 8 6 - 9 4 7 7 ( 0 2 ) 0 0 5 8 0 - 5
 A. Bachtold et al. / Physica E 16 (2003) 42 – 46 43

Fig. 2. Room-temperature characteristics of a single nanotube

transistor. (a–c) Current as a function of the gate voltage for
three di/erent samples. Data were taken at Vsd = 5 mV in vacuum
Fig. 1. Device layout. (a) Height image of a single-nanotube tran- (about 10−4 mbar). (d) I − Vsd curves at various values of Vg
sistor, as acquired by an atomic force microscope. (b) Schematic for a di/erent nanotube transistor. Lines are guides to the eye.
side view of the device. A semiconducting nanotube is contacted
by two Au electrodes. An Al wire, which is covered by a few nm
thin oxide layer, is used as a gate. (Fig. 2a) shows that both p- and n-type carriers can be
injected in the nanotube. Starting from a negative Vg ,
the current -rst decreases, then becomes immeasur-
Al surface. The insulator layer consisted of the native ably small, and -nally increases again. This indicates
oxide that grows by exposing the sample to air. The that Vg shifts the Fermi level successively from the
precise thickness of this layer is diGcult to determine, valence band (accumulation regime) to the gap (de-
but is on the order of a few nanometers. Capacitance pletion) and -nally to the conduction band (inversion)
measurements on two large Al -lms separated by of the semiconducting nanotube. The nearby Al gate
such an oxide layer indicates a thickness of about thus enables the transistor to be ambipolar. Several
2 nm, whereas ellipsometry measurements indicate volts can be applied on the gate without destroying
a value of about 4 nm. Secondly, single-wall carbon the oxide layer. This is quite remarkable since the
nanotubes produced by laser ablation are dispersed insulator layer is only a few nanometers thin, and it
on the wafer from a dispersion in dichloroethane. indicates the excellent quality of the gate oxide. The
Using an atomic force microscopy, those nanotubes breakdown threshold voltage where the layer is des-
are selected that have a diameter of about 1 nm and troyed is typically between 2 and ¿ 4 V. A small
that are situated on top of the Al gate wires. Their gate leakage current (few pA) is observed for Vg
coordinates are registered with respect to alignment approaching such large gate voltages.
markers. Finally, contact electrodes are fabricated Fig. 2b and c show I (Vg ) curves for two other
with electron-beam lithography by evaporating Au samples that have also been measured by sweeping
directly on the nanotube without an adhesion layer. the gate on large voltages. The three curves bare a lot
The same gold wires serve as interconnect wires that in common. The Vg gap size as well the asymmetry
connect the various nanotube FETs. on the p- and n-side are very similar from one sample
Fig. 2 shows the device characteristics of a typi- to the other. These data have allowed us a compari-
cal nanotube FET. The variation of the current I son with a semi-classical model based on Poisson’s
through the device as a function of the gate voltage Vg equation and the study of the non-conventional
44 A. Bachtold et al. / Physica E 16 (2003) 42 – 46

screening of charge along the one-dimensional nano- 100

tubes [7].
Recently, di/erent groups [8–10] have reported
transconductance measurements that also show the
injection of both p- and n-type carriers by modifying

I (nA)
the gate -eld. This has been obtained with the “tradi- 0
tional” layout where the gate consists of the Si wafer
that is covered by several hundreds of nanometers.
Previously, this layout that provides a weaker capaci-
tive coupling between the gate and nanotube has not symmetric bias
allowed to inject n-type carriers [5,6]. In order to get -100
n-type carriers, these groups have used new methods (a)
-1 0
Vsd (V)
1

such as annealing treatments [9] or the selection of

larger diameter nanotubes [10]. 30

Our nanotube transistors can be classi-ed as

enhancement-mode p-type FETs because the strongest
modulation of the current through the nanotube FET
is possible when a negative gate voltage is applied.
Fig. 2d shows the current versus bias voltage charac- I (nA)
0
teristics. Typical FET-type curves are obtained, with
-nite currents through the transistor when the gate
voltage is more negative than a threshold voltage
which is approximately −1:0 V for the current device. asymmetric bias
In the linear regime at small source–drain voltages, -30
-1 0 1
the current is proportional to Vsd . In the saturation (b) Vsd (V)
regime at higher source–drain voltages, that is, when
Vsd becomes more negative than Vg − Vt , the current Fig. 3. I –Vsd curves of a single nanotube transistor. (a) I –Vsd
through the transistor changes more gradually. From curves under symmetrical bias for Vg = 0:9 V. (b) I –Vsd curves
under asymmetrical bias for Vg = 0:9 V.
the data of Fig. 2 we can extract a transconductance
of our nanotube transistors of 0:3 S, and a lower
limit of the on/o/ ratio of at least 105 . The maximum one-dimensional nature and semi-ballistic transport of
current that the nanotube transistor can tolerate is on semiconducting carbon nanotubes.
the order of 100 nA and the on-resistance is 26 MN Fig. 3 shows the I (Vsd ) curves when the nanotube
for Vsd = −1:3 V and Vg = −1:3 V. A voltage gain of is symmetrically and asymmetrically biased for an-
at least 10 can be achieved. Good contact resistance other sample. For symmetric (asymmetric) bias mea-
has been achieved, as is evident from the minimal surements, the voltages on the Au electrodes are set at
resistance of 80 kN at Vg = −3:5 V in Fig. 2a. −Vsd =2 and Vsd =2 (0 and Vsd ). The curves are dramat-
To facilitate the comparison of the nanotube tran- ically di/erent. For asymmetrically biased nanotubes,
sistors to conventional transistors, the data of Fig. 2d the I (Vsd ) curves show asymmetry with respect to the
were -t to a generic p-type MOSFET model. The polarity of the bias voltage. Diode characteristics are
model describes the current in the linear regime as even obtained for some gate voltage regions (Fig. 3b).
I =−k(1−wVsd )Vsd (2(Vg −Vt )−Vsd ) and the current Current ratios between 1V and –1V have been mea-
in the saturation regime as I =−k(1−wVsd )(Vg −Vt )2 . sured that are larger than 1000. Symmetrical I (Vsd )
These equations were found to approximate the data curves are obtained under symmetrical bias (Fig. 3a).
well for the parameters k = 2:3 × 10−7 A=V2 ; Vt = Similar results have been obtained on tubes gated by
−1 V, and w = 1 V−1 . While this model provides a the Si wafer [11]. It has been suggested that this e/ect
reasonable starting point for modeling our devices, a comes from the electric -eld near the contacts that is
full theoretical description will need to consider the di/erent in both cases.
 A. Bachtold et al. / Physica E 16 (2003) 42 – 46 45

It is important to note that the gain is also di/erent

from the measurements that are symmetric biased to
the one that are asymmetric. The largest gain is ob-
tained for asymmetric biased and for negative volt-
age measurements as in Fig 2d. This corresponds to
curves that are saturating in the current. In the sym-
metric measurements where there are no saturating
currents, lower gains are obtained. However, they are
still larger than one, on the order of 4.
A major point of our paper is that small circuits
combining these nanotube transistors can be used to
make a variety of logic elements. Here we demon-
strate an inverter, a NOR gate and a ring oscillator. All
of these elements are realized using a logic scheme
called resistor-transistor logic. In each of the logic
elements, all nanotube transistors were fabricated on
a same chip (Fig. 4a). A voltage of −1:5 V across the
nanotube was found to be a suitable bias voltage for
logic applications. In all logic circuits described here,
a voltage of 0 V represented a logical 0 and a voltage
of −1:5 V represented a logical 1.
Fig. 4b shows the input–output characteristics of an
inverter constructed from a nanotube transistor and an
o/-chip 100 MN bias resistor. An inverter is a basic
logic element that converts a logical 0 into a logical
1, and a logical 1 into a logical 0. When the input is
a logical 1 (Vin = −1:5 V), the negative gate voltage
pulls holes into the tube giving it a resistance much
lower than the bias resistor. This pulls the output volt-
age to 0 V, representing a logical 0. When the input of
the inverter is a logical 0 (Vin = 0 V), then nanotube
is nonconducting and the output is pulled to −1:5 V,
representing a logical 1. The output voltage of an in-
verter should make a rapid transition from one logic
level to the other as the gate voltage is swept. In this
device, the output voltage changes three times faster
than the input voltage in the transition region indicat-
ing that this particular device has a voltage gain of 3
(other devices showed a gain of up to 6).
A NOR gate can be constructed by simply replacing Fig. 4. Demonstration of 1-, 2-, 3-transistor logic circuits with
the single transistor in the inverter with two transistors carbon nanotube FETs. (a) Height-mode atomic-force-microscope
in parallel (Fig. 4c). The layout of the two transistors image of two nanotube transistors connected by a gold interconnect
on the same chip is shown in Fig. 4a. When either or wire. The arrows indicate the position of the transistors. (b) Output
both of the inputs are a logical 1 (Vin = −1:5 V), at voltage as a function of the input voltage of a nanotube inverter.
Inset, schematic of the electronic circuit. The resistance is 100 MN.
least one of the nanotubes is conducting and the output (c) Output voltage of a nanotubes NOR for the four possible input
is pulled to 0 V (logical 0). The output is a logical 1 states (1,1), (1,0), (0,1), and (0,0). The resistance is 50 MN.
only when both inputs are a logical 0 so that neither (d) Output voltage as a function of time for a nanotube ring
nanotube is conducting. In Fig. 4c, the output voltage oscillator. The three resistances are 100 MN; 100 MN and 2 GN.
46 A. Bachtold et al. / Physica E 16 (2003) 42 – 46

is plotted as a function of the four possible input states microQuidics tools. SchRon et al. [15] also demonstrated
(0,0), (0,1), (1,0), and (1,1), verifying that this circuit an inverter based on small organic molecules. These
indeed operates as a NOR gate. Using variations of di/erent reports have used very di/erent techniques
the device circuitry one can realize any logical gate and molecules to achieve a circuit. This shows that the
(AND, OR, NAND, XOR, etc.) in this way. -eld is progressing rapidly and is very encouraging
A 3-transistor device was realized in the ring oscil- for future advances in molecular electronics.
lator shown in Fig. 4d. This circuit, used to generate
an oscillating AC voltage signal, was built by connect-
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