The latency is the time to transfer the first data word (d0) after the row access strobe. Since each clock cycle is 1/500 MHz = 2 ns, and it takes 1 clock cycle to transfer the first data, the latency is 2 ns.
The bandwidth is the rate at which data can be transferred out once the first data is available. Since each data (d0, d1, d2 etc.) is 64 bits wide, and it takes 1 clock cycle of 2 ns to transfer each data, the bandwidth is 64 bits / 2 ns = 32 Gbps.
The latency is the time to transfer the first data word (d0) after the row access strobe. Since each clock cycle is 1/500 MHz = 2 ns, and it takes 1 clock cycle to transfer the first data, the latency is 2 ns.
The bandwidth is the rate at which data can be transferred out once the first data is available. Since each data (d0, d1, d2 etc.) is 64 bits wide, and it takes 1 clock cycle of 2 ns to transfer each data, the bandwidth is 64 bits / 2 ns = 32 Gbps.
The latency is the time to transfer the first data word (d0) after the row access strobe. Since each clock cycle is 1/500 MHz = 2 ns, and it takes 1 clock cycle to transfer the first data, the latency is 2 ns.
The bandwidth is the rate at which data can be transferred out once the first data is available. Since each data (d0, d1, d2 etc.) is 64 bits wide, and it takes 1 clock cycle of 2 ns to transfer each data, the bandwidth is 64 bits / 2 ns = 32 Gbps.
The latency is the time to transfer the first data word (d0) after the row access strobe. Since each clock cycle is 1/500 MHz = 2 ns, and it takes 1 clock cycle to transfer the first data, the latency is 2 ns.
The bandwidth is the rate at which data can be transferred out once the first data is available. Since each data (d0, d1, d2 etc.) is 64 bits wide, and it takes 1 clock cycle of 2 ns to transfer each data, the bandwidth is 64 bits / 2 ns = 32 Gbps.
• Maximum size of memory is determined by addressing scheme
E.g. 16-bit addresses can only address 216 = 65536 memory locations
• Most machines are byte-addressable
• each memory address location refers to a byte • Most machines retrieve/store data in words • Common abbreviations • 1k ≈ 210 (kilo) • 1M ≈ 220 (Mega) • 1G ≈ 230 (Giga) • 1T ≈ 240 (Tera)
8/24 Simplified View Data transfer takes place through • MAR: memory address register • MDR: memory data register
Processor Memory k-bit address bus MAR n -bit data bus Up to 2 k addressable MDR locations
Word length = n bits
Several addressable Control lines locations (bytes) are grouped into a word ( R / W , MFC, etc.)
9/24 Big Picture
Processor usually runs much faster than main memory:
• Small memories are fast, large memories are slow. • Use a cache memory to store data in the processor that is likely to be used.
Main memory is limited:
• Use virtual memory to increase the apparent size of physical memory by moving unused sections of memory to disk (automatically). • A translation between virtual and physical addresses is done by a memory management unit (MMU) • To be discussed in later lectures
10/24 Characteristics of the Memory Hierarchy
Processor Inclusive– 4-8 bytes (word) what is in L1$ is a subset of Increasing L1$ what is in L2$ distance 8-32 bytes (block) is a subset of from the L2$ what is in MM processor that is a 1 to 4 blocks in access subset of is in time Main Memory SM 1,024+ bytes (disk sector = page)
Secondary Memory
(Relative) size of the memory at each level
11/24 Memory Hierarchy: Why Does it Work?
Temporal Locality (locality in time)
If a memory location is referenced then it will tend to be referenced again soon
• Keep most recently accessed data items closer to the processor
12/24 Memory Hierarchy: Why Does it Work?
Temporal Locality (locality in time)
If a memory location is referenced then it will tend to be referenced again soon
• Keep most recently accessed data items closer to the processor
Spatial Locality (locality in space)
If a memory location is referenced, the locations with nearby addresses will tend to be referenced soon
• Move blocks consisting of contiguous words closer to the processor
12/24 Memory Hierarchy
Taking advantage of the principle of locality:
• Present the user with as much memory as is available in the cheapest technology. • Provide access at the speed offered by the fastest technology
Processor
Control Tertiary Secondary Storage Storage (Tape) Second Main (Disk) On-Chip Registers
Level Memory Cache
Datapath Cache (DRAM)
(SRAM)
Speed: ~1 ns Tens ns Hundreds ns – 1 us Tens ms Tens sec
Property: comparable access time for any memory locations
Block (or line)
the minimum unit of information that is present (or not) in a cache
15/24 Terminology
• Hit Rate: the fraction of memory accesses found in a level of the memory hierarchy • Miss Rate: the fraction of memory accesses not found in a level of the memory hierarchy, i.e. 1 - (Hit Rate)
Hit Time Time to access the block + Time to determine hit/miss
Miss Penalty Time to replace a block in that level with the corresponding block from a lower level
Hit Time << Miss Penalty
16/24 Bandwidth v.s. Latency
Example • Mary acts FAST but she’s always LATE. • Peter is always PUNCTUAL but he is SLOW.
17/24 Bandwidth v.s. Latency
Example • Mary acts FAST but she’s always LATE. • Peter is always PUNCTUAL but he is SLOW.
Bandwidth: • talking about the “number of bits/bytes per second” when transferring a block of data steadily. Latency: • amount of time to transfer the first word of a block after issuing the access signal. • Usually measure in “number of clock cycles” or in ns/µs.
17/24 Question: Suppose the clock rate is 500 MHz. What is the latency and what is the bandwidth, assuming that each data is 64 bits?
