SN74CBT16233

16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER

SCDS010K – MAY 1995 – REVISED NOVEMBER 2001

D Member of the Texas Instruments DGG, DGV, OR DL PACKAGE

Widebus  Family (TOP VIEW)

D 5-Ω Switch Connection Between Two Ports 1A 1 56 1B1

D TTL-Compatible Input Levels 2B1 2 55 1B2
2B2 3 54 2A
description 3A 4 53 3B1
4B1 5 52 3B2
The SN74CBT16233 is a 16-bit 1-of-2 FET
multiplexer/demultiplexer used in applications in 4B2 6 51 4A
which two separate data paths must be 5A 7 50 5B1
multiplexed onto, or demultiplexed from, a single 6B1 8 49 5B2
path. This device can be used for memory 6B2 9 48 6A
interleaving, where two different banks of memory 7A 10 47 7B1
need to be addressed simultaneously. The device 8B1 11 46 7B2
can be used as two 8-bit to 16-bit multiplexers or 8B2 12 45 8A
as one 16-bit to 32-bit multiplexer. GND 13 44 GND
VCC 14 43 VCC
Two select (SEL1 and SEL2) inputs control the
9A 15 42 9B1
data flow. When the TEST inputs are asserted, the
10B1 16 41 9B2
A port is connected to both the B1 and the B2
10B2 17 40 10A
ports. SEL1, SEL2, and the TEST inputs can be
11A 18 39 11B1
driven with a 5-V CMOS, a 5-V TTL, or a
12B1 19 38 11B2
low-voltage TTL driver.
12B2 20 37 12A
This device is designed so it does not have 13A 21 36 13B1
through current when switching directions. 14B1 22 35 13B2
14B2 23 34 14A
15A 24 33 15B1
16B1 25 32 15B2
16B2 26 31 16A
TEST1 27 30 SEL1
TEST2 28 29 SEL2

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN74CBT16233DL
SSOP – DL CBT16233
Tape and reel SN74CBT16233DLR
–40°C
40°C to 85°C
TSSOP – DGG Tape and reel SN74CBT16233DGGR CBT16233
TVSOP – DGV Tape and reel SN74CBT16233DGVR
CY233
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Copyright  2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001

FUNCTION TABLE
(each multiplexer/demultiplexer)
INPUTS
FUNCTION
SEL TEST
L L A = B1
H L A = B2
X H A = B1 and A = B2

logic diagram (positive logic)

1 56 15 42
1A 1B1 9A 9B1

55 41
1B2 9B2

45 11 31 25
8A 8B1 16A 16B1

12 26
8B2 16B2

30 29
SEL1 SEL2

27 28
TEST1 TEST2

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001

recommended operating conditions (see Note 3)

MIN MAX UNIT
VCC Supply voltage 4.75 5.25 V
VIH High-level control input voltage 2 V
VIL Low-level control input voltage 0.8 V
TA Operating free-air temperature –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIK VCC = 4.75 V, II = –18 mA –1.2 V
VCC = 0, VI = 5.25 V 10 µA
II
VCC = 5.25 V, VI = 5.25 V or GND ±1 µA
ICC VCC = 5.25 V, IO = 0, VI = VCC or GND 3 µA
∆ICC‡ Control inputs VCC = 5.25 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA
Ci Control inputs VI = 3 V or 0 4.5 pF
Cio(OFF) VO = 3 V or 0 4 pF
II = 64 mA 5 7
VI = 0
ron§ VCC = 4.75 V II = 30 mA 5 7 Ω
VI = 2.4 V, II = 15 mA 7 12
† All typical values are at VCC = 5 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
§ Measured by the voltage drop between A and B terminals at the indicated current through the switch. On-state resistance is determined by the
lower of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
tpd¶ A or B B or A 0.25 ns
tpd SEL A 1.6 5.3 ns
ten TEST or SEL B 1.3 5.2 ns
tdis TEST or SEL B 1 5.3 ns
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN74CBT16233
16-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
SCDS010K – MAY 1995 – REVISED NOVEMBER 2001

PARAMETER MEASUREMENT INFORMATION

7V TEST S1

500 Ω S1 Open tpd Open

From Output tPLZ/tPZL 7V
Under Test GND
tPHZ/tPZH Open
CL = 50 pF
500 Ω
(see Note A)

3V
Output
1.5 V 1.5 V
LOAD CIRCUIT Control
0V

tPZL tPLZ
Output 3.5 V
3V Waveform 1
Input S1 at 7 V 1.5 V VOL + 0.3 V
1.5 V 1.5 V
0V (see Note B) VOL
tPZH tPHZ
tPLH tPHL
Output VOH
VOH Waveform 2 VOH – 0.3 V
Output S1 at Open 1.5 V
1.5 V 1.5 V
VOL (see Note B) 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM
www.ti.com 23-Sep-2006

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
74CBT16233DGGRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74CBT16233DGVRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74CBT16233DGVRG4 ACTIVE TVSOP DGV 56 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16233DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16233DGVR ACTIVE TVSOP DGV 56 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16233DL ACTIVE SSOP DL 56 20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16233DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16233DLR ACTIVE SSOP DL 56 1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16233DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

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 MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635) 0.0135 (0,343)

0.005 (0,13) M
0.008 (0,203)

48 25
0.010 (0,25)
0.005 (0,13)

0.299 (7,59)
0.291 (7,39)

0.420 (10,67)
0.395 (10,03) Gage Plane

0.010 (0,25)

1 24 0°–ā8°
0.040 (1,02)
A
0.020 (0,51)

Seating Plane

0.004 (0,10)
0.110 (2,79) MAX 0.008 (0,20) MIN

PINS **
28 48 56
DIM

0.380 0.630 0.730

A MAX
(9,65) (16,00) (18,54)

0.370 0.620 0.720

A MIN
(9,40) (15,75) (18,29)
4040048 / E 12/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27
0,50 0,08 M
0,17
48 25

6,20 8,30
6,00 7,90 0,15 NOM

Gage Plane

0,25
1 24
0°– 8°
A 0,75
0,50

Seating Plane
0,15
1,20 MAX 0,10
0,05

PINS **
48 56 64
DIM

A MAX 12,60 14,10 17,10

A MIN 12,40 13,90 16,90

4040078 / F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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