SN54ACT16244, 74ACT16244

16-BIT BUFFERS/LINE DRIVERS

WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996

D Members of the Texas Instruments SN54ACT16244 . . . WD PACKAGE

Widebus Family 74ACT16244 . . . DGG OR DL PACKAGE
(TOP VIEW)
D Inputs Are TTL-Voltage Compatible
D 3-State Outputs Drive Bus Lines or Buffer 1OE 1 48 2OE
Memory Address Registers 1Y1 2 47 1A1
D Flow-Through Architecture Optimizes 1Y2 3 46 1A2
PCB Layout GND 4 45 GND
D Distributed VCC and GND Pin 1Y3 5 44 1A3
Configurations Minimize High-Speed 1Y4 6 43 1A4
Switching Noise VCC 7 42 VCC

D EPIC  (Enhanced-Performance Implanted

2Y1
2Y2
8
9
41
40
2A1
2A2
CMOS) 1-mm Process
GND GND
D
10 39
500-mA Typical Latch-Up Immunity at 2Y3 11 38 2A3
125°C 2Y4 12 37 2A4
D Package Options Include Plastic Shrink 3Y1 13 36 3A1
Small-Outline (DL) and Thin Shrink 3Y2 14 35 3A2
Small-Outline (DGG) Packages, and 380-mil GND 15 34 GND
Fine-Pitch Ceramic Flat (WD) Packages 3Y3 16 33 3A3
Using 25-mil Center-to-Center Pin Spacings 3Y4 17 32 3A4
VCC 18 31 VCC
description 4Y1 19 30 4A1
The SN54ACT16244 and 74ACT16244 are 16-bit 4Y2 20 29 4A2
buffers/line drivers designed specifically to GND 21 28 GND
improve both the performance and density of 4Y3 22 27 4A3
3-state memory address drivers, clock drivers, 4Y4 23 26 4A4
and bus-oriented receivers and transmitters. 4OE 24 25 3OE
They can be used as four 4-bit buffers, two 8-bit
buffers, or one 16-bit buffer. The devices provide
true outputs and symmetrical OE (active-low)
output-enable inputs.
The 74ACT16244 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16244 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16244 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE
(each driver)
INPUTS OUTPUT
OE A Y

L H H
L L L
H X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Copyright  1996, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996

logic symbol†

1
1OE EN1
48
2OE EN2
25
3OE EN3
24
4OE EN4

47 2
1A1 1 1 1Y1
46 3
1A2 1Y2
44 5
1A3 1Y3
43 6
1A4 1Y4
41 8
2A1 1 2 2Y1
40 9
2A2 2Y2
38 11
2A3 2Y3
37 12
2A4 2Y4
36 13
3A1 1 3 3Y1
35 14
3A2 3Y2
33 16
3A3 3Y3
32 17
3A4 3Y4
30 19
4A1 1 4 4Y1
29 20
4A2 4Y2
27 22
4A3 4Y3
26 23
4A4 4Y4

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996

logic diagram (positive logic)

1 25
1OE 3OE

47 2 36 13
1A1 1Y1 3A1 3Y1

46 3 35 14
1A2 1Y2 3A2 3Y2

44 5 33 16
1A3 1Y3 3A3 3Y3

43 6 32 17
1A4 1Y4 3A4 3Y4

48 24
2OE 4OE

41 8 30 19
2A1 2Y1 4A1 4Y1

40 9 29 20
2A2 2Y2 4A2 4Y2

38 11 27 22
2A3 2Y3 4A3 4Y3

37 12 26 23
2A4 2Y4 4A4 4Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . . . . . . . 0.85 W
DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996

recommended operating conditions (see Note 3)

SN54ACT16244 74ACT16244
UNIT
MIN MAX MIN MAX
VCC Supply voltage (see Note 4) 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
IOH High-level output current –24 –24 mA
IOL Low-level output current 24 24 mA
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
TA Operating free-air temperature –55 125 –40 85 °C
NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 k W or greater to prevent them from floating.
4. All VCC and GND pins must be connected to the proper voltage supply.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54ACT16244 74ACT16244
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
4.5 V 4.4 4.4 4.4
IOH = –50
50 A m
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.7 3.8
VOH IOH = –24
24 mA V
5.5 V 4.94 4.7 4.8
IOH = –50 mA{ 5.5 V 3.85
IOH = –75 mA{ 5.5 V 3.85
4.5 V 0.1 0.1 0.1
IOL = 50 Am
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
VOL IOL = 24 mA V
5.5 V 0.36 0.5 0.44
IOL = 50 mA{ 5.5 V 1.65
IOL = 75 mA{ 5.5 V 1.65
II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 mA
IOZ VO = VCC or GND 5.5 V ±0.5 ±10 ±5 mA
ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 mA
One input at 3.4 V,
∆ICC} 5.5 V 0.9 1 1 mA
Other inputs at GND or VCC
Ci VI = VCC or GND 5V 4.5 pF
Co VO = VCC or GND 5V 13.5 pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ACT16244
FROM TO
PARAMETER TA = 25°C UNIT
(INPUT) (OUTPUT) MIN MAX
MIN TYP MAX
tPLH 4 6.5 8.5 3 10.3
A Y ns
tPHL 3.4 6.3 8.7 3.4 10.1
tPZH 3 5.8 8.1 3 10.5
OE Y ns
tPZL 3.7 6.7 9.3 3.7 11
tPHZ 5.4 8.1 11.5 5.4 13
OE Y ns
tPLZ 5 7.5 9.5 5 10.9

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
74ACT16244
FROM TO
PARAMETER TA = 25°C UNIT
(INPUT) (OUTPUT) MIN MAX
MIN TYP MAX
tPLH 4 6.5 8.5 4 9.4
A Y ns
tPHL 3.4 6.3 8.7 3.4 9.5
tPZH 3 5.8 8.1 3 8.9
OE Y ns
tPZL 3.7 6.7 9.3 3.7 10.3
tPHZ 5.4 8.1 10.3 5.4 11.3
OE Y ns
tPLZ 5 7.5 9.5 5 10.3

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Outputs enabled 39
Cpd
d Power dissipation capacitance CL = 50 pF,
pF f = 1 MHz pF
Outputs disabled 11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ACT16244, 74ACT16244
16-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCAS116B – MARCH 1990 – REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION

2 × VCC TEST S1
500 Ω S1 tPLH/tPHL Open
Open
From Output tPLZ/tPZL 2 × VCC
Under Test GND tPHZ/tPZH GND
CL = 50 pF 500 Ω
(see Note A)

LOAD CIRCUIT Output 3V

Control
1.5 V 1.5 V
(low-level
0V
enabling)
tPZL

[ VCC
3V tPLZ
Output
Input 1.5 V 1.5 V Waveform 1 50% VCC
0V S1 at 2 × VCC 20% VCC
VOL
tPLH (see Note B)
tPHL tPHZ
tPZH
VOH Output
VOH
50% VCC 50% VCC Waveform 2 80% VCC
Output 50% VCC
VOL
S1 at GND
(see Note B) [0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9202201MXA ACTIVE CFP WD 48 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9202201MX
& Green A
SNJ54ACT16244W
D
74ACT16244DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-1-260C-UNLIM ACT16244

74ACT16244DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244

74ACT16244DGGRG4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244

74ACT16244DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244

74ACT16244DLG4 ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244

74ACT16244DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244

74ACT16244DLRG4 ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT16244

SNJ54ACT16244WD ACTIVE CFP WD 48 1 Non-RoHS SNPB N / A for Pkg Type 5962-9202201MX

& Green A
SNJ54ACT16244W
D

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Aug-2021

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
74ACT16244DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
74ACT16244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74ACT16244DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
74ACT16244DLR SSOP DL 48 1000 367.0 367.0 55.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
74ACT16244DGG DGG TSSOP 48 40 530 11.89 3600 4.9
74ACT16244DL DL SSOP 48 25 473.7 14.24 5110 7.87
74ACT16244DLG4 DL SSOP 48 25 473.7 14.24 5110 7.87

Pack Materials-Page 3
 MECHANICAL DATA

MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997

WD (R-GDFP-F**) CERAMIC DUAL FLATPACK

48 LEADS SHOWN

0.120 (3,05) 0.009 (0,23)

0.075 (1,91) 0.004 (0,10)

1.130 (28,70)
0.870 (22,10)
0.370 (9,40) 0.390 (9,91) 0.370 (9,40)
0.250 (6,35) 0.370 (9,40) 0.250 (6,35)

1 48

0.025 (0,635)

0.014 (0,36)
0.008 (0,20)

24 25

NO. OF
48 56
LEADS**
0.640 0.740
A MAX
(16,26) (18,80)
0.610 0.710
A MIN
(15,49) (18,03)

4040176 / D 10/97

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA
GDFP1-F56 and JEDEC MO -146AB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
DGG0048A SCALE 1.350
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

C
8.3 SEATING PLANE
TYP
7.9
PIN 1 ID 0.1 C
A
AREA
46X 0.5
48
1

12.6 2X
12.4 11.5
NOTE 3

24
25
0.27
48X
6.2 0.17 1.2
B
6.0 0.08 C A B 1.0

(0.15) TYP

0.25
SEE DETAIL A GAGE PLANE

0.15
0 -8 0.75 0.05
0.50

DETAIL A
TYPICAL

4214859/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGG0048A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

48X (1.5) SYMM

1
48

48X (0.3)

46X (0.5)

(R0.05) SYMM
TYP

24 25

(7.5)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214859/B 11/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGG0048A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

48X (1.5) SYMM

1
48

48X (0.3)

46X (0.5)

SYMM
(R0.05) TYP

24 25

(7.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4214859/B 11/2020
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27
0,50 0,08 M
0,17
48 25

6,20 8,30
6,00 7,90 0,15 NOM

Gage Plane

0,25
1 24
0°– 8°
A 0,75
0,50

Seating Plane
0,15
1,20 MAX 0,10
0,05

PINS **
48 56 64
DIM

A MAX 12,60 14,10 17,10

A MIN 12,40 13,90 16,90

4040078 / F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated