EE303: Digital System Design

Memory

Kyeongha Kwon
School of EE, KAIST

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 Memory Unit
 A collection of cells capable of storing a large quantity of binary information
− For storage, binary information is transferred to a memory unit
− For processing, binary information is retrieved from a memory unit and transferred to
registers in the processing unit
− Intermediate and final results obtained in the processing unit are transferred back to
be stored in memory

Binary data

A collection of cells
Processing Unit Data for storage storing a large
Memory
(Comb. logic + Registers) quantity of binary
information
Data for processing

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 A Word in Memory
 A memory unit stores binary information in groups of bits called words
 Word
− A group of bits that go in and out of memory as a unit
− A group of 1’s and 0’s that represents some binary‐coded information

 Byte
− A group of 8 bits Word size: 1 byte
Memory
e.g.1 byte = 8 bits 8 bits of data
16-bit word = 2 bytes
32-bit word = 4 bytes

 Capacity = the total number of bytes that the memory can store

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 2 Types of Memories
 Random‐access memory (RAM)
− Volatile memory
− Information is temporarily stored
− Read/write operation
− Working area of computer

 Read‐only memory (ROM)

− Non-volatile memory
− Information is permanently stored
− Read only
− Start-up memory of the computer
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 Random Access Memory (RAM)
 Supports read/write a word of data from/to a random, desired location
 RAM interface: input/output, address selection, control
 E.g. Assume 2k n-bit words of capacity
− n–bit data input/output lines to write/read 1 word
− k–bit address lines to select one of the 2k words
− Enable is asserted when either read/write operation is required
− Read/Write determines the direction of the data transfer

 Specified by #words and #bits in each word Enable

Read/Write
− Common subscripts:
Kilo (K): 210 / Mega (M): 220 / Giga (G):230
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 Random Access Memory (RAM)
 Address lines select one particular word
1K (=210) words
− k-bit address to distinguish 2k words, 16 bits per word
ranging from 0 to 2k-1.
− #address bits is independent of #bits in each word

 Example
− A memory with 1K (=210) words of 16 bits → 2K bytes
− 10-bit address ranging from 0 to 1023 required

k-bit address
Memory
2k words
10-bit address 210-1
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 RAM Write Operation
 Steps to write a word
1. Apply the binary address of the desired word to the address lines
2. Apply the data bits that should be stored in memory to data input lines
3. Assert Enable and clear Read/Write control signals to 0, thereby enabling the write mode

1 Enable

0 Read/Write

Write mode (Read/Write = 0);

Read mode (Read/Write = 1) Not used
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 RAM Write Operation
 A CPU controls memory operation considering its timing requirements
− Cycle time: Time needed to write to memory
 e.g. Suppose that a CPU runs with 50 MHz (20ns) and the cycle time is 50ns.
− At least 2.5, and possibly 3 50MHz clock cycles are required (T1, T2, T3) for each write operation
For a CPU with TCLK = 20ns, and memory with 50 ns cycle time
③ Write operation completed

① Address, data should be

ready before enable/write
not to corrupt other address ② Stay active at least
for the cycle time (50ns)

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 RAM Read Operation
 Steps to read a word
1. Apply the binary address of the designed word to the address lines
2. Assert Enable and Read/Write control signals to enable the read mode
3. The memory unit will apply the bits from the word to the data output lines
Not used

1 Enable

1 Read/Write

Write mode (Read/Write = 0);

Read mode (Read/Write = 1)
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 RAM Read Operation
 Access time: Time needed to read from memory
 E.g. Suppose that a CPU runs with 50 MHz (20ns) and the access time is 50ns.
− At least 2.5, and possibly 3 50MHz clock cycles are required (T1, T2, T3) for each read operation
− Data is valid on data output following access time

Stay active at least

for the access time (50ns)

Valid data come within the access time 10

 Two Famous Types of RAMs
 Static random access memory (SRAM)
- Operates like a collection of latches
- The stored information remain in the memory as long as power is on
- Generally expensive but very fast (short access / cycle times) than DRAM
- Used as on-chip cache memory of CPUs

 Dynamic random access memory (DRAM)

- Stores the data in the form of electric charges on capacitors
- Requires data to be rewritten (refreshing), otherwise data is lost
- Generally cheaper but has longer access / cycle times than SRAM
- Used as main memory in computer systems
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 SRAM Write Operations
 Typical SRAM write operation examples
− Read, write access times are typically within a single clock cycle
− For write: Enable, address and input data are given at the same clock cycle (T1, T2)

T1 T2 T3 T4 T5

1 1

D_A is stored to A D_B is stored to B

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 SRAM Read Operations
 Typical SRAM operation examples
− Read, write access times are typically within a single clock cycle
− For read: Output data is given at the next clock cycle of enable and address (T3T4, T4T5)

T1 T2 T3 T4 T5

Read A Read B

D_A is available D_B is available 13

 SRAM Modeling in Verilog HDL
 Memory words as an array of registers module SRAM (
input wire Clk,
− Use the address input to select one of the input wire En,
registers (words). input wire RWn, // 0: Write, 1: Read
input wire [9:0] Addr, // 10-bit address
 For the memory with 1024 words of 32 bits input wire [31:0] Din, // 32-bit input data word
output logic [31:0] Dout // 32-bit output data word
− 10-bit address );
#bits in a word #words in memory
− 32-bit input and output data logic [31:0] word_array [0:1023];
(memory width) (memory depth)
always_ff @ (posedge Clk) begin
if (En & !RWn) begin
Memory write operation
word_array[Addr] <= Din;
end
end
always_ff @ (posedge Clk) begin
Memory read operation if (En & RWn) begin
Dout <= word_array[Addr];
end
end
endmodule
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 Memory Storage Cell
 Memory consists of binary storage cells (BC)
− Each cell uses an S-R latch to store a bit of information
− The read/write input determines the operation of the cell when it is selected.
- Read/Write enables either read or write, not both
- Read (Read/Write =1), Write (Read/Write=0)

Binary cells (BC)

0 Input

0 Input`

1 0

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 RAM Overall Architecture
 A RAM with a capacity of 16 bits (4 words of 4bits each)
[4 words x 4 bits RAM]
− One word line = a row of bits 4 words
Write
 Memory with 2m words needs m address lines
− Address inputs given to a decoder 4 bits

 Memory enable
− EN = 0; No word selected
− EN = 1; Select only one-word line

Read

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 2-Dimensional Address Decoding
 Large-capacity RAMs have thousands of words
 A memory with 2k words (n bits per word) requires k address lines that go into a
k x 2k decoder
− Address decoding can be very costly
− E.g. 1024 words need a 10-to-1024 decoder
• 10-to-1024 decoder requires 1024 AND gates (10 inputs per gate)

 # gates and #inputs per gate can be reduced

− by 2‐dimensional address decoding!!

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 2-Dimensional Address Decoding
 Two-dimensional selection
− Divide into row selection and column selection

 Two k/2‐input decoders instead of one k‐input decoder

− One decoder performs the row selection
− The other performs the column selection Each intersection
represents a word
 e.g. One 10-to-1024 decoder  Two 5-to-32 decoders
− 1,024 10-input AND gates  2 x 32 5-input AND gates
− 5 MSBs of address (X) go to row decoder
− 5 LSBs of address (Y) go to column decoder
A word is selected by the coincidence
− If address is 404 (0110010100),
btw 1 of 32 rows and 1 of 32 columns,
 X = 01100 (12) & Y = 10100 (20) for a total of 1,024 words.

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 Read-Only Memory (ROM)
 Nonvolatile memory
− Allows permanent storage of binary information
- Contains the programming that enables a computer to start up or
regenerate each time it is turned on
- Only read operation (normally, no write operation  no data input lines)
- Internal organization is similar to RAM

Depth (= #words)

Width
(= #bits per word)
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 Read-Only Memory (ROM)
 Example: 32 x 8 ROM (32 words, 8 bit each)
− 2k x n ROM has k x 2k decoder + n 2k-input OR gates
2k 32 X 8 = 256 interconnections

k Each intersection could be

programmable if there’s a
switch (connected or not)

Address decoder
n OR gates
8 x 32-input OR
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 Programmable ROM (PROM)
 Fuse: normally connects two points, but can be blown (= open) by applying high voltage
− Once blown, it can’t be restored ① 5 bits
Once programmed,
Can’t be changed
m0=A’B’C’ Connected Open
m1=A’B’C
③ 8 X 5 crosspoints
m2=A’BC’
A
m3=A’BC
3 to 8
B
decoder m4=AB’C’

C m5=AB’C

m6=ABC’
② 3-bit address
m7=ABC

① 23 words

② 5 OR gates (8-input per gate) F0 F1 F2 F3 F4 21

 Programming PROM
 Programming ROM by blowing fuse links in accordance with a truth table
− 0: absence of connection, 1: connected (‘x’)
 When read, only a single word line is set to 1 while other words are 0
− Value 1 will be propagated through connected nodes to output OR gates

Each address stores a word of 8 bits

32 address

5 inputs 0: absence of connection

x : connected
1: connected (‘x’) None: not connected
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 Programming PROM (Cont’d)
 For inputs of 00011 (binary 3), all outputs of the decoder are 0 except for output 3.
− Logic 1 at decoder output 3 propagates through the connections to the OR gate outputs of A7, A5, A4, A1.
• The other four outputs remain at 0.
− As a result, the stored word 10110010 is applied to the eight data outputs. x : connected
None: not connected

②1

① ROM inputs : 00011

③1 1 1 1
④ Outputs : 10110010 23
 PROM Truth Table
 A ROM can be used to implement a truth table
- k inputs, n outputs
- Each minterm of each function can be specified

A B C F0 F1 F 2 F 3 F 4
A
3 Inputs ROM 0 0 0 0 1 0 1 0
B 8 words
Lines 0 0 1 1 1 1 1 0
C x 5 bits
0 1 0 0 0 0 1 1
0 1 1 1 1 1 0 1
1 0 0 0 1 0 1 0
F0 F 1 F 2 F 3 F 4 1 0 1 0 1 1 1 1
1 1 0 1 0 1 0 1
1 1 1 1 1 0 1 0
5 Outputs Lines
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 Summary
 Memories provide storage for computers
- Memories are organized in words
- Each word has multiple bits and is selected by input address

 RAM (Random Access Memory)

- Stores data in latches (SRAM) or capacitors (DRAM)
- SRAM is faster but more expensive compared to DRAM
- Consists of bit storage cells and 2-dimensional address decoder logic

 ROM (Read-Only Memory)

- Provides stable storage for data, no overwrite is possible once programmed
- Useful to implement a truth table (i.e., a pre-determined logic function)
- Consists of address decoder logic and crosspoint switches (fuse)

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 Notice
 Additional tutoring?
− Email to TA in charge of tutoring on Chapter 7
− Sara Kim (김사라, sara@kaist.ac.kr)

− Namhoon Kim (김남훈, namwide@kaist.ac.kr)

 Questions? CLASSUM, KLMS Q&A board

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