17 Apr 2023 04:43:47 - Mosfet UC3843 1.0.

sm
CURRENT MODE BUCK BOOST DESIGN DATA and UC3843 -
SEPIC Converter Design Procedure

We are going to use the TL494 to design a SEPIC converter that converts and input voltage of 12V-20V to an output voltage of
5V-30V supplying a load of 5A 150W with a switching frequency of 100kHz. The outline schematic is shown in FIG. 1

Vin_min 12 V VD 0.5 V

Vin_max 20 V

Vout_min 5V

Vout_max 30 V

Iout_max 5A

η 95 %
Assuming 95% efficiency we know the output power is:
Pout_max Vout_max Iout_max Pout_max 150 W

Pout_max Pin_max
Pin_max Pin_max 157.8947 W Iin_max 13.1579 A
η Vin_min

Vout_max
Rload_min Rload_min 6Ω
Iout_max

The duty cycle of the converter when operating in continuous conduction mode is given by
Vout_min VD
Dmin Dmin 21.5686 %
Vout_min VD Vin_max

Vout_max VD
Dmax Dmax 71.7647 %
Vout_max VD Vin_min

Operation Frequency Single-ended applications:

RT 8.2 kΩ
CT 2.2 nF

1.8 Dmax
fsw 99.7783 kHz this equates to a FET ON time of T
RT CT on 7192.4183 ns
fsw

At this point it is worth checking that we are not violating the minimum ON time of the controller
1
FET ON time IRFZ44N (60ns) < Controller ON time (200ns) << Ton 7.1924 μs Ton 2.8298 μs
fsw

Inductor Choice
To design the SEPIC regulator we need to define the maximum allowed ripple in the inductors. A good rule of thumb is to use
20% to 40% of the input current. Assuming the allowed ripple through both inductors is 40% we arrive at the following
expression:

ΔIL 40 % Iin_max ΔIL 5.2632 A

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Average input current: Individual inductors

Vin_min Dmax
L1 L2 L1 16.3987 μH
ΔIL fsw

If inductors L1 and L2 are coupled inductors, the value of the inductance required is half of what would be needed should there
be two separate inductors. Therefore, for coupled inductors the value of inductance required is given by:

Vin_min Dmax
L1couple L2couple L1couple 8.1994 μH
2 ΔIL fsw

Since we have calculated a desired (individual) inductance of 20uH, if we use a coupled inductor we need the inductance of each coil to be
10uH. A coupled inductor often works out smaller in size than 2 separate inductors. Also, note the winding phase of the transformer. A useful
way to remember the phasing of the SEPIC is to consider removing the coupling cap - the SEPIC then becomes a flyback converter and indeed
the circuit operation of a coupled inductor based SEPIC and a flyback are very similar.

Maximum inductor peak current is for minimum input voltage:

Pout_max Vin_min Dmax ΔIL

IL1_peak or IL1_peak Iin_max IL1_peak 15.7895 A
Vin_min η 2 L1 fsw 2
Must make sure that the inductor never
saturates.
ΔIL
IL2_peak Iout_max IL2_peak 7.6316 A
2
MOSFET Choice
The MOSFET needs to be able to handle the peak current from both inductors so in this design a drain source current rating (Id)
of IL1_peak IL2_peak 23.4211 A is more than sufficient. The Drain–Source voltage rating (Vds) needs to be in excess of the
(Vin + Vout + Vdiode) Vin_max Vout_max 0.4 V 50.4 V .
The Gate-Source turn on voltage of the MOSFET (Vgs) needs to be less than the input voltage, to ensure that the Gate drive
voltage can actually activate the MOSFET. Logic level MOSFETs have a low turn on voltage, are widely available and usually
perfect for low voltage dc/dc converters.

IFET_peak IL1_peak IL2_peak IFET_peak 23.4211 A

Iin_max
IFET_rms IFET_rms 15.5321 A
Dmax

Diode Selection
To ensure proper operation and avoid damaging the diode,the diode selected must be able to withstand reverse voltages
equal to:

VR Vin_max Vout_max VR 50 V

The peak current through the diode is equal to the peak current of transistor IFET_peak 23.4211 A .

Coupling Capacitor Selection

The coupling capacitor must be able to handle voltages equal to: Vin_max.
ΔVcp 2 % Vin_max 400 mV - The peak−to−peak voltage across the capacitor.
if IL1_peak IL2_peak
Iout_max Dmax max_ILpeak IL1_peak
Ccp Ccp 89.9052 μF
ΔVcp fsw else
max_ILpeak IL2_peak
It is recommended to use a ceramic capacitor to keep the ESR losses as small as possible.

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ΔVcp
ESRcp ESRcp 25.3333 mΩ
max_ILpeak

Output Capacitor Choice

The ripple caused by the discharge of the output capacitor while the inductor is charging is dictated by:
ΔVout 2 % Vout_max 600 mV

Iout_max Dmax
Cout Cout 59.9368 μF
ΔVout fsw

ΔVout
ESRout ESRout 25.618 mΩ
IL1_peak IL2_peak

Input Capacitor
The input capacitor sees moderately low RMS current thanks to the input inductor. The RMS current in the input capacitor is
given by:
ΔIL
ICin_rms 1.5193 A
12

UC3843 PARAMETERS
Transistor INRFZ44N
tr 80 ns Qt 63 nC VG 12 V Rout_DriverIC 5Ω
Qt
IG IG 0.7875 A
tr

VG
RG Rout_DriverIC RG 10.2381 Ω 2
IG PRG IG RG 6.3492 W

Transistor Drive
VCC 12 V Vout_UC3843 13 V

IC2 IG 0.7875 A choose -> BD139, BD140

IC2
for VCE2 0.21 V must be IB2 78.75 mA ---> IC1 IB2 78.75 mA choose -> 2N2222
10
IC1
IB1 7.875 mA ---> VCE1 0.07 V
10

VCC VCE1
RC RC 151.4921 Ω
IC1

Vout_UC3843 VCE1
RB RB 1641.9048 Ω
IB1

Rsense Calculation
V
RCSF 1
ΔIL
IFET_peak RCSF 38.3838 mΩ
2

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Feedback Resistor Calculator
Current-mode Control
Vref 2.5 V VEA_max 6 V Icomp_src 0.5 mA Rd 4.7 kΩ Rifix 4.7 kΩ

Output Voltage Feedback and Compensation

The E/A output will source 0.5 mA and sink 2 mA. A lower limit for RF is given by:
VEA_max Vref
RF_min RF_min 7 kΩ
Icomp_src
________________________________________________________________
A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance
contribute a left-half plane zero,ωESRz, to the power stage, and the frequency of this zero,
fESRz, are calculated with
1
fESRz fESRz 103.6529 kHz
2 π ESRout Cout

Choosing Rf 56 kΩ , the required value of Cf is determined using:

1
Cf Cf 27.4189 pF
2 π fESRz Rf

Rf Rf Dutycycle Control
Ri Ri Ri 28 kΩ if Ri 50 kΩ
2 2
____________________________________________________________

E/A input bias current (2 µA max) flows through Ri, resulting in a DC error in output
voltage (Vo) given by : ΔV 2 μA Ri 100 mV
o_max
Vout_min Vref Vout_max Vref
IRi_max 531.9149 μA IRi_min 502.7422 μA
Rifix Rifix Ri

IRi_min 200 2 μA 1
Ponteciometer Range voltage Test

if Rpot 0 kΩ Rdvar Rd Rpot 4.7 kΩ Rivar Ri Rpot Rifix 54.7 kΩ

Rivar
Vout_min_max Vref 1 31.5957 V In FIG.1 Ri is ( R1fix + Rpot ) in serie.
Rdvar

Current
if CCSF 220 pF

1 1
RCSF RCSF RCSF 1.9807 kΩ
20 cCSF fsw 23 CCSF fsw

Soft Start and Dead Time

The soft-start time generally is in the range of 25 to 100 clock cycles.

If 50 clock cycles at a f-kHz switching

rate is selected, the soft-start time is: t

1 RT
t Rss
fsw 0.164 kΩ
50
1
50 0.5011 ms
t fsw
Css 50 3.0556 μF
Rss
Rss Css 0.5011 ms

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The outline schematic is shown in FIG. 1

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