Gata comuption “uy Logic Gates & Truth Tables Logie Gates tocie gates are the basic building Proce of digital systems or coms that nave ot least one (and Usually more) input and oe oo Cas true and false. In computing, false or ious Taare Inpor ce Presented pnd db asic circuits BSiput valves are the logical val ‘fue of high. Logic gates nonetheless, h ;, have no memor TY So the v0 our Ut is She 1 is indicative of dependent on the ‘current state of the input. vie uavoty consider three basic Kinds of gates! AND Gates, OR Gates, and NOT G fs ates (or in Verters) truth Tobles run tobles map or demonstrate the intemal logi ic of the part Table combinations of inputs and the rest Mt eon tc oct ultant output of the 5 aioe tn pecific gate. he differey . ntAnd Gates an AND gate can have any numberof inpus bul only one output. The output i 1 afin Inputs are Totherwiseit'.0 (fase). Thisis demonstrated in he Muth table. 1 (0) tan he ano er BORD pote with two inpuls looks lke this: Boolean function for this set of inputs is ain fo $0 Ab eis equal to xAND y) Figure 12: AND Gate ‘AND Gate Truth Tobie INeuTs oRGotes FEED ‘An OR gate cen have ony number of npuls bul only one output. The output is | {tue} f any of the inputs fs high or 1, otherwise the output is 0 (false). T he truth Ino ike this: The Bootean function is witten as: 2= AeB The '#' sign means logical OR, table for on OR gate with two inputs a nat [OR Gate Truth Tobie INPUTS [OUTPUTS = AL 6 | LAs) ° Figure 13: OR Gote ow noo Horta NOT Gates (Inverters) ANOT gate has only one input and one output. The inverter inverts the incoming input signal to the ‘opposite signal. Hence, ifthe input signal s22r0 after passing th {els complement value of 1. On the other hand, i he input i (0). he truth table for an inverter looks lke this: Boole Figure 14: NOT Gate }an func NOT Gate Truth Table hrough this gate, the output isinveried, is then the outputs inverted to ze10 ionis written as: A= "A (not ») Taput [Output A ~ 0 7 1 0 These are the three basic gates used in computer architecture: they however, can be combined to make other gates with different functionality such os NAND, NOR or Exclusive OR (EX-OR] and Exclusive: NOR (EX-NOR)Gote nthe output. The AND to with an inverter on the OUtpUt.The NAND gj 1 of on AND 200 ut, We represent thi By placing ge ‘Anan gote b.600 2rpiements he ouput. Wo roe Pree Stay to pul ANDY at rom te AND OO “ Siput torent a ve cogromtertne wann antes me vpn ne fro aNd gale ex Nat up yy rnenuncnetohe aw BU Cano wens F= (AB) OF o Tre ered: Te Boe : NAND Gate Tuth Tobie 2 INPUTS | OUTPUTS i AT S| 2x) a a oj 1 pure 18:NAND Gate of eco NoR Gate weer mest an oF ae inonINGIt 20 CD We eprint i + conf ne OR gale. The logical gate diagram forthe NOR gate is cing g eros on ecules heim e one h@OR Gale excep that ol ute voves rat ut valves nee he uh ble f ne 2eo. The uth ode To The NOR gale Wshown below, NPE, Figure Té: NOR Gate 7 = [oft i a ifm | The Boolean function s written as: function is written as: is 0 {false}. The Boolean T= ((AB'}+(‘AB))ORZA B [Exclusive OR Gate Truth Tabie] ome Figure 17: Exclusive OR Gatefxclusive NOR Gate high output only duce 9 >=) te wil pr ‘wnere (8 The Eckve NOR gate tho vere of he EX-OR gale. Me Cray hos MPUIS wen both Inputs. the same. san EX-OR gate Ah O” dnd one OUIDU. The Boolean foneton kwriltan Of THAR] IAD) ORTEA > roth comet Faqre 18 Exclusive NOR Gate Combinational Circuits ee ots DOSE logical blocks vied to construct cigital cuits 0 Roma Beater Usefulness and serve higher functions. Combinational "edie expressions ond truth fables trom the base goles. ey ed by combing the ra is oe daigned using can create ehcocen a ne Det lie gates, we create combined cuits ond from those we ‘encoders. multiplexers, demuliplexers ond ede: The characteristics of combinational circuits ore: The Combinational crcuit does not contain or behave ike memory. * TRS gute of combinational circu is dependent on input signals. ts current stale i not ependent on past inputs, ' ‘A combinational circuit can have n numberof inputs ond m number of outputs. Block diagrams con be used in generalsation ofthe circuit In order 10 construct @ combinational there ore four inputs then the uth tab thet pro Cieuit, the output i a function of is inputs. For exemple. if e willbe 24 posse combinations and the unique combinations 1UCe a high Output wil be discrete functions from these posible combinations Combinational circuit can be consttuctedin he following ways directly from the truth table or rom {2 Boolean function, Construction of Combinational Crcuit 1. Each inputs assigned a letter, asi the output 2. Write the Boolean function ram ine th table 3. Construct the combinational czcut fm the derived Boolean funetionFor example, even the fofowing Boolean function contuct he combinational ey Re'AC#D tere. we oteoty se that theta are Hee designated inpuls A. C ond © and one write ouiput fa func ofthe inputs. These inpuls wil be sent Trough ee CoE haba produce the output R. ‘Guile gayetea The truth table for the function i below: Lope |e | Reise nas es Or ong Leto te : toa 0 Then the resi of ANDING the inverted input ofA. ( 'A) with input issen with input 0 to achieve R= "AC +D wth input C.'AC]. sent through on OR gas Example 2 Given the following truth table, construct the combinational circuit, a Note, = x'ye- ye +aye oye Next we constuct the Circuit from the function derived, when F i highyet ya FEEDBACK: fryersHalf Adder (HA) gure 19: Logic diagram, Hat adder Figure 20: Block diagram, Hott Acer (Cut hot eo, nade toeveicame the weoknesat ne BPrevious circuit. the new inoutis devant Block diagram of Ful AdderLogic diogram of Ful Adder Multiplexors (MUX) pats ond ‘Amuliplexor's 9 combinationel ckcuit which selects one of several analogue O° OV% ore 2 input tines to a muitiolexer. then the multiplexer has selec ines which are used 10 SOIC ine desir signal o send the ouput A multiplexers ako known os a data selector. They OS A ncrionalty 19 of daital components such os the CPU and GPUS, They ao provide IRE GENET og felecommunication networks where they alow a specie omount of nformatien ey ns and even a particular communication channel. Mliplexos can come wih wth o Way Se with an odcitional input ne called an enable ine. The citferentIypes of sto 2:1 mulfiplexor (2 input lines to 1 output ine} 4:1 mutfiplexor (4 input lines fo 1 output ine) 16:1 mutiplexor (16 input lines fo 1 output ine) 32:1 muliplexor (32 input ines fo 1 output ine) _y» sl» 0 or Figure 21: Logic dlagram 4:1 MUXBlock diagram of 411 MUX without an Enable ine iTable fora 4x Mux — Selection [ouput eel Lines soifisy |v : fo [b0 wo fo 1_|os Encoders 5 e format to cnother. oten inmost Of fransiation or betoys fot snes ‘ ‘ransmitied, he e The encoder prockices any ges aesPencin to then Scere tigi worg, 3 3. & i a cal Of 4 to 2iine Encodey oDecoders A.decoder'sa device or cuit wn snereoy tov ut which evens he operation of on encoder etBEM pu eS gnalintomation 1. combinational cui tnt converts binary tration FO ce eimosimumol Pungue Sapo 1 asare sr the decoder doesnot havea dati wane ne oa +H ——— Se T Sequential Circuits Flip-Flops Digital circuits that ore constructed, are from combining the Ioaic a0 sequential ckcuts ore p-hps. props are ra memory bistable Sev Count operations Wares dota ond smulcte cert orhmefe ober Gnd vizon, Just os gates were bul! fom Fens, ip Hops ana IOICNES ECT opera Baste gates Fp ops afer em combraonl erin that, these PRS Of ie as lock Ub. Fp Rope alo possess o memory element which sexes © previo {um ulimately determines fhe output athe cre pe lement o The value thot the memeny ofthe Fip-op retin cor he sate of sequent element Fip-Fop. since tne merery computer jst fie, the br sequence ibe firite, thot totes the oust, The sequent component wil move trough afte number ofS Sn the Sequence of nous, Sequential cule le refered To os inte-state machines. “Sequential circuits ore typified os ether synchronous cr asynchronous, Asynchronous sequential crcult. are circus that change the output valves as a result fo a change ‘or changes in the input values whenever they happen fo o¢cur, soes apace ameter rae ote meroclock equencyY ‘Viclock period. ioe yo Wigaered. they wanes QandO ss $R IK. Tan id D. By includir Kn eaters couse Can be beats rere 72 10 NPOE, rip-FloP rete conn of the OURS timed sync! Counter: sR Fip-FIOP motes! possible erent element and sole eg goles back To the olor NO of oo rede eee NOR gate ne 50 Fi HOP HCY Tre frcted BY EST, the oulDu! for RESET 19 er and these are 'M* apis of oro be held in memory the the task Jn 8 S- Flip-Flops woul Ud be ney eden t, n qond ‘a ond ine vere complement J Ge 1 then '@ =o erinput SHIH ine clock puse's tiggered- sponse s HIGH (1 put Qe ok is triggered nines then ov! (1), when the © rane Reser inout 6 HIGH Te gutput @ 8 LOW (0) ip-fioe. he serand RESETINP UIC ote thotinan SR oth be HIGH (1: ise is Hi Block diagram of &-8 Fp ‘onnot gered. he Flip-Flop aoe able. 9p goesinto what is ces bed irpotninpuisore HG ore sate where MeO fon naeterinJA Fp-Flop, Master Stave. The LK F, the most versa ‘rom the output of second 1—DH a ‘Circuit Diagram using NOR Gates of JK Fip-Flop The characteristic equation of he JK Flip 00 f: One Flip-Flop (Delay Flip-Flop) Block Diagram oF Graphic Symbol of 0D Fp Hop Delay Flip-Flop oD Flip-flops a single input FF that ‘san altered $ Fip-Fiop, Mol Not NAND gates connected between the S ond Rinpuls An inven —)e ‘Also between the S and R inputs.tt he delay Fis cated such due fo the “dey” thal accustom input fo outers Me MPM oto is ‘ransmitted to the output alter a period of time has elopsed. lever bo idontica, S.ond Rinputs wi be the complements of each other, therefore tnotinpul Wi 1. wil never occur ro adostod state srespective ot 1 CAR S=ReOors= Some fiip-lops have: r lops have asynchronous inputs that coerce he Flip-OP OG ety, which Behave ko the CLK and b inputs, These inputs typically labled PRS (preset the set ond reset inputs on an SR latch, Circuit Diagram 0 Flip-tlop . Lore 5 "O cared R wn inge state of the: device. Tea a ee) angie Inout ats ued fo change Block Diagram 1 Fip-Fop oP] ovell fo] o ofapt Fo Registers ital processorsuch t their core, are “Aregiteris o smal area of highspeed memory location available os part of a i reat Regiters con be accessed more quickly than main memory. Registers o cJoup of connected Flip-Flops. Each Fip-Flop stores one bit, hence a r-bit register consists of n cerehted Flip-Flops which consequentialy con store a n-bil word. There are different types of regifers One such so sit register which tokes advantage of the Fip-Fop's ability when connected, fo shit data from one Flig-#lop to the nex}, thereby eaming its name. ;ooo [accumuiators Conational Regites_— [constant Regstes co Torler compuling systems had only one. They ore used to execute shi ce contacts operators ney ware ropioced by Golo wogher ee or toate ee ‘Ako called sogment or index registers. hey are used to segment memory. A egax regkler Ina) computer's CPU fs @ processor register used for Aadiving operand addresses during the execution of programming sees fons. They are abo closslied a: a hardware element which holds @ renter hal may be ether added to or subtracted from the address portion cory eompulerinstuction 1o form an effective oddress oid ruth values offen used fo deterrrine whether some instructions should Or should not be executed. old read only (constant) valves. They are read-only register. They conta) ol eretont valves of Eand pi. They can contoin adaitonal bis hat alow Ie greater computational accuracy. miro certain aspects of processor He J program counter, its used 10 co contralRegites: | procedures Genel PurP0% | can store bath cota ond adresses Regsies sesjontegier _|ods Thensvetion curenty PETS executed iwemory Butler ores data being Worserted fo and rom immediate access storage Reais: [MBR) er bao ike abuferand noi anying hal oes To The memory. ready verano, |lrtne processor tute. contains ete 310° fetch from RAM. MDR holds | {0 Ihe rc snbetoreit goes othe decoder. MDR © 2-way register !noy | theinlorrime dala To be wtlien info or read fom of the addressed contains Tike dais is fetched from meme i's placed into the MOR. in rocoto aration, the data fo be written s placed into the MDR from | oie Cou regi, which then puls the data into memory. ame Kates ha sores memory addres of data fo be fetched Tisregiter& see 1 womary Acces _[fccess dato and isctions om memory ding the exocution phase of instruction. | Address Registers | they axe used fo store the address of specific memory locati | memory locations that ore Tree by insituctions that ore being executed by the CPU. They are also vied fo come he ou pyscalaaes: of memory ocotions ang provides assstance in the dynamic memory allocation process Gnd vitual memory. meee ae eee Shi Regier Tniareclional shill regier sil ne datain oniy one: | Ure ition bom aston, muritescl reget moves ate site Ogrections and loads the data paral ister moves data fpecirpow | vay hots the rosrom counter egies peeRegisters are a re wed to execute certain cofihmetic and logical ‘adem {cule certain types of actions such os operat oa crc ate using he Von Newmon architecture, postets 0 SPECS YES of regster caja fe ich is Used to axis! the processorin locating the nex! execuIaPle $24 Fnstructions Spe ‘eGisters have four operational approaches: hi + Setial input Serio! Output (S80) + Serial input Poratiel Output (SIP) + Paraliel input Serial Output (PISO) * Parallel input Porale! Output {PPO} Parallel: all the bits are loaded at the same time into reasler Setiat one bit ato ime into rege Seriol input Serio output (4-8 S80 Shit, Register sour to 1d seiaty the outbut HOM each succesigg tn this type of register the data & entered and exttocted Flip-Rop is the input fo the next. tou fons connectes. he Loos sgntican! BSB wil Be sored ig For example. if there axe fou Fp-flops connected. Te OTC, ic transtested 10 Fip-Hop 3 fst on st Si -ant Bit MSB, in Flia-FIOP. is entered the first value. eae Oanet ne Mot Sem fe clock puse wnen the nes i lve held Flip-Flop 3 willbe transferred to Flip-Flop 2. etc- p> @ re sec ruc Gt eps P) » cot nj tc woe bs anored ely te le ag i oe ie hs hon Seba Ce oe i cee oleae nach a wil be needed, orate! Input Parallel Output (4-it PIO Shit Register In his mode, one clock pulke is needed to load all he bits of an mbit binary word, The 4-bit binary input 80, 61, 82. B3 is applied to the data inputs DO, D1. D2, D3 respectively of the four Flip-Flops, When a negative clock edge is appiied, the input bits ae loaded instantaneously into the Fip-Flops where they wil aso flow trom the outputs, Be Da 0,@ 2 @ cr cP cP cPUniversal Shit Register Ashi tegster that shifts the data in only one direction scaled a unidiectional sift register. A sit reaste! thot sis the dat in both cirectionss called « bi-directional shit register. A shi regex that loads the data parallely a5 well os fo shi the data in both drections [lef and right) fslabeled Gs & Universal shill register. Counters ‘Acounter is another ype of sequential cicut. It &@ st of connected flp-Flops which respond 10 @ lock signal. The counters wsed to store the number of mes a particular process is executed UBON g.clock puke, Modus. refers to the total number of counts @.counter can count fo, modulo on the other hand, refers o the bi Count of the courier Fer excmple, the total count for a three-stage counter i (bose 10). This s because the maximum number that con be represented with 3 bls is 8, Korn 000 fo 111 and moduio-Bis used 10 express thatthe counter hos 3 bits There are two major types of clock signals: ‘Asynchronous or pple counters Synchronous counters HIGH cr cr Figure 23: 2.bit Asyncironous counter ‘Asynchronous counters ‘Asynchronous means no synchronization, of not occuring atthe same time. Asynchronous counters ‘Fe used for controling the operation and fiming by using a clock pulse only when the previous ‘operation is completed, as opposed to intermittent timing, Synchronous counters When © counter has the clock pulses applied sequentialy to athe fip-lops, then tis termed as synchronous counter os hey oe tigger rom tne some clock pute fn pera ees. HGH cy cr. Figure 24: 2bit Synchronous counter© Describe the function of an adder. The full adder are 2 connected half adders whose Purpose Is fo Cany out arithmetic operation of adding of three one bit numbers, S Astill teaister typically is used to convert between parallel and serial, in one direction oF another b. A counter is used for counting the specific occurence of a particular event. Three select lines To decode the memor "Y address of the memory location requested or sent from the micro- processor I would not, a 64-bit microprocessor can handle greater amount of RAM and can handie © greater amount of data at once than a 32-bit processor