MAJLIS ARTS

AND SCIENCE
COLLEGE,
PURAMANNUR

Computer
Science
Department
DBMS – MODULE-1

Majlis Arts and Science College,

Puramannur affiliated to the University
of Calicut, approved by the
Government of Kerala.
 UNIT-III

1. What is the counter?How is it designed?

Counters are primarily used to keep track of events.

Example:
MVI B,00H ; INITIALIZE COUNTER
LOOP: DCR B ; COUNT=COUNT-1
MOV A,B ; MOVE COUNT TO ACC
OUT 01H ; DISPLAY IT AT PORT 01H
JNZ LOOP ; IF COUNT>0 REPEAT

2. What is time delay?

Delays are used to set up accurate delays between events.

3. Explain programming techniques and tools.

Programming Techniques : Looping, Counting, Indexing, Counters and Time Delay.
Looping:
It is used to instruct the microprocessor unit to repeat tasks.A loop is set up by instructing
MPU to change sequence of execution and perform the task given.This is accomplished by
Jump Instructions.
Loops are of 2 types:
• Continuous(repeats a task continuously)
• Conditional(repeats a task until certain data conditions are met)
Indexing:
It means counting or referencing objects with sequential numbers.Data bytes are stored in
memory location,and those data bytes are referred to by their memory location.
Counters:
This programming technique uses INR or DCR instructions.A loop is established to update
count and each count is checked to determine whether it has reached the final number and if
not reached,then the loop is repeated.
Time Delay:
It is a similar programming technique used to set up a counter. Register is loaded with a
number depending on the time delay required and then the register is decremented until it
reaches zero.
Register works on the principle of time delay within setting up a loop with a conditional
jump instruction and the loop causes delay depending upon the lock period of the system. It
is achieved by two methods:
• Using a register
• Using a register pair.

Timer Delay Using NOP Instruction:

NOP instruction does nothing but takes 4T states of processor time to execute. So by
executing NOP instruction in between two instructions we can get delay of 4 T-state

Timer Delay Using Counters:

Counting can create time delays. Since the execution times of the instructions used in a
counting routine are known, the initial value of the counter, required to get specific time
delay can be determined.

Timer Delay Using Nested Loops:

In this, there are more than one loops. The innermost loop is same as explained above. The
outer loop sets the multiplying count to the delays provided by the innermost loop.
4. What is a subroutine?
• A subroutine is a small program written separately from the main program to perform a
particular task that you may repeatedly require in the main program. Essentially, the concept
of a subroutine is that it is used to avoid the repetition of smaller programs.
• Subroutines are written separately and are stored in a memory location that is different from
the main program. You can call a subroutine multiple times from the main program using a
simple CALL instruction. And a RET instruction is used at the end of the subroutine to
return to the main program.

5. Describe the subroutine related instructions of the 8085 microprocessor.

The 8085 microprocessor has 4 instructions to implement subroutines. The unconditional
and conditional CALL and RET instructions.
• In unconditional CALL, when a subroutine is called the content of the PC is stored on the
stack and the program execution is transferred to the subroutine address. When the
unconditional RET instruction is executed, the memory address stored on the stack is
retrieved and the sequence of execution is resumed in the main program.
• The conditional CALL and RET instructions are based on the four flag register
conditions-S,Z,CY and P. The conditions are tesed by checking the respective flags. In
conditional CALL , execution control is transferred to the subroutine if the condition is met.
In conditional RET instruction, the control returns to the main program if the condition is
met, otherwise the sequence in the subroutine is continued.
Conditional CALL statements
• CC Call at address if cy (carry flag) = 1
• CNC Call at address if cy (carry flag) = 0
• CZ Call at address if ZF (zero flag) = 1
• CNZ Call at address if ZF (zero flag) = 0
• CPE Call at address if PF (parity flag) = 1
• CPO Call at address if PF (parity flag) = 0
• CN Call at address if SF (signed flag) = 1
• CP Call at address if SF (signed flag) = 0
The conditional return (RET) statements
• RC Return from subroutine if cy (carry flag) = 1
• RNC Return from subroutine if cy (carry flag) = 0
• RZ Return from subroutine if ZF (zero flag) = 1
 • RNZ Return from subroutine if ZF (zero flag) = 0
• RPE Return from subroutine if PF (parity flag) = 1
• RPO Return from subroutine if PF (parity flag) = 0
• RN Return from subroutine if SF (signed flag) = 1
• RP Return from subroutine if SF (signed flag) = 0
After the completion of the subroutine, the main program begins from the instruction
immediately following the CALL instruction.

6. What is stack?

The stack is a reserved area of the memory in RAM where we can store
temporary information. Interestingly, the stack is a shared resource as it can
be shared by the microprocessor and the programmer. The programmer
can use the stack to store data. And the microprocessor uses the stack to
execute subroutines.
The 8085 has a 16-bit register known as the ‘Stack Pointer.’ its function is
to hold the memory address of the stack. This control is given to the
programmer. The programmer can decide the starting address of the stack
by loading the address into the stack pointer register at the beginning of a
program.
The stack works on the principle of First In Last Out. The memory location
of the most recent data entry on the stack is known as the Stack Top.

7. Describe the procedure to implement a stack using instructions of 8085 with an illustrative
example.
The stack works on the principle of First In Last Out. The memory location of the most
recent data entry on the stack is known as the Stack Top.
Two operations used to control the movement of data into a stack and from a stack.
These two instructions are PUSH and POP.
PUSH – This is the instruction to write information on the stack. POP – This is the instruction
to read information from the stack.
There are two methods to add data to the stack: Direct method and Indirect method.using
either LXI or the SPHL instruction
In the direct method, the stack pointers address is loaded into the stack pointer register
directly. Using LXI instruction
In the indirect method, the stack pointers address is loaded into the stack pointer register via
another register pair. Using SPHL

In the direct method, the stack pointers address is loaded into the stack pointer register
directly.
LXI SP, 8000H
LXI H, 1234H
PUSH H
POP D
HLT
Explanation of the code
 LXI SP, 8000H – The address of the stack pointer is set to 8000H by loading the number into
the stack pointer register. LXI H, 1234H – Next, we add a number to the HL pair. The most
significant two bits will enter the H register. The least significant two bits will enter the L
register.
PUSH H – The PUSH command will push the contents of the H register first to the stack.
Then the contents of the L register will be sent to the stack. So the new stack top will hold
34H.
POP D – The POP command will remove the contents of the stack and store them to the DE
register pair. The top of the stack clears first and enters the E register. The new top of the
stack is 12H now. This one clears last and enters the D register. The contents of the DE
register pair is now 1234H. HLT – HLT indicates that the program execution needs to stop.

In the indirect method, the stack pointers address is loaded into the stack pointer
register via another register pair.
LXI H, 8000H – The number that we wish to enter into the stack pointer, 8000H, is loaded
into the HL pair register.
SPHL – This is a special command that we can use to transfer data from HL pair to Stack
pointer (SP). Now, the contents of the HL pair are in the SP.
LXI H, 1234H – Next, we add a number to the HL pair. The most significant two bits will
enter the H register. The least significant two bits will enter the L register.
PUSH H – The PUSH command will push the contents of the H register first to the stack.
Then the contents of the L register will be sent to the stack. So the new stack top will hold
34H.
POP D – The POP command will remove the contents of the stack and store them to the DE
register pair. The top of the stack clears first and enters the E register. The new top of the
stack is 12H now. This one clears last and enters the D register. The contents of the DE
register pair is now 1234H.
HLT – HLT indicates that the program execution needs to stop.

8. What are software interrupts?

Software Interrupt is invoked by the use of INT instruction. This event
immediately stops execution of the program and passes execution over to the
INT handler. The INT handler is usually a part of the operating system and
determines the action to be taken. It occurs when an application program
terminates or requests certain services from the operating system.
Software interrupts can be classified into two types: 1. Normal Interrupts. 2.
Exception
They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

9. What are hardware interrupts?

Hardware Interrupt is caused by some hardware device such as a request to
start an I/O, a hardware failure or something similar. Hardware interrupts were
introduced as a way to avoid wasting the processor’s valuable time in polling
 loops, waiting for external events.For example, when an I/O operation is
completed such as reading some data into the computer from a tape drive.
Hardware interrupts can be classified into two types: 1. Maskable Interrupt. 2. Non
Maskable Interrupt.
They are  INTR, RST 7.5, RST 6.5, RST 5.5, TRAP

10. Describe various interrupts of 8085 microprocessors.

When microprocessor receives any interrupt signal from peripheral(s) which are
requesting its services, it stops its current execution and program control is transferred
to a sub-routine by generating CALL signal and after executing sub-routine by
generating RET signal again program control is transferred to main program from
where it had stopped.
When a microprocessor receives interrupt signals, it sends an acknowledgement
(INTA) to the peripheral which is requesting for its service.
Interrupts can be classified into various categories based on different parameters:
Hardware Interrupts: When microprocessors receive interrupt signals through pins
(hardware) of microprocessor, they are known as Hardware Interrupts. There are 5
Hardware Interrupts in 8085 microprocessors.
They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Software Interrupts:  are those which are inserted in between the program which
means these are mnemonics of microprocessor. There are 8 software interrupts in the
8085 microprocessor.
They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

Vectored Interrupts: Vectored Interrupts are those which have fixed vector address
(starting address of sub-routine) and after executing these, program control is
transferred to that address.
Vector Addresses are calculated by the formula 8 * TYPE.
INTERRUPT VECTOR ADDRESS
TRAP (RST 4.5) 24 H
RST 5.5 2C H
RST 6.5 34 H
RST 7.5 3C H
For Software interrupts vector addresses are given by:
INTERRUPT VECTOR ADDRESS
RST 0 00 H
RST 1 08 H
RST 2 10 H
RST 3 18 H
RST 4 20 H
RST 5 28 H
RST 6 30 H
 RST 7 38 H
Non-Vectored Interrupts: are those in which the vector address is not predefined.
The interrupting device gives the address of the sub-routine for these interrupts. INTR
is the only non-vectored interrupt in an 8085 microprocessor.
Maskable Interrupts: are those which can be disabled or ignored by the
microprocessor. These interrupts are either edge-triggered or level-triggered, so they
can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085
microprocessor.
Non-Maskable Interrupts: are those which cannot be disabled or ignored by
microprocessor. TRAP is a non-maskable interrupt. It consists of both levels as well
as edge triggering and is used in critical power failure conditions.

11. Which interrupt of the 8085 has the highest priority?

Priority of Interrupts –
When microprocessor receives multiple interrupt requests simultaneously, it will
execute the interrupt service request (ISR) according to the priority of the interrupts.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding interrupting
source is called an ISR.

TRAP It is a non-maskable interrupt, having the highest priority among all interrupts. By
default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and
sends the data to backup memory. This interrupt transfers the control to the location 0024H.

RST7.5 It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 003CH address.

RST 6.5 It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 0034H address.
RST 5.5 It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.

INTR It is a maskable interrupt, having the lowest priority among all interrupts. It can be
disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
● The microprocessor checks the status of the INTR signal during the execution
of each instruction.
● When the INTR signal is high, then the microprocessor completes its current
instruction and sends an active low interrupt acknowledge signal.
● When instructions are received, then the microprocessor saves the address of
the next instruction on stack and executes the received instruction.

12. Explain SIM and RIM instructions .

Instruction for masking or unmasking of Interrupts under program control –

Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are
enabled following the execution of the next instruction followed by EI. No flags are
affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to enable the interrupts again (except TRAP).

Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop
hence disabling all the interrupts. No flags are affected by this instruction.

Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST
7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output data
via the Serial Output Data (SOD) line. First the required value is loaded in
accumulator then the SIM will take the bit pattern from it.

Read Interrupt Mask (RIM) – This instruction is used to read the status of the
hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte
 which defines the condition of the mask bits for the interrupts. It also reads the
condition of SID (Serial Input Data) bit on the microprocessor.

13. What is a peripheral device?

To communicate with the outside world microcomputers use peripherals (I/O devices).
Commonly used peripherals are: A/D converter, D/A converter, CRT, printers, Hard disks, floppy
disks, magnetic tapes etc. Peripherals are connected to the microcomputer through electronic
circuits known as interfacing circuits.

14. What are the features of 8255A?

The prominent features of 8255A are as follows −
● It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
● Address/data bus must be externally demux'd.
● It is TTL compatible.
● It has improved DC driving capability.

15. Explain PPI or 8255A with block diagram .

A programmable peripheral interface(PPI) is a multiport device. The ports may be programmed in

a variety of ways as required by the programmer. The device is very useful for interfacing
peripheral devices. The term PIA, Peripheral Interface Adapter is also used by some
manufacturers. 

The Intel 8255 is a programmable peripheral interface (PPI). It has two versions, namely the Intel
8255A and Intel 8255A-5. General descriptions for both are the same. There are some differences
in their electrical characteristics. Its main functions are to interface peripheral devices to the
microcomputer.

8255A
The 8255A is a general purpose programmable I/O device designed to transfer the
data from I/O to interrupt I/O under certain conditions as required. It can be used
with almost any microprocessor.
 It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured
as per the requirement.

Ports of 8255A
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
● Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
● Port B is similar to PORT A.
● Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A
and upper PORT C. Group B includes PORT B and lower PORT C. These two groups
can be programmed in three different modes, i.e. the first mode is named as mode 0,
the second mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes
8255A has three different operating modes −
Mode 0 - Simple Input/output: The 8255 has two 8-bit ports (Port A and Port B) and two 4-bit
ports (Port Cupper and Port Clower). Each port can be programmed in either input mode or
output mode where outputs are latched and inputs are not latched. Ports do not have
interrupt capability.
Mode 1-Strobed Input/output: Mode 1 is strobed input/output mode of operation. The Port A
and Port B both are designed to operate in this mode of operation. When Port A and Port B are
programmed in Mode 1, six pins of Port C are used for their control.
Mode 2 -Bidirectional Port: Mode 2 is strobed bidirectional mode of operation. In this mode,
Port A can be configured as the bidirectional port and Port B either in Mode 0 or
Mode 1. Port A uses five signals from Port C as handshake signals for data transfer.
The remaining three signals from Port C can be used either as simple I/O or as a
handshake for port B.
The following figure shows the architecture of 8255A −
 16. Describe the functional description of the pins in 8255A

 The functional description of the pins in 8255A.

Data Bus Buffer It is a tri-state 8-bit buffer, which is used to interface the
microprocessor to the system data bus. Data is transmitted or received by the buffer as per the
instructions by the CPU. Control words and status information is also transferred using this
bus.

Read/Write Control Logic This block is responsible for controlling the

internal/external transfer of data/control/status word. It accepts the input from the CPU
address and control buses, and in turn issues commands to both the control groups.
CS It stands for Chip Select. A LOW on this input selects the chip and enables the
communication between the 8255A and the CPU. It is connected to the decoded address, and
A0 & A 1 are connected to the microprocessor address lines.

Their result depends on the following conditions −

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

WR It stands for write. This control signal enables the write operation. When this signal
goes low, the microprocessor writes into a selected I/O port or control register.

RESET This is an active high signal. It clears the control register and sets all ports in the
input mode.

RD It stands for Read. This control signal enables the Read operation. When the signal is
low, the microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1 These input signals work with RD, WR, and one of the control signal.
Following is the table showing their various signals with their result.

A1 A0 RD WR CS Result

0 0 0 1 0 Input Operation
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

17. Explain different operating modes in 8255A.

There are 2 modes in 8255:

● Bit Set/Reset mode (BSR mode).

● Input/Output mode (I/O mode).

The two modes are selected on the basis of the value present at the D7 bit of the control
word register. When D7 = 1, 8255 operates in I/O mode, and when D7 = 0, it operates in the BSR
mode.
Bit set reset (BSR) mode – This mode is used to set or reset the bits of port C only,
and selected when the most significant bit (D7) in the control register is 0. Control
Register is as follows:

This mode affects only one bit of port C at a time because, as user set the bit, it remains
set until and unless user changes it. User needs to load the bit pattern in control register to
change the bit.
 Input/output mode (I/O) – This mode is selected when the most significant bit (D7)
in the control register is 1. This is further divided into three modes:

Mode 0 – Simple or basic I/O mode:

Port A, B and C can work either as input function or as output function. The outputs
are latched but the inputs are not latched. It has interrupt handling capability.

Mode 1 – Handshake or strobbed I/O:

In this either port A or B can work and port C bits are used to provide handshaking.
The outputs as well as inputs are latched. It has interrupt handling capability. Before
actual data transfer there is transmission of signal to match the speed of the CPU and
printer.
Example: When the CPU wants to send data to a slow peripheral device like a printer,
it will send a handshaking signal to the printer to tell whether it is ready or not to
transfer the data. When the printer is ready it will send one acknowledgement to the
CPU then there will be transfer of data through the data bus.

Mode 2 – Bidirectional I/O:

In this mode only port A will work, port B can either be in mode 0 or 1 and port C bits
are used as a handshake signal. The outputs as well as inputs are latched. It has
interrupt handling capability. Control Register is as follows:

The most significant bit (D7) is 1 for the I/O mode and 0 for the BSR mode.

D6 & D5It is used to set the port A mode.

D4 is used to tell whether port A is taking input or displaying the result. If it is 1 then it is
taking input otherwise displaying output.
D3 is used to tell whether port C higher bits are taking input or displaying the result. If it
is 1 then it is taking input otherwise displaying output.

D2 tells the mode of port B. If it is 0 then port B is in m0 mode otherwise in m1 mode.

D1 is used to tell whether port B is taking input or displaying the result. If it is 1 then it is
taking input otherwise displaying output.

D0 is used to tell whether port C lower bits are taking input or displaying the result. If it is
1 then it is taking input otherwise displaying output.

When 8255 microprocessor is reset, it will clear the control word register contents, setting
all the ports to input mode.

18. Explain 8254 programmable interval timer

8254 is a device designed to solve the timing control problems in a microprocessor. It
has 3 independent counters, each capable of handling clock inputs up to 10 MHz and
size of each counter is 16 bit. It operates in +5V regulated power supply and has 24
pin signals. All modes are software programmable. The 8254 is an advanced version
of 8253 which did not offer the feature of read back command.

8254 Pin Description

Here is the pin diagram of 8254 –

The basic block diagram of 8254 is:

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and
a control register.

It has 3 counters each with two inputs (Clock and Gate) and one output. Gate is used to
enable or disable counting. When any value of count is loaded and the value of gate is set(1),
after every step the value of count is decremented by 1 until it becomes zero.

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions −

● Programming the modes of 8253/54.

● Loading the count registers.

● Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O
mode, the RD and WR signals are connected to IOR and IOW, respectively. In the memory
mapped I/O mode, these are connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is
tied to a decoded address. The control word register and counters are selected according to
the signals on lines A 0 & A 1.

Depending upon the value of CS, A1 and A0 we can determine addresses of selected
counters.

CS A1 A0 SELECTION
0 0 0 C0

0 0 1 C1

0 1 0 C2

0 1 1 Control Register

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command
word, which specifies the counter to be used, its mode, and either a read or write operation.
Following table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2

1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

Applications –To generate accurate time delay,As an event counter,Square wave generator,
Rate generato rand Digital one shot

19. What is the DMA controller in 8085?

 DMA Controller is a hardware device that allows I/O devices to directly
access memory with less participation of the processor. DMA controller needs
the same old circuits of an interface to communicate with the CPU and
Input/Output devices.
DMA Controller temporarily borrows the address bus,data bus and
control bus from the microprocessor and transfers the data directly from the
external device to memory location and vice versa.

20. Explain 8237 DMA Controller with block diagram.

Intel 8237 is a direct memory access (DMA) controller, a part of the MCS
85 microprocessor family. It enables data transfer between memory and the I/O with reduced load
on the system's main processor by providing the memory with control signals and memory address
information during the DMA transfer.
The 8237 is a four-channel device that can be expanded to include any number of DMA
channel inputs. The 8237 is capable of DMA transfers at rates of up to 1.6 megabyte per second.
Each channel is capable of addressing a full 64k-byte section of memory and can transfer up to
64k bytes with a single programming.
A single 8237 was used as the DMA controller in the original  IBM PC and IBM XT. 
The 8237 operates in four different modes, depending upon the number of bytes transferred per
cycle and number of ICs used:

● Single mode In single mode only one byte is transferred per request. For every transfer, the
counting register is decremented and address is incremented or decremented depending on
programming. When the counting register reaches zero, the terminal count TC signal is sent to the
card.
The DMA request DREQ must be raised by the card and held active until it is acknowledged by
the DMA acknowledge DACK.

● Block transfer mode The transfer is activated by the DREQ which can be deactivated

once acknowledged by DACK. The transfer continues until end of process EOP (either internal or
external) is activated which will trigger terminal count TC to the card. Auto-initialization may be
programmed in this mode.
● Demand transfer mode The transfer is activated by DREQ and acknowledged
by DACK and continues until either TC, external EOP or DREQ goes inactive. Only TC or
external EOP may activate auto-initialization if this is programmed.
 ● Cascade Used to cascade additional DMA controllers. DREQ and DACK are matched with
HRQ and HLDA from the next chip to establish a priority chain. Actual bus signals are executed
by cascaded chips.
Memory-to-memory transfer can be performed. This means data can be transferred from one memory
device to another memory device. The channel 0 Current Address register is the source for the data transfer
and channel 1 and the transfer terminates when Current Word Count register becomes 0. Channel 0 is used
for DRAM refresh on IBM PC compatibles.
In auto initialize mode the address and count values are restored upon reception of an end of process
(EOP) signal. This happens without any CPU intervention. It is used to repeat the last transfer.
The terminal count (TC) signals the end of transfer to ISA cards. At the end of transfer an auto initialize
will occur configured to do so.

The internal registers used in the 8237 for data transfer are as follows:

● Base address register: To store the initial address from where data transfer will take place
● Base word count register: To store the number of transfers to be performed
● Current address register: To store the current address from where data is being transferred
● Current word count register: To store the number of transfers remaining to be performed
● Temporary address register: To hold address of data during memory-to-memory transfer
● Temporary word count register: To hold number of transfers to be performed in memory-to-memory
transfer
● Mode register: 8-bit register which stores the channel to be used, the operating mode, i.e. the transfer
mode, and other transfer parameters
● Command register: 8-bit register which initializes the channel to be used for data transfer
● Request register: 8-bit register used to indicate which channel is requesting for data transfer
● Mask register: 8-bit register used to mask a particular channel from requesting for DMA service
● Status register: 8-bit register used to indicate which channel is currently under DMA service and some
other parameters